clk-stm32f4.c 51 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Author: Daniel Thompson <daniel.thompson@linaro.org>
  4. *
  5. * Inspired by clk-asm9260.c .
  6. */
  7. #include <linux/clk-provider.h>
  8. #include <linux/err.h>
  9. #include <linux/io.h>
  10. #include <linux/iopoll.h>
  11. #include <linux/ioport.h>
  12. #include <linux/slab.h>
  13. #include <linux/spinlock.h>
  14. #include <linux/of.h>
  15. #include <linux/of_address.h>
  16. #include <linux/regmap.h>
  17. #include <linux/mfd/syscon.h>
  18. /*
  19. * Include list of clocks wich are not derived from system clock (SYSCLOCK)
  20. * The index of these clocks is the secondary index of DT bindings
  21. *
  22. */
  23. #include <dt-bindings/clock/stm32fx-clock.h>
  24. #define STM32F4_RCC_CR 0x00
  25. #define STM32F4_RCC_PLLCFGR 0x04
  26. #define STM32F4_RCC_CFGR 0x08
  27. #define STM32F4_RCC_AHB1ENR 0x30
  28. #define STM32F4_RCC_AHB2ENR 0x34
  29. #define STM32F4_RCC_AHB3ENR 0x38
  30. #define STM32F4_RCC_APB1ENR 0x40
  31. #define STM32F4_RCC_APB2ENR 0x44
  32. #define STM32F4_RCC_BDCR 0x70
  33. #define STM32F4_RCC_CSR 0x74
  34. #define STM32F4_RCC_PLLI2SCFGR 0x84
  35. #define STM32F4_RCC_PLLSAICFGR 0x88
  36. #define STM32F4_RCC_DCKCFGR 0x8c
  37. #define STM32F7_RCC_DCKCFGR2 0x90
  38. #define NONE -1
  39. #define NO_IDX NONE
  40. #define NO_MUX NONE
  41. #define NO_GATE NONE
  42. struct stm32f4_gate_data {
  43. u8 offset;
  44. u8 bit_idx;
  45. const char *name;
  46. const char *parent_name;
  47. unsigned long flags;
  48. };
  49. static const struct stm32f4_gate_data stm32f429_gates[] __initconst = {
  50. { STM32F4_RCC_AHB1ENR, 0, "gpioa", "ahb_div" },
  51. { STM32F4_RCC_AHB1ENR, 1, "gpiob", "ahb_div" },
  52. { STM32F4_RCC_AHB1ENR, 2, "gpioc", "ahb_div" },
  53. { STM32F4_RCC_AHB1ENR, 3, "gpiod", "ahb_div" },
  54. { STM32F4_RCC_AHB1ENR, 4, "gpioe", "ahb_div" },
  55. { STM32F4_RCC_AHB1ENR, 5, "gpiof", "ahb_div" },
  56. { STM32F4_RCC_AHB1ENR, 6, "gpiog", "ahb_div" },
  57. { STM32F4_RCC_AHB1ENR, 7, "gpioh", "ahb_div" },
  58. { STM32F4_RCC_AHB1ENR, 8, "gpioi", "ahb_div" },
  59. { STM32F4_RCC_AHB1ENR, 9, "gpioj", "ahb_div" },
  60. { STM32F4_RCC_AHB1ENR, 10, "gpiok", "ahb_div" },
  61. { STM32F4_RCC_AHB1ENR, 12, "crc", "ahb_div" },
  62. { STM32F4_RCC_AHB1ENR, 18, "bkpsra", "ahb_div" },
  63. { STM32F4_RCC_AHB1ENR, 20, "ccmdatam", "ahb_div" },
  64. { STM32F4_RCC_AHB1ENR, 21, "dma1", "ahb_div" },
  65. { STM32F4_RCC_AHB1ENR, 22, "dma2", "ahb_div" },
  66. { STM32F4_RCC_AHB1ENR, 23, "dma2d", "ahb_div" },
  67. { STM32F4_RCC_AHB1ENR, 25, "ethmac", "ahb_div" },
  68. { STM32F4_RCC_AHB1ENR, 26, "ethmactx", "ahb_div" },
  69. { STM32F4_RCC_AHB1ENR, 27, "ethmacrx", "ahb_div" },
  70. { STM32F4_RCC_AHB1ENR, 28, "ethmacptp", "ahb_div" },
  71. { STM32F4_RCC_AHB1ENR, 29, "otghs", "ahb_div" },
  72. { STM32F4_RCC_AHB1ENR, 30, "otghsulpi", "ahb_div" },
  73. { STM32F4_RCC_AHB2ENR, 0, "dcmi", "ahb_div" },
  74. { STM32F4_RCC_AHB2ENR, 4, "cryp", "ahb_div" },
  75. { STM32F4_RCC_AHB2ENR, 5, "hash", "ahb_div" },
  76. { STM32F4_RCC_AHB2ENR, 6, "rng", "pll48" },
  77. { STM32F4_RCC_AHB2ENR, 7, "otgfs", "pll48" },
  78. { STM32F4_RCC_AHB3ENR, 0, "fmc", "ahb_div",
  79. CLK_IGNORE_UNUSED },
  80. { STM32F4_RCC_APB1ENR, 0, "tim2", "apb1_mul" },
  81. { STM32F4_RCC_APB1ENR, 1, "tim3", "apb1_mul" },
  82. { STM32F4_RCC_APB1ENR, 2, "tim4", "apb1_mul" },
  83. { STM32F4_RCC_APB1ENR, 3, "tim5", "apb1_mul" },
  84. { STM32F4_RCC_APB1ENR, 4, "tim6", "apb1_mul" },
  85. { STM32F4_RCC_APB1ENR, 5, "tim7", "apb1_mul" },
  86. { STM32F4_RCC_APB1ENR, 6, "tim12", "apb1_mul" },
  87. { STM32F4_RCC_APB1ENR, 7, "tim13", "apb1_mul" },
  88. { STM32F4_RCC_APB1ENR, 8, "tim14", "apb1_mul" },
  89. { STM32F4_RCC_APB1ENR, 11, "wwdg", "apb1_div" },
  90. { STM32F4_RCC_APB1ENR, 14, "spi2", "apb1_div" },
  91. { STM32F4_RCC_APB1ENR, 15, "spi3", "apb1_div" },
  92. { STM32F4_RCC_APB1ENR, 17, "uart2", "apb1_div" },
  93. { STM32F4_RCC_APB1ENR, 18, "uart3", "apb1_div" },
  94. { STM32F4_RCC_APB1ENR, 19, "uart4", "apb1_div" },
  95. { STM32F4_RCC_APB1ENR, 20, "uart5", "apb1_div" },
  96. { STM32F4_RCC_APB1ENR, 21, "i2c1", "apb1_div" },
  97. { STM32F4_RCC_APB1ENR, 22, "i2c2", "apb1_div" },
  98. { STM32F4_RCC_APB1ENR, 23, "i2c3", "apb1_div" },
  99. { STM32F4_RCC_APB1ENR, 25, "can1", "apb1_div" },
  100. { STM32F4_RCC_APB1ENR, 26, "can2", "apb1_div" },
  101. { STM32F4_RCC_APB1ENR, 28, "pwr", "apb1_div" },
  102. { STM32F4_RCC_APB1ENR, 29, "dac", "apb1_div" },
  103. { STM32F4_RCC_APB1ENR, 30, "uart7", "apb1_div" },
  104. { STM32F4_RCC_APB1ENR, 31, "uart8", "apb1_div" },
  105. { STM32F4_RCC_APB2ENR, 0, "tim1", "apb2_mul" },
  106. { STM32F4_RCC_APB2ENR, 1, "tim8", "apb2_mul" },
  107. { STM32F4_RCC_APB2ENR, 4, "usart1", "apb2_div" },
  108. { STM32F4_RCC_APB2ENR, 5, "usart6", "apb2_div" },
  109. { STM32F4_RCC_APB2ENR, 8, "adc1", "apb2_div" },
  110. { STM32F4_RCC_APB2ENR, 9, "adc2", "apb2_div" },
  111. { STM32F4_RCC_APB2ENR, 10, "adc3", "apb2_div" },
  112. { STM32F4_RCC_APB2ENR, 11, "sdio", "pll48" },
  113. { STM32F4_RCC_APB2ENR, 12, "spi1", "apb2_div" },
  114. { STM32F4_RCC_APB2ENR, 13, "spi4", "apb2_div" },
  115. { STM32F4_RCC_APB2ENR, 14, "syscfg", "apb2_div" },
  116. { STM32F4_RCC_APB2ENR, 16, "tim9", "apb2_mul" },
  117. { STM32F4_RCC_APB2ENR, 17, "tim10", "apb2_mul" },
  118. { STM32F4_RCC_APB2ENR, 18, "tim11", "apb2_mul" },
  119. { STM32F4_RCC_APB2ENR, 20, "spi5", "apb2_div" },
  120. { STM32F4_RCC_APB2ENR, 21, "spi6", "apb2_div" },
  121. { STM32F4_RCC_APB2ENR, 22, "sai1", "apb2_div" },
  122. };
  123. static const struct stm32f4_gate_data stm32f469_gates[] __initconst = {
  124. { STM32F4_RCC_AHB1ENR, 0, "gpioa", "ahb_div" },
  125. { STM32F4_RCC_AHB1ENR, 1, "gpiob", "ahb_div" },
  126. { STM32F4_RCC_AHB1ENR, 2, "gpioc", "ahb_div" },
  127. { STM32F4_RCC_AHB1ENR, 3, "gpiod", "ahb_div" },
  128. { STM32F4_RCC_AHB1ENR, 4, "gpioe", "ahb_div" },
  129. { STM32F4_RCC_AHB1ENR, 5, "gpiof", "ahb_div" },
  130. { STM32F4_RCC_AHB1ENR, 6, "gpiog", "ahb_div" },
  131. { STM32F4_RCC_AHB1ENR, 7, "gpioh", "ahb_div" },
  132. { STM32F4_RCC_AHB1ENR, 8, "gpioi", "ahb_div" },
  133. { STM32F4_RCC_AHB1ENR, 9, "gpioj", "ahb_div" },
  134. { STM32F4_RCC_AHB1ENR, 10, "gpiok", "ahb_div" },
  135. { STM32F4_RCC_AHB1ENR, 12, "crc", "ahb_div" },
  136. { STM32F4_RCC_AHB1ENR, 18, "bkpsra", "ahb_div" },
  137. { STM32F4_RCC_AHB1ENR, 20, "ccmdatam", "ahb_div" },
  138. { STM32F4_RCC_AHB1ENR, 21, "dma1", "ahb_div" },
  139. { STM32F4_RCC_AHB1ENR, 22, "dma2", "ahb_div" },
  140. { STM32F4_RCC_AHB1ENR, 23, "dma2d", "ahb_div" },
  141. { STM32F4_RCC_AHB1ENR, 25, "ethmac", "ahb_div" },
  142. { STM32F4_RCC_AHB1ENR, 26, "ethmactx", "ahb_div" },
  143. { STM32F4_RCC_AHB1ENR, 27, "ethmacrx", "ahb_div" },
  144. { STM32F4_RCC_AHB1ENR, 28, "ethmacptp", "ahb_div" },
  145. { STM32F4_RCC_AHB1ENR, 29, "otghs", "ahb_div" },
  146. { STM32F4_RCC_AHB1ENR, 30, "otghsulpi", "ahb_div" },
  147. { STM32F4_RCC_AHB2ENR, 0, "dcmi", "ahb_div" },
  148. { STM32F4_RCC_AHB2ENR, 4, "cryp", "ahb_div" },
  149. { STM32F4_RCC_AHB2ENR, 5, "hash", "ahb_div" },
  150. { STM32F4_RCC_AHB2ENR, 6, "rng", "pll48" },
  151. { STM32F4_RCC_AHB2ENR, 7, "otgfs", "pll48" },
  152. { STM32F4_RCC_AHB3ENR, 0, "fmc", "ahb_div",
  153. CLK_IGNORE_UNUSED },
  154. { STM32F4_RCC_AHB3ENR, 1, "qspi", "ahb_div",
  155. CLK_IGNORE_UNUSED },
  156. { STM32F4_RCC_APB1ENR, 0, "tim2", "apb1_mul" },
  157. { STM32F4_RCC_APB1ENR, 1, "tim3", "apb1_mul" },
  158. { STM32F4_RCC_APB1ENR, 2, "tim4", "apb1_mul" },
  159. { STM32F4_RCC_APB1ENR, 3, "tim5", "apb1_mul" },
  160. { STM32F4_RCC_APB1ENR, 4, "tim6", "apb1_mul" },
  161. { STM32F4_RCC_APB1ENR, 5, "tim7", "apb1_mul" },
  162. { STM32F4_RCC_APB1ENR, 6, "tim12", "apb1_mul" },
  163. { STM32F4_RCC_APB1ENR, 7, "tim13", "apb1_mul" },
  164. { STM32F4_RCC_APB1ENR, 8, "tim14", "apb1_mul" },
  165. { STM32F4_RCC_APB1ENR, 11, "wwdg", "apb1_div" },
  166. { STM32F4_RCC_APB1ENR, 14, "spi2", "apb1_div" },
  167. { STM32F4_RCC_APB1ENR, 15, "spi3", "apb1_div" },
  168. { STM32F4_RCC_APB1ENR, 17, "uart2", "apb1_div" },
  169. { STM32F4_RCC_APB1ENR, 18, "uart3", "apb1_div" },
  170. { STM32F4_RCC_APB1ENR, 19, "uart4", "apb1_div" },
  171. { STM32F4_RCC_APB1ENR, 20, "uart5", "apb1_div" },
  172. { STM32F4_RCC_APB1ENR, 21, "i2c1", "apb1_div" },
  173. { STM32F4_RCC_APB1ENR, 22, "i2c2", "apb1_div" },
  174. { STM32F4_RCC_APB1ENR, 23, "i2c3", "apb1_div" },
  175. { STM32F4_RCC_APB1ENR, 25, "can1", "apb1_div" },
  176. { STM32F4_RCC_APB1ENR, 26, "can2", "apb1_div" },
  177. { STM32F4_RCC_APB1ENR, 28, "pwr", "apb1_div" },
  178. { STM32F4_RCC_APB1ENR, 29, "dac", "apb1_div" },
  179. { STM32F4_RCC_APB1ENR, 30, "uart7", "apb1_div" },
  180. { STM32F4_RCC_APB1ENR, 31, "uart8", "apb1_div" },
  181. { STM32F4_RCC_APB2ENR, 0, "tim1", "apb2_mul" },
  182. { STM32F4_RCC_APB2ENR, 1, "tim8", "apb2_mul" },
  183. { STM32F4_RCC_APB2ENR, 4, "usart1", "apb2_div" },
  184. { STM32F4_RCC_APB2ENR, 5, "usart6", "apb2_div" },
  185. { STM32F4_RCC_APB2ENR, 8, "adc1", "apb2_div" },
  186. { STM32F4_RCC_APB2ENR, 9, "adc2", "apb2_div" },
  187. { STM32F4_RCC_APB2ENR, 10, "adc3", "apb2_div" },
  188. { STM32F4_RCC_APB2ENR, 11, "sdio", "sdmux" },
  189. { STM32F4_RCC_APB2ENR, 12, "spi1", "apb2_div" },
  190. { STM32F4_RCC_APB2ENR, 13, "spi4", "apb2_div" },
  191. { STM32F4_RCC_APB2ENR, 14, "syscfg", "apb2_div" },
  192. { STM32F4_RCC_APB2ENR, 16, "tim9", "apb2_mul" },
  193. { STM32F4_RCC_APB2ENR, 17, "tim10", "apb2_mul" },
  194. { STM32F4_RCC_APB2ENR, 18, "tim11", "apb2_mul" },
  195. { STM32F4_RCC_APB2ENR, 20, "spi5", "apb2_div" },
  196. { STM32F4_RCC_APB2ENR, 21, "spi6", "apb2_div" },
  197. { STM32F4_RCC_APB2ENR, 22, "sai1", "apb2_div" },
  198. };
  199. static const struct stm32f4_gate_data stm32f746_gates[] __initconst = {
  200. { STM32F4_RCC_AHB1ENR, 0, "gpioa", "ahb_div" },
  201. { STM32F4_RCC_AHB1ENR, 1, "gpiob", "ahb_div" },
  202. { STM32F4_RCC_AHB1ENR, 2, "gpioc", "ahb_div" },
  203. { STM32F4_RCC_AHB1ENR, 3, "gpiod", "ahb_div" },
  204. { STM32F4_RCC_AHB1ENR, 4, "gpioe", "ahb_div" },
  205. { STM32F4_RCC_AHB1ENR, 5, "gpiof", "ahb_div" },
  206. { STM32F4_RCC_AHB1ENR, 6, "gpiog", "ahb_div" },
  207. { STM32F4_RCC_AHB1ENR, 7, "gpioh", "ahb_div" },
  208. { STM32F4_RCC_AHB1ENR, 8, "gpioi", "ahb_div" },
  209. { STM32F4_RCC_AHB1ENR, 9, "gpioj", "ahb_div" },
  210. { STM32F4_RCC_AHB1ENR, 10, "gpiok", "ahb_div" },
  211. { STM32F4_RCC_AHB1ENR, 12, "crc", "ahb_div" },
  212. { STM32F4_RCC_AHB1ENR, 18, "bkpsra", "ahb_div" },
  213. { STM32F4_RCC_AHB1ENR, 20, "dtcmram", "ahb_div" },
  214. { STM32F4_RCC_AHB1ENR, 21, "dma1", "ahb_div" },
  215. { STM32F4_RCC_AHB1ENR, 22, "dma2", "ahb_div" },
  216. { STM32F4_RCC_AHB1ENR, 23, "dma2d", "ahb_div" },
  217. { STM32F4_RCC_AHB1ENR, 25, "ethmac", "ahb_div" },
  218. { STM32F4_RCC_AHB1ENR, 26, "ethmactx", "ahb_div" },
  219. { STM32F4_RCC_AHB1ENR, 27, "ethmacrx", "ahb_div" },
  220. { STM32F4_RCC_AHB1ENR, 28, "ethmacptp", "ahb_div" },
  221. { STM32F4_RCC_AHB1ENR, 29, "otghs", "ahb_div" },
  222. { STM32F4_RCC_AHB1ENR, 30, "otghsulpi", "ahb_div" },
  223. { STM32F4_RCC_AHB2ENR, 0, "dcmi", "ahb_div" },
  224. { STM32F4_RCC_AHB2ENR, 4, "cryp", "ahb_div" },
  225. { STM32F4_RCC_AHB2ENR, 5, "hash", "ahb_div" },
  226. { STM32F4_RCC_AHB2ENR, 6, "rng", "pll48" },
  227. { STM32F4_RCC_AHB2ENR, 7, "otgfs", "pll48" },
  228. { STM32F4_RCC_AHB3ENR, 0, "fmc", "ahb_div",
  229. CLK_IGNORE_UNUSED },
  230. { STM32F4_RCC_AHB3ENR, 1, "qspi", "ahb_div",
  231. CLK_IGNORE_UNUSED },
  232. { STM32F4_RCC_APB1ENR, 0, "tim2", "apb1_mul" },
  233. { STM32F4_RCC_APB1ENR, 1, "tim3", "apb1_mul" },
  234. { STM32F4_RCC_APB1ENR, 2, "tim4", "apb1_mul" },
  235. { STM32F4_RCC_APB1ENR, 3, "tim5", "apb1_mul" },
  236. { STM32F4_RCC_APB1ENR, 4, "tim6", "apb1_mul" },
  237. { STM32F4_RCC_APB1ENR, 5, "tim7", "apb1_mul" },
  238. { STM32F4_RCC_APB1ENR, 6, "tim12", "apb1_mul" },
  239. { STM32F4_RCC_APB1ENR, 7, "tim13", "apb1_mul" },
  240. { STM32F4_RCC_APB1ENR, 8, "tim14", "apb1_mul" },
  241. { STM32F4_RCC_APB1ENR, 11, "wwdg", "apb1_div" },
  242. { STM32F4_RCC_APB1ENR, 14, "spi2", "apb1_div" },
  243. { STM32F4_RCC_APB1ENR, 15, "spi3", "apb1_div" },
  244. { STM32F4_RCC_APB1ENR, 16, "spdifrx", "apb1_div" },
  245. { STM32F4_RCC_APB1ENR, 25, "can1", "apb1_div" },
  246. { STM32F4_RCC_APB1ENR, 26, "can2", "apb1_div" },
  247. { STM32F4_RCC_APB1ENR, 27, "cec", "apb1_div" },
  248. { STM32F4_RCC_APB1ENR, 28, "pwr", "apb1_div" },
  249. { STM32F4_RCC_APB1ENR, 29, "dac", "apb1_div" },
  250. { STM32F4_RCC_APB2ENR, 0, "tim1", "apb2_mul" },
  251. { STM32F4_RCC_APB2ENR, 1, "tim8", "apb2_mul" },
  252. { STM32F4_RCC_APB2ENR, 7, "sdmmc2", "sdmux" },
  253. { STM32F4_RCC_APB2ENR, 8, "adc1", "apb2_div" },
  254. { STM32F4_RCC_APB2ENR, 9, "adc2", "apb2_div" },
  255. { STM32F4_RCC_APB2ENR, 10, "adc3", "apb2_div" },
  256. { STM32F4_RCC_APB2ENR, 11, "sdmmc", "sdmux" },
  257. { STM32F4_RCC_APB2ENR, 12, "spi1", "apb2_div" },
  258. { STM32F4_RCC_APB2ENR, 13, "spi4", "apb2_div" },
  259. { STM32F4_RCC_APB2ENR, 14, "syscfg", "apb2_div" },
  260. { STM32F4_RCC_APB2ENR, 16, "tim9", "apb2_mul" },
  261. { STM32F4_RCC_APB2ENR, 17, "tim10", "apb2_mul" },
  262. { STM32F4_RCC_APB2ENR, 18, "tim11", "apb2_mul" },
  263. { STM32F4_RCC_APB2ENR, 20, "spi5", "apb2_div" },
  264. { STM32F4_RCC_APB2ENR, 21, "spi6", "apb2_div" },
  265. { STM32F4_RCC_APB2ENR, 22, "sai1", "apb2_div" },
  266. { STM32F4_RCC_APB2ENR, 23, "sai2", "apb2_div" },
  267. };
  268. static const struct stm32f4_gate_data stm32f769_gates[] __initconst = {
  269. { STM32F4_RCC_AHB1ENR, 0, "gpioa", "ahb_div" },
  270. { STM32F4_RCC_AHB1ENR, 1, "gpiob", "ahb_div" },
  271. { STM32F4_RCC_AHB1ENR, 2, "gpioc", "ahb_div" },
  272. { STM32F4_RCC_AHB1ENR, 3, "gpiod", "ahb_div" },
  273. { STM32F4_RCC_AHB1ENR, 4, "gpioe", "ahb_div" },
  274. { STM32F4_RCC_AHB1ENR, 5, "gpiof", "ahb_div" },
  275. { STM32F4_RCC_AHB1ENR, 6, "gpiog", "ahb_div" },
  276. { STM32F4_RCC_AHB1ENR, 7, "gpioh", "ahb_div" },
  277. { STM32F4_RCC_AHB1ENR, 8, "gpioi", "ahb_div" },
  278. { STM32F4_RCC_AHB1ENR, 9, "gpioj", "ahb_div" },
  279. { STM32F4_RCC_AHB1ENR, 10, "gpiok", "ahb_div" },
  280. { STM32F4_RCC_AHB1ENR, 12, "crc", "ahb_div" },
  281. { STM32F4_RCC_AHB1ENR, 18, "bkpsra", "ahb_div" },
  282. { STM32F4_RCC_AHB1ENR, 20, "dtcmram", "ahb_div" },
  283. { STM32F4_RCC_AHB1ENR, 21, "dma1", "ahb_div" },
  284. { STM32F4_RCC_AHB1ENR, 22, "dma2", "ahb_div" },
  285. { STM32F4_RCC_AHB1ENR, 23, "dma2d", "ahb_div" },
  286. { STM32F4_RCC_AHB1ENR, 25, "ethmac", "ahb_div" },
  287. { STM32F4_RCC_AHB1ENR, 26, "ethmactx", "ahb_div" },
  288. { STM32F4_RCC_AHB1ENR, 27, "ethmacrx", "ahb_div" },
  289. { STM32F4_RCC_AHB1ENR, 28, "ethmacptp", "ahb_div" },
  290. { STM32F4_RCC_AHB1ENR, 29, "otghs", "ahb_div" },
  291. { STM32F4_RCC_AHB1ENR, 30, "otghsulpi", "ahb_div" },
  292. { STM32F4_RCC_AHB2ENR, 0, "dcmi", "ahb_div" },
  293. { STM32F4_RCC_AHB2ENR, 1, "jpeg", "ahb_div" },
  294. { STM32F4_RCC_AHB2ENR, 4, "cryp", "ahb_div" },
  295. { STM32F4_RCC_AHB2ENR, 5, "hash", "ahb_div" },
  296. { STM32F4_RCC_AHB2ENR, 6, "rng", "pll48" },
  297. { STM32F4_RCC_AHB2ENR, 7, "otgfs", "pll48" },
  298. { STM32F4_RCC_AHB3ENR, 0, "fmc", "ahb_div",
  299. CLK_IGNORE_UNUSED },
  300. { STM32F4_RCC_AHB3ENR, 1, "qspi", "ahb_div",
  301. CLK_IGNORE_UNUSED },
  302. { STM32F4_RCC_APB1ENR, 0, "tim2", "apb1_mul" },
  303. { STM32F4_RCC_APB1ENR, 1, "tim3", "apb1_mul" },
  304. { STM32F4_RCC_APB1ENR, 2, "tim4", "apb1_mul" },
  305. { STM32F4_RCC_APB1ENR, 3, "tim5", "apb1_mul" },
  306. { STM32F4_RCC_APB1ENR, 4, "tim6", "apb1_mul" },
  307. { STM32F4_RCC_APB1ENR, 5, "tim7", "apb1_mul" },
  308. { STM32F4_RCC_APB1ENR, 6, "tim12", "apb1_mul" },
  309. { STM32F4_RCC_APB1ENR, 7, "tim13", "apb1_mul" },
  310. { STM32F4_RCC_APB1ENR, 8, "tim14", "apb1_mul" },
  311. { STM32F4_RCC_APB1ENR, 10, "rtcapb", "apb1_mul" },
  312. { STM32F4_RCC_APB1ENR, 11, "wwdg", "apb1_div" },
  313. { STM32F4_RCC_APB1ENR, 13, "can3", "apb1_div" },
  314. { STM32F4_RCC_APB1ENR, 14, "spi2", "apb1_div" },
  315. { STM32F4_RCC_APB1ENR, 15, "spi3", "apb1_div" },
  316. { STM32F4_RCC_APB1ENR, 16, "spdifrx", "apb1_div" },
  317. { STM32F4_RCC_APB1ENR, 25, "can1", "apb1_div" },
  318. { STM32F4_RCC_APB1ENR, 26, "can2", "apb1_div" },
  319. { STM32F4_RCC_APB1ENR, 27, "cec", "apb1_div" },
  320. { STM32F4_RCC_APB1ENR, 28, "pwr", "apb1_div" },
  321. { STM32F4_RCC_APB1ENR, 29, "dac", "apb1_div" },
  322. { STM32F4_RCC_APB2ENR, 0, "tim1", "apb2_mul" },
  323. { STM32F4_RCC_APB2ENR, 1, "tim8", "apb2_mul" },
  324. { STM32F4_RCC_APB2ENR, 7, "sdmmc2", "sdmux2" },
  325. { STM32F4_RCC_APB2ENR, 8, "adc1", "apb2_div" },
  326. { STM32F4_RCC_APB2ENR, 9, "adc2", "apb2_div" },
  327. { STM32F4_RCC_APB2ENR, 10, "adc3", "apb2_div" },
  328. { STM32F4_RCC_APB2ENR, 11, "sdmmc1", "sdmux1" },
  329. { STM32F4_RCC_APB2ENR, 12, "spi1", "apb2_div" },
  330. { STM32F4_RCC_APB2ENR, 13, "spi4", "apb2_div" },
  331. { STM32F4_RCC_APB2ENR, 14, "syscfg", "apb2_div" },
  332. { STM32F4_RCC_APB2ENR, 16, "tim9", "apb2_mul" },
  333. { STM32F4_RCC_APB2ENR, 17, "tim10", "apb2_mul" },
  334. { STM32F4_RCC_APB2ENR, 18, "tim11", "apb2_mul" },
  335. { STM32F4_RCC_APB2ENR, 20, "spi5", "apb2_div" },
  336. { STM32F4_RCC_APB2ENR, 21, "spi6", "apb2_div" },
  337. { STM32F4_RCC_APB2ENR, 22, "sai1", "apb2_div" },
  338. { STM32F4_RCC_APB2ENR, 23, "sai2", "apb2_div" },
  339. { STM32F4_RCC_APB2ENR, 30, "mdio", "apb2_div" },
  340. };
  341. /*
  342. * This bitmask tells us which bit offsets (0..192) on STM32F4[23]xxx
  343. * have gate bits associated with them. Its combined hweight is 71.
  344. */
  345. #define MAX_GATE_MAP 3
  346. static const u64 stm32f42xx_gate_map[MAX_GATE_MAP] = { 0x000000f17ef417ffull,
  347. 0x0000000000000001ull,
  348. 0x04777f33f6fec9ffull };
  349. static const u64 stm32f46xx_gate_map[MAX_GATE_MAP] = { 0x000000f17ef417ffull,
  350. 0x0000000000000003ull,
  351. 0x0c777f33f6fec9ffull };
  352. static const u64 stm32f746_gate_map[MAX_GATE_MAP] = { 0x000000f17ef417ffull,
  353. 0x0000000000000003ull,
  354. 0x04f77f833e01c9ffull };
  355. static const u64 stm32f769_gate_map[MAX_GATE_MAP] = { 0x000000f37ef417ffull,
  356. 0x0000000000000003ull,
  357. 0x44F77F833E01EDFFull };
  358. static const u64 *stm32f4_gate_map;
  359. static struct clk_hw **clks;
  360. static DEFINE_SPINLOCK(stm32f4_clk_lock);
  361. static void __iomem *base;
  362. static struct regmap *pdrm;
  363. static int stm32fx_end_primary_clk;
  364. /*
  365. * "Multiplier" device for APBx clocks.
  366. *
  367. * The APBx dividers are power-of-two dividers and, if *not* running in 1:1
  368. * mode, they also tap out the one of the low order state bits to run the
  369. * timers. ST datasheets represent this feature as a (conditional) clock
  370. * multiplier.
  371. */
  372. struct clk_apb_mul {
  373. struct clk_hw hw;
  374. u8 bit_idx;
  375. };
  376. #define to_clk_apb_mul(_hw) container_of(_hw, struct clk_apb_mul, hw)
  377. static unsigned long clk_apb_mul_recalc_rate(struct clk_hw *hw,
  378. unsigned long parent_rate)
  379. {
  380. struct clk_apb_mul *am = to_clk_apb_mul(hw);
  381. if (readl(base + STM32F4_RCC_CFGR) & BIT(am->bit_idx))
  382. return parent_rate * 2;
  383. return parent_rate;
  384. }
  385. static long clk_apb_mul_round_rate(struct clk_hw *hw, unsigned long rate,
  386. unsigned long *prate)
  387. {
  388. struct clk_apb_mul *am = to_clk_apb_mul(hw);
  389. unsigned long mult = 1;
  390. if (readl(base + STM32F4_RCC_CFGR) & BIT(am->bit_idx))
  391. mult = 2;
  392. if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) {
  393. unsigned long best_parent = rate / mult;
  394. *prate = clk_hw_round_rate(clk_hw_get_parent(hw), best_parent);
  395. }
  396. return *prate * mult;
  397. }
  398. static int clk_apb_mul_set_rate(struct clk_hw *hw, unsigned long rate,
  399. unsigned long parent_rate)
  400. {
  401. /*
  402. * We must report success but we can do so unconditionally because
  403. * clk_apb_mul_round_rate returns values that ensure this call is a
  404. * nop.
  405. */
  406. return 0;
  407. }
  408. static const struct clk_ops clk_apb_mul_factor_ops = {
  409. .round_rate = clk_apb_mul_round_rate,
  410. .set_rate = clk_apb_mul_set_rate,
  411. .recalc_rate = clk_apb_mul_recalc_rate,
  412. };
  413. static struct clk *clk_register_apb_mul(struct device *dev, const char *name,
  414. const char *parent_name,
  415. unsigned long flags, u8 bit_idx)
  416. {
  417. struct clk_apb_mul *am;
  418. struct clk_init_data init;
  419. struct clk *clk;
  420. am = kzalloc(sizeof(*am), GFP_KERNEL);
  421. if (!am)
  422. return ERR_PTR(-ENOMEM);
  423. am->bit_idx = bit_idx;
  424. am->hw.init = &init;
  425. init.name = name;
  426. init.ops = &clk_apb_mul_factor_ops;
  427. init.flags = flags;
  428. init.parent_names = &parent_name;
  429. init.num_parents = 1;
  430. clk = clk_register(dev, &am->hw);
  431. if (IS_ERR(clk))
  432. kfree(am);
  433. return clk;
  434. }
  435. enum {
  436. PLL,
  437. PLL_I2S,
  438. PLL_SAI,
  439. };
  440. static const struct clk_div_table pll_divp_table[] = {
  441. { 0, 2 }, { 1, 4 }, { 2, 6 }, { 3, 8 }, { 0 }
  442. };
  443. static const struct clk_div_table pll_divq_table[] = {
  444. { 2, 2 }, { 3, 3 }, { 4, 4 }, { 5, 5 }, { 6, 6 }, { 7, 7 },
  445. { 8, 8 }, { 9, 9 }, { 10, 10 }, { 11, 11 }, { 12, 12 }, { 13, 13 },
  446. { 14, 14 }, { 15, 15 },
  447. { 0 }
  448. };
  449. static const struct clk_div_table pll_divr_table[] = {
  450. { 2, 2 }, { 3, 3 }, { 4, 4 }, { 5, 5 }, { 6, 6 }, { 7, 7 }, { 0 }
  451. };
  452. struct stm32f4_pll {
  453. spinlock_t *lock;
  454. struct clk_gate gate;
  455. u8 offset;
  456. u8 bit_rdy_idx;
  457. u8 status;
  458. u8 n_start;
  459. };
  460. #define to_stm32f4_pll(_gate) container_of(_gate, struct stm32f4_pll, gate)
  461. struct stm32f4_pll_post_div_data {
  462. int idx;
  463. int pll_idx;
  464. const char *name;
  465. const char *parent;
  466. u8 flag;
  467. u8 offset;
  468. u8 shift;
  469. u8 width;
  470. u8 flag_div;
  471. const struct clk_div_table *div_table;
  472. };
  473. struct stm32f4_vco_data {
  474. const char *vco_name;
  475. u8 offset;
  476. u8 bit_idx;
  477. u8 bit_rdy_idx;
  478. };
  479. static const struct stm32f4_vco_data vco_data[] = {
  480. { "vco", STM32F4_RCC_PLLCFGR, 24, 25 },
  481. { "vco-i2s", STM32F4_RCC_PLLI2SCFGR, 26, 27 },
  482. { "vco-sai", STM32F4_RCC_PLLSAICFGR, 28, 29 },
  483. };
  484. static const struct clk_div_table post_divr_table[] = {
  485. { 0, 2 }, { 1, 4 }, { 2, 8 }, { 3, 16 }, { 0 }
  486. };
  487. #define MAX_POST_DIV 3
  488. static const struct stm32f4_pll_post_div_data post_div_data[MAX_POST_DIV] = {
  489. { CLK_I2SQ_PDIV, PLL_VCO_I2S, "plli2s-q-div", "plli2s-q",
  490. CLK_SET_RATE_PARENT, STM32F4_RCC_DCKCFGR, 0, 5, 0, NULL},
  491. { CLK_SAIQ_PDIV, PLL_VCO_SAI, "pllsai-q-div", "pllsai-q",
  492. CLK_SET_RATE_PARENT, STM32F4_RCC_DCKCFGR, 8, 5, 0, NULL },
  493. { NO_IDX, PLL_VCO_SAI, "pllsai-r-div", "pllsai-r", CLK_SET_RATE_PARENT,
  494. STM32F4_RCC_DCKCFGR, 16, 2, 0, post_divr_table },
  495. };
  496. struct stm32f4_div_data {
  497. u8 shift;
  498. u8 width;
  499. u8 flag_div;
  500. const struct clk_div_table *div_table;
  501. };
  502. #define MAX_PLL_DIV 3
  503. static const struct stm32f4_div_data div_data[MAX_PLL_DIV] = {
  504. { 16, 2, 0, pll_divp_table },
  505. { 24, 4, 0, pll_divq_table },
  506. { 28, 3, 0, pll_divr_table },
  507. };
  508. struct stm32f4_pll_data {
  509. u8 pll_num;
  510. u8 n_start;
  511. const char *div_name[MAX_PLL_DIV];
  512. };
  513. static const struct stm32f4_pll_data stm32f429_pll[MAX_PLL_DIV] = {
  514. { PLL, 192, { "pll", "pll48", NULL } },
  515. { PLL_I2S, 192, { NULL, "plli2s-q", "plli2s-r" } },
  516. { PLL_SAI, 49, { NULL, "pllsai-q", "pllsai-r" } },
  517. };
  518. static const struct stm32f4_pll_data stm32f469_pll[MAX_PLL_DIV] = {
  519. { PLL, 50, { "pll", "pll-q", "pll-r" } },
  520. { PLL_I2S, 50, { "plli2s-p", "plli2s-q", "plli2s-r" } },
  521. { PLL_SAI, 50, { "pllsai-p", "pllsai-q", "pllsai-r" } },
  522. };
  523. static int stm32f4_pll_is_enabled(struct clk_hw *hw)
  524. {
  525. return clk_gate_ops.is_enabled(hw);
  526. }
  527. #define PLL_TIMEOUT 10000
  528. static int stm32f4_pll_enable(struct clk_hw *hw)
  529. {
  530. struct clk_gate *gate = to_clk_gate(hw);
  531. struct stm32f4_pll *pll = to_stm32f4_pll(gate);
  532. int bit_status;
  533. unsigned int timeout = PLL_TIMEOUT;
  534. if (clk_gate_ops.is_enabled(hw))
  535. return 0;
  536. clk_gate_ops.enable(hw);
  537. do {
  538. bit_status = !(readl(gate->reg) & BIT(pll->bit_rdy_idx));
  539. } while (bit_status && --timeout);
  540. return bit_status;
  541. }
  542. static void stm32f4_pll_disable(struct clk_hw *hw)
  543. {
  544. clk_gate_ops.disable(hw);
  545. }
  546. static unsigned long stm32f4_pll_recalc(struct clk_hw *hw,
  547. unsigned long parent_rate)
  548. {
  549. struct clk_gate *gate = to_clk_gate(hw);
  550. struct stm32f4_pll *pll = to_stm32f4_pll(gate);
  551. unsigned long n;
  552. n = (readl(base + pll->offset) >> 6) & 0x1ff;
  553. return parent_rate * n;
  554. }
  555. static long stm32f4_pll_round_rate(struct clk_hw *hw, unsigned long rate,
  556. unsigned long *prate)
  557. {
  558. struct clk_gate *gate = to_clk_gate(hw);
  559. struct stm32f4_pll *pll = to_stm32f4_pll(gate);
  560. unsigned long n;
  561. n = rate / *prate;
  562. if (n < pll->n_start)
  563. n = pll->n_start;
  564. else if (n > 432)
  565. n = 432;
  566. return *prate * n;
  567. }
  568. static int stm32f4_pll_set_rate(struct clk_hw *hw, unsigned long rate,
  569. unsigned long parent_rate)
  570. {
  571. struct clk_gate *gate = to_clk_gate(hw);
  572. struct stm32f4_pll *pll = to_stm32f4_pll(gate);
  573. unsigned long n;
  574. unsigned long val;
  575. int pll_state;
  576. pll_state = stm32f4_pll_is_enabled(hw);
  577. if (pll_state)
  578. stm32f4_pll_disable(hw);
  579. n = rate / parent_rate;
  580. val = readl(base + pll->offset) & ~(0x1ff << 6);
  581. writel(val | ((n & 0x1ff) << 6), base + pll->offset);
  582. if (pll_state)
  583. stm32f4_pll_enable(hw);
  584. return 0;
  585. }
  586. static const struct clk_ops stm32f4_pll_gate_ops = {
  587. .enable = stm32f4_pll_enable,
  588. .disable = stm32f4_pll_disable,
  589. .is_enabled = stm32f4_pll_is_enabled,
  590. .recalc_rate = stm32f4_pll_recalc,
  591. .round_rate = stm32f4_pll_round_rate,
  592. .set_rate = stm32f4_pll_set_rate,
  593. };
  594. struct stm32f4_pll_div {
  595. struct clk_divider div;
  596. struct clk_hw *hw_pll;
  597. };
  598. #define to_pll_div_clk(_div) container_of(_div, struct stm32f4_pll_div, div)
  599. static unsigned long stm32f4_pll_div_recalc_rate(struct clk_hw *hw,
  600. unsigned long parent_rate)
  601. {
  602. return clk_divider_ops.recalc_rate(hw, parent_rate);
  603. }
  604. static long stm32f4_pll_div_round_rate(struct clk_hw *hw, unsigned long rate,
  605. unsigned long *prate)
  606. {
  607. return clk_divider_ops.round_rate(hw, rate, prate);
  608. }
  609. static int stm32f4_pll_div_set_rate(struct clk_hw *hw, unsigned long rate,
  610. unsigned long parent_rate)
  611. {
  612. int pll_state, ret;
  613. struct clk_divider *div = to_clk_divider(hw);
  614. struct stm32f4_pll_div *pll_div = to_pll_div_clk(div);
  615. pll_state = stm32f4_pll_is_enabled(pll_div->hw_pll);
  616. if (pll_state)
  617. stm32f4_pll_disable(pll_div->hw_pll);
  618. ret = clk_divider_ops.set_rate(hw, rate, parent_rate);
  619. if (pll_state)
  620. stm32f4_pll_enable(pll_div->hw_pll);
  621. return ret;
  622. }
  623. static const struct clk_ops stm32f4_pll_div_ops = {
  624. .recalc_rate = stm32f4_pll_div_recalc_rate,
  625. .round_rate = stm32f4_pll_div_round_rate,
  626. .set_rate = stm32f4_pll_div_set_rate,
  627. };
  628. static struct clk_hw *clk_register_pll_div(const char *name,
  629. const char *parent_name, unsigned long flags,
  630. void __iomem *reg, u8 shift, u8 width,
  631. u8 clk_divider_flags, const struct clk_div_table *table,
  632. struct clk_hw *pll_hw, spinlock_t *lock)
  633. {
  634. struct stm32f4_pll_div *pll_div;
  635. struct clk_hw *hw;
  636. struct clk_init_data init;
  637. int ret;
  638. /* allocate the divider */
  639. pll_div = kzalloc(sizeof(*pll_div), GFP_KERNEL);
  640. if (!pll_div)
  641. return ERR_PTR(-ENOMEM);
  642. init.name = name;
  643. init.ops = &stm32f4_pll_div_ops;
  644. init.flags = flags;
  645. init.parent_names = (parent_name ? &parent_name : NULL);
  646. init.num_parents = (parent_name ? 1 : 0);
  647. /* struct clk_divider assignments */
  648. pll_div->div.reg = reg;
  649. pll_div->div.shift = shift;
  650. pll_div->div.width = width;
  651. pll_div->div.flags = clk_divider_flags;
  652. pll_div->div.lock = lock;
  653. pll_div->div.table = table;
  654. pll_div->div.hw.init = &init;
  655. pll_div->hw_pll = pll_hw;
  656. /* register the clock */
  657. hw = &pll_div->div.hw;
  658. ret = clk_hw_register(NULL, hw);
  659. if (ret) {
  660. kfree(pll_div);
  661. hw = ERR_PTR(ret);
  662. }
  663. return hw;
  664. }
  665. static struct clk_hw *stm32f4_rcc_register_pll(const char *pllsrc,
  666. const struct stm32f4_pll_data *data, spinlock_t *lock)
  667. {
  668. struct stm32f4_pll *pll;
  669. struct clk_init_data init = { NULL };
  670. void __iomem *reg;
  671. struct clk_hw *pll_hw;
  672. int ret;
  673. int i;
  674. const struct stm32f4_vco_data *vco;
  675. pll = kzalloc(sizeof(*pll), GFP_KERNEL);
  676. if (!pll)
  677. return ERR_PTR(-ENOMEM);
  678. vco = &vco_data[data->pll_num];
  679. init.name = vco->vco_name;
  680. init.ops = &stm32f4_pll_gate_ops;
  681. init.flags = CLK_SET_RATE_GATE;
  682. init.parent_names = &pllsrc;
  683. init.num_parents = 1;
  684. pll->gate.lock = lock;
  685. pll->gate.reg = base + STM32F4_RCC_CR;
  686. pll->gate.bit_idx = vco->bit_idx;
  687. pll->gate.hw.init = &init;
  688. pll->offset = vco->offset;
  689. pll->n_start = data->n_start;
  690. pll->bit_rdy_idx = vco->bit_rdy_idx;
  691. pll->status = (readl(base + STM32F4_RCC_CR) >> vco->bit_idx) & 0x1;
  692. reg = base + pll->offset;
  693. pll_hw = &pll->gate.hw;
  694. ret = clk_hw_register(NULL, pll_hw);
  695. if (ret) {
  696. kfree(pll);
  697. return ERR_PTR(ret);
  698. }
  699. for (i = 0; i < MAX_PLL_DIV; i++)
  700. if (data->div_name[i])
  701. clk_register_pll_div(data->div_name[i],
  702. vco->vco_name,
  703. 0,
  704. reg,
  705. div_data[i].shift,
  706. div_data[i].width,
  707. div_data[i].flag_div,
  708. div_data[i].div_table,
  709. pll_hw,
  710. lock);
  711. return pll_hw;
  712. }
  713. /*
  714. * Converts the primary and secondary indices (as they appear in DT) to an
  715. * offset into our struct clock array.
  716. */
  717. static int stm32f4_rcc_lookup_clk_idx(u8 primary, u8 secondary)
  718. {
  719. u64 table[MAX_GATE_MAP];
  720. if (primary == 1) {
  721. if (WARN_ON(secondary >= stm32fx_end_primary_clk))
  722. return -EINVAL;
  723. return secondary;
  724. }
  725. memcpy(table, stm32f4_gate_map, sizeof(table));
  726. /* only bits set in table can be used as indices */
  727. if (WARN_ON(secondary >= BITS_PER_BYTE * sizeof(table) ||
  728. 0 == (table[BIT_ULL_WORD(secondary)] &
  729. BIT_ULL_MASK(secondary))))
  730. return -EINVAL;
  731. /* mask out bits above our current index */
  732. table[BIT_ULL_WORD(secondary)] &=
  733. GENMASK_ULL(secondary % BITS_PER_LONG_LONG, 0);
  734. return stm32fx_end_primary_clk - 1 + hweight64(table[0]) +
  735. (BIT_ULL_WORD(secondary) >= 1 ? hweight64(table[1]) : 0) +
  736. (BIT_ULL_WORD(secondary) >= 2 ? hweight64(table[2]) : 0);
  737. }
  738. static struct clk_hw *
  739. stm32f4_rcc_lookup_clk(struct of_phandle_args *clkspec, void *data)
  740. {
  741. int i = stm32f4_rcc_lookup_clk_idx(clkspec->args[0], clkspec->args[1]);
  742. if (i < 0)
  743. return ERR_PTR(-EINVAL);
  744. return clks[i];
  745. }
  746. #define to_rgclk(_rgate) container_of(_rgate, struct stm32_rgate, gate)
  747. static inline void disable_power_domain_write_protection(void)
  748. {
  749. if (pdrm)
  750. regmap_update_bits(pdrm, 0x00, (1 << 8), (1 << 8));
  751. }
  752. static inline void enable_power_domain_write_protection(void)
  753. {
  754. if (pdrm)
  755. regmap_update_bits(pdrm, 0x00, (1 << 8), (0 << 8));
  756. }
  757. static inline void sofware_reset_backup_domain(void)
  758. {
  759. unsigned long val;
  760. val = readl(base + STM32F4_RCC_BDCR);
  761. writel(val | BIT(16), base + STM32F4_RCC_BDCR);
  762. writel(val & ~BIT(16), base + STM32F4_RCC_BDCR);
  763. }
  764. struct stm32_rgate {
  765. struct clk_gate gate;
  766. u8 bit_rdy_idx;
  767. };
  768. #define RGATE_TIMEOUT 50000
  769. static int rgclk_enable(struct clk_hw *hw)
  770. {
  771. struct clk_gate *gate = to_clk_gate(hw);
  772. struct stm32_rgate *rgate = to_rgclk(gate);
  773. int bit_status;
  774. unsigned int timeout = RGATE_TIMEOUT;
  775. if (clk_gate_ops.is_enabled(hw))
  776. return 0;
  777. disable_power_domain_write_protection();
  778. clk_gate_ops.enable(hw);
  779. do {
  780. bit_status = !(readl(gate->reg) & BIT(rgate->bit_rdy_idx));
  781. if (bit_status)
  782. udelay(100);
  783. } while (bit_status && --timeout);
  784. enable_power_domain_write_protection();
  785. return bit_status;
  786. }
  787. static void rgclk_disable(struct clk_hw *hw)
  788. {
  789. clk_gate_ops.disable(hw);
  790. }
  791. static int rgclk_is_enabled(struct clk_hw *hw)
  792. {
  793. return clk_gate_ops.is_enabled(hw);
  794. }
  795. static const struct clk_ops rgclk_ops = {
  796. .enable = rgclk_enable,
  797. .disable = rgclk_disable,
  798. .is_enabled = rgclk_is_enabled,
  799. };
  800. static struct clk_hw *clk_register_rgate(struct device *dev, const char *name,
  801. const char *parent_name, unsigned long flags,
  802. void __iomem *reg, u8 bit_idx, u8 bit_rdy_idx,
  803. u8 clk_gate_flags, spinlock_t *lock)
  804. {
  805. struct stm32_rgate *rgate;
  806. struct clk_init_data init = { NULL };
  807. struct clk_hw *hw;
  808. int ret;
  809. rgate = kzalloc(sizeof(*rgate), GFP_KERNEL);
  810. if (!rgate)
  811. return ERR_PTR(-ENOMEM);
  812. init.name = name;
  813. init.ops = &rgclk_ops;
  814. init.flags = flags;
  815. init.parent_names = &parent_name;
  816. init.num_parents = 1;
  817. rgate->bit_rdy_idx = bit_rdy_idx;
  818. rgate->gate.lock = lock;
  819. rgate->gate.reg = reg;
  820. rgate->gate.bit_idx = bit_idx;
  821. rgate->gate.hw.init = &init;
  822. hw = &rgate->gate.hw;
  823. ret = clk_hw_register(dev, hw);
  824. if (ret) {
  825. kfree(rgate);
  826. hw = ERR_PTR(ret);
  827. }
  828. return hw;
  829. }
  830. static int cclk_gate_enable(struct clk_hw *hw)
  831. {
  832. int ret;
  833. disable_power_domain_write_protection();
  834. ret = clk_gate_ops.enable(hw);
  835. enable_power_domain_write_protection();
  836. return ret;
  837. }
  838. static void cclk_gate_disable(struct clk_hw *hw)
  839. {
  840. disable_power_domain_write_protection();
  841. clk_gate_ops.disable(hw);
  842. enable_power_domain_write_protection();
  843. }
  844. static int cclk_gate_is_enabled(struct clk_hw *hw)
  845. {
  846. return clk_gate_ops.is_enabled(hw);
  847. }
  848. static const struct clk_ops cclk_gate_ops = {
  849. .enable = cclk_gate_enable,
  850. .disable = cclk_gate_disable,
  851. .is_enabled = cclk_gate_is_enabled,
  852. };
  853. static u8 cclk_mux_get_parent(struct clk_hw *hw)
  854. {
  855. return clk_mux_ops.get_parent(hw);
  856. }
  857. static int cclk_mux_set_parent(struct clk_hw *hw, u8 index)
  858. {
  859. int ret;
  860. disable_power_domain_write_protection();
  861. sofware_reset_backup_domain();
  862. ret = clk_mux_ops.set_parent(hw, index);
  863. enable_power_domain_write_protection();
  864. return ret;
  865. }
  866. static const struct clk_ops cclk_mux_ops = {
  867. .get_parent = cclk_mux_get_parent,
  868. .set_parent = cclk_mux_set_parent,
  869. };
  870. static struct clk_hw *stm32_register_cclk(struct device *dev, const char *name,
  871. const char * const *parent_names, int num_parents,
  872. void __iomem *reg, u8 bit_idx, u8 shift, unsigned long flags,
  873. spinlock_t *lock)
  874. {
  875. struct clk_hw *hw;
  876. struct clk_gate *gate;
  877. struct clk_mux *mux;
  878. gate = kzalloc(sizeof(*gate), GFP_KERNEL);
  879. if (!gate) {
  880. hw = ERR_PTR(-EINVAL);
  881. goto fail;
  882. }
  883. mux = kzalloc(sizeof(*mux), GFP_KERNEL);
  884. if (!mux) {
  885. kfree(gate);
  886. hw = ERR_PTR(-EINVAL);
  887. goto fail;
  888. }
  889. gate->reg = reg;
  890. gate->bit_idx = bit_idx;
  891. gate->flags = 0;
  892. gate->lock = lock;
  893. mux->reg = reg;
  894. mux->shift = shift;
  895. mux->mask = 3;
  896. mux->flags = 0;
  897. hw = clk_hw_register_composite(dev, name, parent_names, num_parents,
  898. &mux->hw, &cclk_mux_ops,
  899. NULL, NULL,
  900. &gate->hw, &cclk_gate_ops,
  901. flags);
  902. if (IS_ERR(hw)) {
  903. kfree(gate);
  904. kfree(mux);
  905. }
  906. fail:
  907. return hw;
  908. }
  909. static const char *sys_parents[] __initdata = { "hsi", NULL, "pll" };
  910. static const struct clk_div_table ahb_div_table[] = {
  911. { 0x0, 1 }, { 0x1, 1 }, { 0x2, 1 }, { 0x3, 1 },
  912. { 0x4, 1 }, { 0x5, 1 }, { 0x6, 1 }, { 0x7, 1 },
  913. { 0x8, 2 }, { 0x9, 4 }, { 0xa, 8 }, { 0xb, 16 },
  914. { 0xc, 64 }, { 0xd, 128 }, { 0xe, 256 }, { 0xf, 512 },
  915. { 0 },
  916. };
  917. static const struct clk_div_table apb_div_table[] = {
  918. { 0, 1 }, { 0, 1 }, { 0, 1 }, { 0, 1 },
  919. { 4, 2 }, { 5, 4 }, { 6, 8 }, { 7, 16 },
  920. { 0 },
  921. };
  922. static const char *rtc_parents[4] = {
  923. "no-clock", "lse", "lsi", "hse-rtc"
  924. };
  925. static const char *pll_src = "pll-src";
  926. static const char *pllsrc_parent[2] = { "hsi", NULL };
  927. static const char *dsi_parent[2] = { NULL, "pll-r" };
  928. static const char *lcd_parent[1] = { "pllsai-r-div" };
  929. static const char *i2s_parents[2] = { "plli2s-r", NULL };
  930. static const char *sai_parents[4] = { "pllsai-q-div", "plli2s-q-div", NULL,
  931. "no-clock" };
  932. static const char *pll48_parents[2] = { "pll-q", "pllsai-p" };
  933. static const char *sdmux_parents[2] = { "pll48", "sys" };
  934. static const char *hdmi_parents[2] = { "lse", "hsi_div488" };
  935. static const char *spdif_parent[1] = { "plli2s-p" };
  936. static const char *lptim_parent[4] = { "apb1_mul", "lsi", "hsi", "lse" };
  937. static const char *uart_parents1[4] = { "apb2_div", "sys", "hsi", "lse" };
  938. static const char *uart_parents2[4] = { "apb1_div", "sys", "hsi", "lse" };
  939. static const char *i2c_parents[4] = { "apb1_div", "sys", "hsi", "no-clock" };
  940. static const char * const dfsdm1_src[] = { "apb2_div", "sys" };
  941. static const char * const adsfdm1_parent[] = { "sai1_clk", "sai2_clk" };
  942. struct stm32_aux_clk {
  943. int idx;
  944. const char *name;
  945. const char * const *parent_names;
  946. int num_parents;
  947. int offset_mux;
  948. u8 shift;
  949. u8 mask;
  950. int offset_gate;
  951. u8 bit_idx;
  952. unsigned long flags;
  953. };
  954. struct stm32f4_clk_data {
  955. const struct stm32f4_gate_data *gates_data;
  956. const u64 *gates_map;
  957. int gates_num;
  958. const struct stm32f4_pll_data *pll_data;
  959. const struct stm32_aux_clk *aux_clk;
  960. int aux_clk_num;
  961. int end_primary;
  962. };
  963. static const struct stm32_aux_clk stm32f429_aux_clk[] = {
  964. {
  965. CLK_LCD, "lcd-tft", lcd_parent, ARRAY_SIZE(lcd_parent),
  966. NO_MUX, 0, 0,
  967. STM32F4_RCC_APB2ENR, 26,
  968. CLK_SET_RATE_PARENT
  969. },
  970. {
  971. CLK_I2S, "i2s", i2s_parents, ARRAY_SIZE(i2s_parents),
  972. STM32F4_RCC_CFGR, 23, 1,
  973. NO_GATE, 0,
  974. CLK_SET_RATE_PARENT
  975. },
  976. {
  977. CLK_SAI1, "sai1-a", sai_parents, ARRAY_SIZE(sai_parents),
  978. STM32F4_RCC_DCKCFGR, 20, 3,
  979. STM32F4_RCC_APB2ENR, 22,
  980. CLK_SET_RATE_PARENT
  981. },
  982. {
  983. CLK_SAI2, "sai1-b", sai_parents, ARRAY_SIZE(sai_parents),
  984. STM32F4_RCC_DCKCFGR, 22, 3,
  985. STM32F4_RCC_APB2ENR, 22,
  986. CLK_SET_RATE_PARENT
  987. },
  988. };
  989. static const struct stm32_aux_clk stm32f469_aux_clk[] = {
  990. {
  991. CLK_LCD, "lcd-tft", lcd_parent, ARRAY_SIZE(lcd_parent),
  992. NO_MUX, 0, 0,
  993. STM32F4_RCC_APB2ENR, 26,
  994. CLK_SET_RATE_PARENT
  995. },
  996. {
  997. CLK_I2S, "i2s", i2s_parents, ARRAY_SIZE(i2s_parents),
  998. STM32F4_RCC_CFGR, 23, 1,
  999. NO_GATE, 0,
  1000. CLK_SET_RATE_PARENT
  1001. },
  1002. {
  1003. CLK_SAI1, "sai1-a", sai_parents, ARRAY_SIZE(sai_parents),
  1004. STM32F4_RCC_DCKCFGR, 20, 3,
  1005. STM32F4_RCC_APB2ENR, 22,
  1006. CLK_SET_RATE_PARENT
  1007. },
  1008. {
  1009. CLK_SAI2, "sai1-b", sai_parents, ARRAY_SIZE(sai_parents),
  1010. STM32F4_RCC_DCKCFGR, 22, 3,
  1011. STM32F4_RCC_APB2ENR, 22,
  1012. CLK_SET_RATE_PARENT
  1013. },
  1014. {
  1015. NO_IDX, "pll48", pll48_parents, ARRAY_SIZE(pll48_parents),
  1016. STM32F4_RCC_DCKCFGR, 27, 1,
  1017. NO_GATE, 0,
  1018. 0
  1019. },
  1020. {
  1021. NO_IDX, "sdmux", sdmux_parents, ARRAY_SIZE(sdmux_parents),
  1022. STM32F4_RCC_DCKCFGR, 28, 1,
  1023. NO_GATE, 0,
  1024. 0
  1025. },
  1026. {
  1027. CLK_F469_DSI, "dsi", dsi_parent, ARRAY_SIZE(dsi_parent),
  1028. STM32F4_RCC_DCKCFGR, 29, 1,
  1029. STM32F4_RCC_APB2ENR, 27,
  1030. CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT
  1031. },
  1032. };
  1033. static const struct stm32_aux_clk stm32f746_aux_clk[] = {
  1034. {
  1035. CLK_LCD, "lcd-tft", lcd_parent, ARRAY_SIZE(lcd_parent),
  1036. NO_MUX, 0, 0,
  1037. STM32F4_RCC_APB2ENR, 26,
  1038. CLK_SET_RATE_PARENT
  1039. },
  1040. {
  1041. CLK_I2S, "i2s", i2s_parents, ARRAY_SIZE(i2s_parents),
  1042. STM32F4_RCC_CFGR, 23, 1,
  1043. NO_GATE, 0,
  1044. CLK_SET_RATE_PARENT
  1045. },
  1046. {
  1047. CLK_SAI1, "sai1_clk", sai_parents, ARRAY_SIZE(sai_parents),
  1048. STM32F4_RCC_DCKCFGR, 20, 3,
  1049. STM32F4_RCC_APB2ENR, 22,
  1050. CLK_SET_RATE_PARENT
  1051. },
  1052. {
  1053. CLK_SAI2, "sai2_clk", sai_parents, ARRAY_SIZE(sai_parents),
  1054. STM32F4_RCC_DCKCFGR, 22, 3,
  1055. STM32F4_RCC_APB2ENR, 23,
  1056. CLK_SET_RATE_PARENT
  1057. },
  1058. {
  1059. NO_IDX, "pll48", pll48_parents, ARRAY_SIZE(pll48_parents),
  1060. STM32F7_RCC_DCKCFGR2, 27, 1,
  1061. NO_GATE, 0,
  1062. 0
  1063. },
  1064. {
  1065. NO_IDX, "sdmux", sdmux_parents, ARRAY_SIZE(sdmux_parents),
  1066. STM32F7_RCC_DCKCFGR2, 28, 1,
  1067. NO_GATE, 0,
  1068. 0
  1069. },
  1070. {
  1071. CLK_HDMI_CEC, "hdmi-cec",
  1072. hdmi_parents, ARRAY_SIZE(hdmi_parents),
  1073. STM32F7_RCC_DCKCFGR2, 26, 1,
  1074. NO_GATE, 0,
  1075. 0
  1076. },
  1077. {
  1078. CLK_SPDIF, "spdif-rx",
  1079. spdif_parent, ARRAY_SIZE(spdif_parent),
  1080. STM32F7_RCC_DCKCFGR2, 22, 3,
  1081. STM32F4_RCC_APB2ENR, 23,
  1082. CLK_SET_RATE_PARENT
  1083. },
  1084. {
  1085. CLK_USART1, "usart1",
  1086. uart_parents1, ARRAY_SIZE(uart_parents1),
  1087. STM32F7_RCC_DCKCFGR2, 0, 3,
  1088. STM32F4_RCC_APB2ENR, 4,
  1089. CLK_SET_RATE_PARENT,
  1090. },
  1091. {
  1092. CLK_USART2, "usart2",
  1093. uart_parents2, ARRAY_SIZE(uart_parents1),
  1094. STM32F7_RCC_DCKCFGR2, 2, 3,
  1095. STM32F4_RCC_APB1ENR, 17,
  1096. CLK_SET_RATE_PARENT,
  1097. },
  1098. {
  1099. CLK_USART3, "usart3",
  1100. uart_parents2, ARRAY_SIZE(uart_parents1),
  1101. STM32F7_RCC_DCKCFGR2, 4, 3,
  1102. STM32F4_RCC_APB1ENR, 18,
  1103. CLK_SET_RATE_PARENT,
  1104. },
  1105. {
  1106. CLK_UART4, "uart4",
  1107. uart_parents2, ARRAY_SIZE(uart_parents1),
  1108. STM32F7_RCC_DCKCFGR2, 6, 3,
  1109. STM32F4_RCC_APB1ENR, 19,
  1110. CLK_SET_RATE_PARENT,
  1111. },
  1112. {
  1113. CLK_UART5, "uart5",
  1114. uart_parents2, ARRAY_SIZE(uart_parents1),
  1115. STM32F7_RCC_DCKCFGR2, 8, 3,
  1116. STM32F4_RCC_APB1ENR, 20,
  1117. CLK_SET_RATE_PARENT,
  1118. },
  1119. {
  1120. CLK_USART6, "usart6",
  1121. uart_parents1, ARRAY_SIZE(uart_parents1),
  1122. STM32F7_RCC_DCKCFGR2, 10, 3,
  1123. STM32F4_RCC_APB2ENR, 5,
  1124. CLK_SET_RATE_PARENT,
  1125. },
  1126. {
  1127. CLK_UART7, "uart7",
  1128. uart_parents2, ARRAY_SIZE(uart_parents1),
  1129. STM32F7_RCC_DCKCFGR2, 12, 3,
  1130. STM32F4_RCC_APB1ENR, 30,
  1131. CLK_SET_RATE_PARENT,
  1132. },
  1133. {
  1134. CLK_UART8, "uart8",
  1135. uart_parents2, ARRAY_SIZE(uart_parents1),
  1136. STM32F7_RCC_DCKCFGR2, 14, 3,
  1137. STM32F4_RCC_APB1ENR, 31,
  1138. CLK_SET_RATE_PARENT,
  1139. },
  1140. {
  1141. CLK_I2C1, "i2c1",
  1142. i2c_parents, ARRAY_SIZE(i2c_parents),
  1143. STM32F7_RCC_DCKCFGR2, 16, 3,
  1144. STM32F4_RCC_APB1ENR, 21,
  1145. CLK_SET_RATE_PARENT,
  1146. },
  1147. {
  1148. CLK_I2C2, "i2c2",
  1149. i2c_parents, ARRAY_SIZE(i2c_parents),
  1150. STM32F7_RCC_DCKCFGR2, 18, 3,
  1151. STM32F4_RCC_APB1ENR, 22,
  1152. CLK_SET_RATE_PARENT,
  1153. },
  1154. {
  1155. CLK_I2C3, "i2c3",
  1156. i2c_parents, ARRAY_SIZE(i2c_parents),
  1157. STM32F7_RCC_DCKCFGR2, 20, 3,
  1158. STM32F4_RCC_APB1ENR, 23,
  1159. CLK_SET_RATE_PARENT,
  1160. },
  1161. {
  1162. CLK_I2C4, "i2c4",
  1163. i2c_parents, ARRAY_SIZE(i2c_parents),
  1164. STM32F7_RCC_DCKCFGR2, 22, 3,
  1165. STM32F4_RCC_APB1ENR, 24,
  1166. CLK_SET_RATE_PARENT,
  1167. },
  1168. {
  1169. CLK_LPTIMER, "lptim1",
  1170. lptim_parent, ARRAY_SIZE(lptim_parent),
  1171. STM32F7_RCC_DCKCFGR2, 24, 3,
  1172. STM32F4_RCC_APB1ENR, 9,
  1173. CLK_SET_RATE_PARENT
  1174. },
  1175. };
  1176. static const struct stm32_aux_clk stm32f769_aux_clk[] = {
  1177. {
  1178. CLK_LCD, "lcd-tft", lcd_parent, ARRAY_SIZE(lcd_parent),
  1179. NO_MUX, 0, 0,
  1180. STM32F4_RCC_APB2ENR, 26,
  1181. CLK_SET_RATE_PARENT
  1182. },
  1183. {
  1184. CLK_I2S, "i2s", i2s_parents, ARRAY_SIZE(i2s_parents),
  1185. STM32F4_RCC_CFGR, 23, 1,
  1186. NO_GATE, 0,
  1187. CLK_SET_RATE_PARENT
  1188. },
  1189. {
  1190. CLK_SAI1, "sai1_clk", sai_parents, ARRAY_SIZE(sai_parents),
  1191. STM32F4_RCC_DCKCFGR, 20, 3,
  1192. STM32F4_RCC_APB2ENR, 22,
  1193. CLK_SET_RATE_PARENT
  1194. },
  1195. {
  1196. CLK_SAI2, "sai2_clk", sai_parents, ARRAY_SIZE(sai_parents),
  1197. STM32F4_RCC_DCKCFGR, 22, 3,
  1198. STM32F4_RCC_APB2ENR, 23,
  1199. CLK_SET_RATE_PARENT
  1200. },
  1201. {
  1202. NO_IDX, "pll48", pll48_parents, ARRAY_SIZE(pll48_parents),
  1203. STM32F7_RCC_DCKCFGR2, 27, 1,
  1204. NO_GATE, 0,
  1205. 0
  1206. },
  1207. {
  1208. NO_IDX, "sdmux1", sdmux_parents, ARRAY_SIZE(sdmux_parents),
  1209. STM32F7_RCC_DCKCFGR2, 28, 1,
  1210. NO_GATE, 0,
  1211. 0
  1212. },
  1213. {
  1214. NO_IDX, "sdmux2", sdmux_parents, ARRAY_SIZE(sdmux_parents),
  1215. STM32F7_RCC_DCKCFGR2, 29, 1,
  1216. NO_GATE, 0,
  1217. 0
  1218. },
  1219. {
  1220. CLK_HDMI_CEC, "hdmi-cec",
  1221. hdmi_parents, ARRAY_SIZE(hdmi_parents),
  1222. STM32F7_RCC_DCKCFGR2, 26, 1,
  1223. NO_GATE, 0,
  1224. 0
  1225. },
  1226. {
  1227. CLK_SPDIF, "spdif-rx",
  1228. spdif_parent, ARRAY_SIZE(spdif_parent),
  1229. STM32F7_RCC_DCKCFGR2, 22, 3,
  1230. STM32F4_RCC_APB2ENR, 23,
  1231. CLK_SET_RATE_PARENT
  1232. },
  1233. {
  1234. CLK_USART1, "usart1",
  1235. uart_parents1, ARRAY_SIZE(uart_parents1),
  1236. STM32F7_RCC_DCKCFGR2, 0, 3,
  1237. STM32F4_RCC_APB2ENR, 4,
  1238. CLK_SET_RATE_PARENT,
  1239. },
  1240. {
  1241. CLK_USART2, "usart2",
  1242. uart_parents2, ARRAY_SIZE(uart_parents1),
  1243. STM32F7_RCC_DCKCFGR2, 2, 3,
  1244. STM32F4_RCC_APB1ENR, 17,
  1245. CLK_SET_RATE_PARENT,
  1246. },
  1247. {
  1248. CLK_USART3, "usart3",
  1249. uart_parents2, ARRAY_SIZE(uart_parents1),
  1250. STM32F7_RCC_DCKCFGR2, 4, 3,
  1251. STM32F4_RCC_APB1ENR, 18,
  1252. CLK_SET_RATE_PARENT,
  1253. },
  1254. {
  1255. CLK_UART4, "uart4",
  1256. uart_parents2, ARRAY_SIZE(uart_parents1),
  1257. STM32F7_RCC_DCKCFGR2, 6, 3,
  1258. STM32F4_RCC_APB1ENR, 19,
  1259. CLK_SET_RATE_PARENT,
  1260. },
  1261. {
  1262. CLK_UART5, "uart5",
  1263. uart_parents2, ARRAY_SIZE(uart_parents1),
  1264. STM32F7_RCC_DCKCFGR2, 8, 3,
  1265. STM32F4_RCC_APB1ENR, 20,
  1266. CLK_SET_RATE_PARENT,
  1267. },
  1268. {
  1269. CLK_USART6, "usart6",
  1270. uart_parents1, ARRAY_SIZE(uart_parents1),
  1271. STM32F7_RCC_DCKCFGR2, 10, 3,
  1272. STM32F4_RCC_APB2ENR, 5,
  1273. CLK_SET_RATE_PARENT,
  1274. },
  1275. {
  1276. CLK_UART7, "uart7",
  1277. uart_parents2, ARRAY_SIZE(uart_parents1),
  1278. STM32F7_RCC_DCKCFGR2, 12, 3,
  1279. STM32F4_RCC_APB1ENR, 30,
  1280. CLK_SET_RATE_PARENT,
  1281. },
  1282. {
  1283. CLK_UART8, "uart8",
  1284. uart_parents2, ARRAY_SIZE(uart_parents1),
  1285. STM32F7_RCC_DCKCFGR2, 14, 3,
  1286. STM32F4_RCC_APB1ENR, 31,
  1287. CLK_SET_RATE_PARENT,
  1288. },
  1289. {
  1290. CLK_I2C1, "i2c1",
  1291. i2c_parents, ARRAY_SIZE(i2c_parents),
  1292. STM32F7_RCC_DCKCFGR2, 16, 3,
  1293. STM32F4_RCC_APB1ENR, 21,
  1294. CLK_SET_RATE_PARENT,
  1295. },
  1296. {
  1297. CLK_I2C2, "i2c2",
  1298. i2c_parents, ARRAY_SIZE(i2c_parents),
  1299. STM32F7_RCC_DCKCFGR2, 18, 3,
  1300. STM32F4_RCC_APB1ENR, 22,
  1301. CLK_SET_RATE_PARENT,
  1302. },
  1303. {
  1304. CLK_I2C3, "i2c3",
  1305. i2c_parents, ARRAY_SIZE(i2c_parents),
  1306. STM32F7_RCC_DCKCFGR2, 20, 3,
  1307. STM32F4_RCC_APB1ENR, 23,
  1308. CLK_SET_RATE_PARENT,
  1309. },
  1310. {
  1311. CLK_I2C4, "i2c4",
  1312. i2c_parents, ARRAY_SIZE(i2c_parents),
  1313. STM32F7_RCC_DCKCFGR2, 22, 3,
  1314. STM32F4_RCC_APB1ENR, 24,
  1315. CLK_SET_RATE_PARENT,
  1316. },
  1317. {
  1318. CLK_LPTIMER, "lptim1",
  1319. lptim_parent, ARRAY_SIZE(lptim_parent),
  1320. STM32F7_RCC_DCKCFGR2, 24, 3,
  1321. STM32F4_RCC_APB1ENR, 9,
  1322. CLK_SET_RATE_PARENT
  1323. },
  1324. {
  1325. CLK_F769_DSI, "dsi",
  1326. dsi_parent, ARRAY_SIZE(dsi_parent),
  1327. STM32F7_RCC_DCKCFGR2, 0, 1,
  1328. STM32F4_RCC_APB2ENR, 27,
  1329. CLK_SET_RATE_PARENT
  1330. },
  1331. {
  1332. CLK_DFSDM1, "dfsdm1",
  1333. dfsdm1_src, ARRAY_SIZE(dfsdm1_src),
  1334. STM32F4_RCC_DCKCFGR, 25, 1,
  1335. STM32F4_RCC_APB2ENR, 29,
  1336. CLK_SET_RATE_PARENT
  1337. },
  1338. {
  1339. CLK_ADFSDM1, "adfsdm1",
  1340. adsfdm1_parent, ARRAY_SIZE(adsfdm1_parent),
  1341. STM32F4_RCC_DCKCFGR, 26, 1,
  1342. STM32F4_RCC_APB2ENR, 29,
  1343. CLK_SET_RATE_PARENT
  1344. },
  1345. };
  1346. static const struct stm32f4_clk_data stm32f429_clk_data = {
  1347. .end_primary = END_PRIMARY_CLK,
  1348. .gates_data = stm32f429_gates,
  1349. .gates_map = stm32f42xx_gate_map,
  1350. .gates_num = ARRAY_SIZE(stm32f429_gates),
  1351. .pll_data = stm32f429_pll,
  1352. .aux_clk = stm32f429_aux_clk,
  1353. .aux_clk_num = ARRAY_SIZE(stm32f429_aux_clk),
  1354. };
  1355. static const struct stm32f4_clk_data stm32f469_clk_data = {
  1356. .end_primary = END_PRIMARY_CLK,
  1357. .gates_data = stm32f469_gates,
  1358. .gates_map = stm32f46xx_gate_map,
  1359. .gates_num = ARRAY_SIZE(stm32f469_gates),
  1360. .pll_data = stm32f469_pll,
  1361. .aux_clk = stm32f469_aux_clk,
  1362. .aux_clk_num = ARRAY_SIZE(stm32f469_aux_clk),
  1363. };
  1364. static const struct stm32f4_clk_data stm32f746_clk_data = {
  1365. .end_primary = END_PRIMARY_CLK_F7,
  1366. .gates_data = stm32f746_gates,
  1367. .gates_map = stm32f746_gate_map,
  1368. .gates_num = ARRAY_SIZE(stm32f746_gates),
  1369. .pll_data = stm32f469_pll,
  1370. .aux_clk = stm32f746_aux_clk,
  1371. .aux_clk_num = ARRAY_SIZE(stm32f746_aux_clk),
  1372. };
  1373. static const struct stm32f4_clk_data stm32f769_clk_data = {
  1374. .end_primary = END_PRIMARY_CLK_F7,
  1375. .gates_data = stm32f769_gates,
  1376. .gates_map = stm32f769_gate_map,
  1377. .gates_num = ARRAY_SIZE(stm32f769_gates),
  1378. .pll_data = stm32f469_pll,
  1379. .aux_clk = stm32f769_aux_clk,
  1380. .aux_clk_num = ARRAY_SIZE(stm32f769_aux_clk),
  1381. };
  1382. static const struct of_device_id stm32f4_of_match[] = {
  1383. {
  1384. .compatible = "st,stm32f42xx-rcc",
  1385. .data = &stm32f429_clk_data
  1386. },
  1387. {
  1388. .compatible = "st,stm32f469-rcc",
  1389. .data = &stm32f469_clk_data
  1390. },
  1391. {
  1392. .compatible = "st,stm32f746-rcc",
  1393. .data = &stm32f746_clk_data
  1394. },
  1395. {
  1396. .compatible = "st,stm32f769-rcc",
  1397. .data = &stm32f769_clk_data
  1398. },
  1399. {}
  1400. };
  1401. static struct clk_hw *stm32_register_aux_clk(const char *name,
  1402. const char * const *parent_names, int num_parents,
  1403. int offset_mux, u8 shift, u8 mask,
  1404. int offset_gate, u8 bit_idx,
  1405. unsigned long flags, spinlock_t *lock)
  1406. {
  1407. struct clk_hw *hw;
  1408. struct clk_gate *gate = NULL;
  1409. struct clk_mux *mux = NULL;
  1410. struct clk_hw *mux_hw = NULL, *gate_hw = NULL;
  1411. const struct clk_ops *mux_ops = NULL, *gate_ops = NULL;
  1412. if (offset_gate != NO_GATE) {
  1413. gate = kzalloc(sizeof(*gate), GFP_KERNEL);
  1414. if (!gate) {
  1415. hw = ERR_PTR(-EINVAL);
  1416. goto fail;
  1417. }
  1418. gate->reg = base + offset_gate;
  1419. gate->bit_idx = bit_idx;
  1420. gate->flags = 0;
  1421. gate->lock = lock;
  1422. gate_hw = &gate->hw;
  1423. gate_ops = &clk_gate_ops;
  1424. }
  1425. if (offset_mux != NO_MUX) {
  1426. mux = kzalloc(sizeof(*mux), GFP_KERNEL);
  1427. if (!mux) {
  1428. hw = ERR_PTR(-EINVAL);
  1429. goto fail;
  1430. }
  1431. mux->reg = base + offset_mux;
  1432. mux->shift = shift;
  1433. mux->mask = mask;
  1434. mux->flags = 0;
  1435. mux_hw = &mux->hw;
  1436. mux_ops = &clk_mux_ops;
  1437. }
  1438. if (mux_hw == NULL && gate_hw == NULL) {
  1439. hw = ERR_PTR(-EINVAL);
  1440. goto fail;
  1441. }
  1442. hw = clk_hw_register_composite(NULL, name, parent_names, num_parents,
  1443. mux_hw, mux_ops,
  1444. NULL, NULL,
  1445. gate_hw, gate_ops,
  1446. flags);
  1447. fail:
  1448. if (IS_ERR(hw)) {
  1449. kfree(gate);
  1450. kfree(mux);
  1451. }
  1452. return hw;
  1453. }
  1454. static void __init stm32f4_rcc_init(struct device_node *np)
  1455. {
  1456. const char *hse_clk, *i2s_in_clk;
  1457. int n;
  1458. const struct of_device_id *match;
  1459. const struct stm32f4_clk_data *data;
  1460. unsigned long pllm;
  1461. struct clk_hw *pll_src_hw;
  1462. base = of_iomap(np, 0);
  1463. if (!base) {
  1464. pr_err("%pOFn: unable to map resource\n", np);
  1465. return;
  1466. }
  1467. pdrm = syscon_regmap_lookup_by_phandle(np, "st,syscfg");
  1468. if (IS_ERR(pdrm)) {
  1469. pdrm = NULL;
  1470. pr_warn("%s: Unable to get syscfg\n", __func__);
  1471. }
  1472. match = of_match_node(stm32f4_of_match, np);
  1473. if (WARN_ON(!match))
  1474. return;
  1475. data = match->data;
  1476. stm32fx_end_primary_clk = data->end_primary;
  1477. clks = kmalloc_array(data->gates_num + stm32fx_end_primary_clk,
  1478. sizeof(*clks), GFP_KERNEL);
  1479. if (!clks)
  1480. goto fail;
  1481. stm32f4_gate_map = data->gates_map;
  1482. hse_clk = of_clk_get_parent_name(np, 0);
  1483. dsi_parent[0] = hse_clk;
  1484. pllsrc_parent[1] = hse_clk;
  1485. i2s_in_clk = of_clk_get_parent_name(np, 1);
  1486. i2s_parents[1] = i2s_in_clk;
  1487. sai_parents[2] = i2s_in_clk;
  1488. if (of_device_is_compatible(np, "st,stm32f769-rcc")) {
  1489. clk_hw_register_gate(NULL, "dfsdm1_apb", "apb2_div", 0,
  1490. base + STM32F4_RCC_APB2ENR, 29,
  1491. CLK_IGNORE_UNUSED, &stm32f4_clk_lock);
  1492. dsi_parent[0] = pll_src;
  1493. sai_parents[3] = pll_src;
  1494. }
  1495. clks[CLK_HSI] = clk_hw_register_fixed_rate_with_accuracy(NULL, "hsi",
  1496. NULL, 0, 16000000, 160000);
  1497. pll_src_hw = clk_hw_register_mux(NULL, pll_src, pllsrc_parent,
  1498. ARRAY_SIZE(pllsrc_parent), 0,
  1499. base + STM32F4_RCC_PLLCFGR, 22, 1, 0,
  1500. &stm32f4_clk_lock);
  1501. pllm = readl(base + STM32F4_RCC_PLLCFGR) & 0x3f;
  1502. clk_hw_register_fixed_factor(NULL, "vco_in", pll_src,
  1503. 0, 1, pllm);
  1504. stm32f4_rcc_register_pll("vco_in", &data->pll_data[0],
  1505. &stm32f4_clk_lock);
  1506. clks[PLL_VCO_I2S] = stm32f4_rcc_register_pll("vco_in",
  1507. &data->pll_data[1], &stm32f4_clk_lock);
  1508. clks[PLL_VCO_SAI] = stm32f4_rcc_register_pll("vco_in",
  1509. &data->pll_data[2], &stm32f4_clk_lock);
  1510. for (n = 0; n < MAX_POST_DIV; n++) {
  1511. const struct stm32f4_pll_post_div_data *post_div;
  1512. struct clk_hw *hw;
  1513. post_div = &post_div_data[n];
  1514. hw = clk_register_pll_div(post_div->name,
  1515. post_div->parent,
  1516. post_div->flag,
  1517. base + post_div->offset,
  1518. post_div->shift,
  1519. post_div->width,
  1520. post_div->flag_div,
  1521. post_div->div_table,
  1522. clks[post_div->pll_idx],
  1523. &stm32f4_clk_lock);
  1524. if (post_div->idx != NO_IDX)
  1525. clks[post_div->idx] = hw;
  1526. }
  1527. sys_parents[1] = hse_clk;
  1528. clks[CLK_SYSCLK] = clk_hw_register_mux_table(
  1529. NULL, "sys", sys_parents, ARRAY_SIZE(sys_parents), 0,
  1530. base + STM32F4_RCC_CFGR, 0, 3, 0, NULL, &stm32f4_clk_lock);
  1531. clk_register_divider_table(NULL, "ahb_div", "sys",
  1532. CLK_SET_RATE_PARENT, base + STM32F4_RCC_CFGR,
  1533. 4, 4, 0, ahb_div_table, &stm32f4_clk_lock);
  1534. clk_register_divider_table(NULL, "apb1_div", "ahb_div",
  1535. CLK_SET_RATE_PARENT, base + STM32F4_RCC_CFGR,
  1536. 10, 3, 0, apb_div_table, &stm32f4_clk_lock);
  1537. clk_register_apb_mul(NULL, "apb1_mul", "apb1_div",
  1538. CLK_SET_RATE_PARENT, 12);
  1539. clk_register_divider_table(NULL, "apb2_div", "ahb_div",
  1540. CLK_SET_RATE_PARENT, base + STM32F4_RCC_CFGR,
  1541. 13, 3, 0, apb_div_table, &stm32f4_clk_lock);
  1542. clk_register_apb_mul(NULL, "apb2_mul", "apb2_div",
  1543. CLK_SET_RATE_PARENT, 15);
  1544. clks[SYSTICK] = clk_hw_register_fixed_factor(NULL, "systick", "ahb_div",
  1545. 0, 1, 8);
  1546. clks[FCLK] = clk_hw_register_fixed_factor(NULL, "fclk", "ahb_div",
  1547. 0, 1, 1);
  1548. for (n = 0; n < data->gates_num; n++) {
  1549. const struct stm32f4_gate_data *gd;
  1550. unsigned int secondary;
  1551. int idx;
  1552. gd = &data->gates_data[n];
  1553. secondary = 8 * (gd->offset - STM32F4_RCC_AHB1ENR) +
  1554. gd->bit_idx;
  1555. idx = stm32f4_rcc_lookup_clk_idx(0, secondary);
  1556. if (idx < 0)
  1557. goto fail;
  1558. clks[idx] = clk_hw_register_gate(
  1559. NULL, gd->name, gd->parent_name, gd->flags,
  1560. base + gd->offset, gd->bit_idx, 0, &stm32f4_clk_lock);
  1561. if (IS_ERR(clks[idx])) {
  1562. pr_err("%pOF: Unable to register leaf clock %s\n",
  1563. np, gd->name);
  1564. goto fail;
  1565. }
  1566. }
  1567. clks[CLK_LSI] = clk_register_rgate(NULL, "lsi", "clk-lsi", 0,
  1568. base + STM32F4_RCC_CSR, 0, 1, 0, &stm32f4_clk_lock);
  1569. if (IS_ERR(clks[CLK_LSI])) {
  1570. pr_err("Unable to register lsi clock\n");
  1571. goto fail;
  1572. }
  1573. clks[CLK_LSE] = clk_register_rgate(NULL, "lse", "clk-lse", 0,
  1574. base + STM32F4_RCC_BDCR, 0, 1, 0, &stm32f4_clk_lock);
  1575. if (IS_ERR(clks[CLK_LSE])) {
  1576. pr_err("Unable to register lse clock\n");
  1577. goto fail;
  1578. }
  1579. clks[CLK_HSE_RTC] = clk_hw_register_divider(NULL, "hse-rtc", "clk-hse",
  1580. 0, base + STM32F4_RCC_CFGR, 16, 5, 0,
  1581. &stm32f4_clk_lock);
  1582. if (IS_ERR(clks[CLK_HSE_RTC])) {
  1583. pr_err("Unable to register hse-rtc clock\n");
  1584. goto fail;
  1585. }
  1586. clks[CLK_RTC] = stm32_register_cclk(NULL, "rtc", rtc_parents, 4,
  1587. base + STM32F4_RCC_BDCR, 15, 8, 0, &stm32f4_clk_lock);
  1588. if (IS_ERR(clks[CLK_RTC])) {
  1589. pr_err("Unable to register rtc clock\n");
  1590. goto fail;
  1591. }
  1592. for (n = 0; n < data->aux_clk_num; n++) {
  1593. const struct stm32_aux_clk *aux_clk;
  1594. struct clk_hw *hw;
  1595. aux_clk = &data->aux_clk[n];
  1596. hw = stm32_register_aux_clk(aux_clk->name,
  1597. aux_clk->parent_names, aux_clk->num_parents,
  1598. aux_clk->offset_mux, aux_clk->shift,
  1599. aux_clk->mask, aux_clk->offset_gate,
  1600. aux_clk->bit_idx, aux_clk->flags,
  1601. &stm32f4_clk_lock);
  1602. if (IS_ERR(hw)) {
  1603. pr_warn("Unable to register %s clk\n", aux_clk->name);
  1604. continue;
  1605. }
  1606. if (aux_clk->idx != NO_IDX)
  1607. clks[aux_clk->idx] = hw;
  1608. }
  1609. if (of_device_is_compatible(np, "st,stm32f746-rcc")) {
  1610. clk_hw_register_fixed_factor(NULL, "hsi_div488", "hsi", 0,
  1611. 1, 488);
  1612. clks[CLK_PLL_SRC] = pll_src_hw;
  1613. }
  1614. of_clk_add_hw_provider(np, stm32f4_rcc_lookup_clk, NULL);
  1615. return;
  1616. fail:
  1617. kfree(clks);
  1618. iounmap(base);
  1619. }
  1620. CLK_OF_DECLARE_DRIVER(stm32f42xx_rcc, "st,stm32f42xx-rcc", stm32f4_rcc_init);
  1621. CLK_OF_DECLARE_DRIVER(stm32f46xx_rcc, "st,stm32f469-rcc", stm32f4_rcc_init);
  1622. CLK_OF_DECLARE_DRIVER(stm32f746_rcc, "st,stm32f746-rcc", stm32f4_rcc_init);
  1623. CLK_OF_DECLARE_DRIVER(stm32f769_rcc, "st,stm32f769-rcc", stm32f4_rcc_init);