clk-scmi.c 5.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * System Control and Power Interface (SCMI) Protocol based clock driver
  4. *
  5. * Copyright (C) 2018-2020 ARM Ltd.
  6. */
  7. #include <linux/clk-provider.h>
  8. #include <linux/device.h>
  9. #include <linux/err.h>
  10. #include <linux/of.h>
  11. #include <linux/module.h>
  12. #include <linux/scmi_protocol.h>
  13. #include <asm/div64.h>
  14. static const struct scmi_clk_proto_ops *clk_ops;
  15. struct scmi_clk {
  16. u32 id;
  17. struct clk_hw hw;
  18. const struct scmi_clock_info *info;
  19. const struct scmi_protocol_handle *ph;
  20. };
  21. #define to_scmi_clk(clk) container_of(clk, struct scmi_clk, hw)
  22. static unsigned long scmi_clk_recalc_rate(struct clk_hw *hw,
  23. unsigned long parent_rate)
  24. {
  25. int ret;
  26. u64 rate;
  27. struct scmi_clk *clk = to_scmi_clk(hw);
  28. ret = clk_ops->rate_get(clk->ph, clk->id, &rate);
  29. if (ret)
  30. return 0;
  31. return rate;
  32. }
  33. static long scmi_clk_round_rate(struct clk_hw *hw, unsigned long rate,
  34. unsigned long *parent_rate)
  35. {
  36. u64 fmin, fmax, ftmp;
  37. struct scmi_clk *clk = to_scmi_clk(hw);
  38. /*
  39. * We can't figure out what rate it will be, so just return the
  40. * rate back to the caller. scmi_clk_recalc_rate() will be called
  41. * after the rate is set and we'll know what rate the clock is
  42. * running at then.
  43. */
  44. if (clk->info->rate_discrete)
  45. return rate;
  46. fmin = clk->info->range.min_rate;
  47. fmax = clk->info->range.max_rate;
  48. if (rate <= fmin)
  49. return fmin;
  50. else if (rate >= fmax)
  51. return fmax;
  52. ftmp = rate - fmin;
  53. ftmp += clk->info->range.step_size - 1; /* to round up */
  54. do_div(ftmp, clk->info->range.step_size);
  55. return ftmp * clk->info->range.step_size + fmin;
  56. }
  57. static int scmi_clk_set_rate(struct clk_hw *hw, unsigned long rate,
  58. unsigned long parent_rate)
  59. {
  60. struct scmi_clk *clk = to_scmi_clk(hw);
  61. return clk_ops->rate_set(clk->ph, clk->id, rate);
  62. }
  63. static int scmi_clk_enable(struct clk_hw *hw)
  64. {
  65. struct scmi_clk *clk = to_scmi_clk(hw);
  66. return clk_ops->enable(clk->ph, clk->id);
  67. }
  68. static void scmi_clk_disable(struct clk_hw *hw)
  69. {
  70. struct scmi_clk *clk = to_scmi_clk(hw);
  71. clk_ops->disable(clk->ph, clk->id);
  72. }
  73. static const struct clk_ops scmi_clk_ops = {
  74. .recalc_rate = scmi_clk_recalc_rate,
  75. .round_rate = scmi_clk_round_rate,
  76. .set_rate = scmi_clk_set_rate,
  77. /*
  78. * We can't provide enable/disable callback as we can't perform the same
  79. * in atomic context. Since the clock framework provides standard API
  80. * clk_prepare_enable that helps cases using clk_enable in non-atomic
  81. * context, it should be fine providing prepare/unprepare.
  82. */
  83. .prepare = scmi_clk_enable,
  84. .unprepare = scmi_clk_disable,
  85. };
  86. static int scmi_clk_ops_init(struct device *dev, struct scmi_clk *sclk)
  87. {
  88. int ret;
  89. unsigned long min_rate, max_rate;
  90. struct clk_init_data init = {
  91. .flags = CLK_GET_RATE_NOCACHE,
  92. .num_parents = 0,
  93. .ops = &scmi_clk_ops,
  94. .name = sclk->info->name,
  95. };
  96. sclk->hw.init = &init;
  97. ret = devm_clk_hw_register(dev, &sclk->hw);
  98. if (ret)
  99. return ret;
  100. if (sclk->info->rate_discrete) {
  101. int num_rates = sclk->info->list.num_rates;
  102. if (num_rates <= 0)
  103. return -EINVAL;
  104. min_rate = sclk->info->list.rates[0];
  105. max_rate = sclk->info->list.rates[num_rates - 1];
  106. } else {
  107. min_rate = sclk->info->range.min_rate;
  108. max_rate = sclk->info->range.max_rate;
  109. }
  110. clk_hw_set_rate_range(&sclk->hw, min_rate, max_rate);
  111. return ret;
  112. }
  113. static int scmi_clocks_probe(struct scmi_device *sdev)
  114. {
  115. int idx, count, err;
  116. struct clk_hw **hws;
  117. struct clk_hw_onecell_data *clk_data;
  118. struct device *dev = &sdev->dev;
  119. struct device_node *np = dev->of_node;
  120. const struct scmi_handle *handle = sdev->handle;
  121. struct scmi_protocol_handle *ph;
  122. if (!handle)
  123. return -ENODEV;
  124. clk_ops = handle->devm_get_protocol(sdev, SCMI_PROTOCOL_CLOCK, &ph);
  125. if (IS_ERR(clk_ops))
  126. return PTR_ERR(clk_ops);
  127. count = clk_ops->count_get(ph);
  128. if (count < 0) {
  129. dev_err(dev, "%pOFn: invalid clock output count\n", np);
  130. return -EINVAL;
  131. }
  132. clk_data = devm_kzalloc(dev, struct_size(clk_data, hws, count),
  133. GFP_KERNEL);
  134. if (!clk_data)
  135. return -ENOMEM;
  136. clk_data->num = count;
  137. hws = clk_data->hws;
  138. for (idx = 0; idx < count; idx++) {
  139. struct scmi_clk *sclk;
  140. sclk = devm_kzalloc(dev, sizeof(*sclk), GFP_KERNEL);
  141. if (!sclk)
  142. return -ENOMEM;
  143. sclk->info = clk_ops->info_get(ph, idx);
  144. if (!sclk->info) {
  145. dev_dbg(dev, "invalid clock info for idx %d\n", idx);
  146. continue;
  147. }
  148. sclk->id = idx;
  149. sclk->ph = ph;
  150. err = scmi_clk_ops_init(dev, sclk);
  151. if (err) {
  152. dev_err(dev, "failed to register clock %d\n", idx);
  153. devm_kfree(dev, sclk);
  154. hws[idx] = NULL;
  155. } else {
  156. dev_dbg(dev, "Registered clock:%s\n", sclk->info->name);
  157. hws[idx] = &sclk->hw;
  158. }
  159. }
  160. return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
  161. clk_data);
  162. }
  163. static const struct scmi_device_id scmi_id_table[] = {
  164. { SCMI_PROTOCOL_CLOCK, "clocks" },
  165. { },
  166. };
  167. MODULE_DEVICE_TABLE(scmi, scmi_id_table);
  168. static struct scmi_driver scmi_clocks_driver = {
  169. .name = "scmi-clocks",
  170. .probe = scmi_clocks_probe,
  171. .id_table = scmi_id_table,
  172. };
  173. module_scmi_driver(scmi_clocks_driver);
  174. MODULE_AUTHOR("Sudeep Holla <sudeep.holla@arm.com>");
  175. MODULE_DESCRIPTION("ARM SCMI clock driver");
  176. MODULE_LICENSE("GPL v2");