clk-max77686.c 7.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. //
  3. // clk-max77686.c - Clock driver for Maxim 77686/MAX77802
  4. //
  5. // Copyright (C) 2012 Samsung Electornics
  6. // Jonghwa Lee <jonghwa3.lee@samsung.com>
  7. #include <linux/kernel.h>
  8. #include <linux/slab.h>
  9. #include <linux/err.h>
  10. #include <linux/module.h>
  11. #include <linux/platform_device.h>
  12. #include <linux/mfd/max77620.h>
  13. #include <linux/mfd/max77686.h>
  14. #include <linux/mfd/max77686-private.h>
  15. #include <linux/clk-provider.h>
  16. #include <linux/mutex.h>
  17. #include <linux/clkdev.h>
  18. #include <linux/of.h>
  19. #include <linux/regmap.h>
  20. #include <dt-bindings/clock/maxim,max77686.h>
  21. #include <dt-bindings/clock/maxim,max77802.h>
  22. #include <dt-bindings/clock/maxim,max77620.h>
  23. #define MAX77802_CLOCK_LOW_JITTER_SHIFT 0x3
  24. enum max77686_chip_name {
  25. CHIP_MAX77686,
  26. CHIP_MAX77802,
  27. CHIP_MAX77620,
  28. };
  29. struct max77686_hw_clk_info {
  30. const char *name;
  31. u32 clk_reg;
  32. u32 clk_enable_mask;
  33. u32 flags;
  34. };
  35. struct max77686_clk_init_data {
  36. struct regmap *regmap;
  37. struct clk_hw hw;
  38. struct clk_init_data clk_idata;
  39. const struct max77686_hw_clk_info *clk_info;
  40. };
  41. struct max77686_clk_driver_data {
  42. enum max77686_chip_name chip;
  43. struct max77686_clk_init_data *max_clk_data;
  44. size_t num_clks;
  45. };
  46. static const struct
  47. max77686_hw_clk_info max77686_hw_clks_info[MAX77686_CLKS_NUM] = {
  48. [MAX77686_CLK_AP] = {
  49. .name = "32khz_ap",
  50. .clk_reg = MAX77686_REG_32KHZ,
  51. .clk_enable_mask = BIT(MAX77686_CLK_AP),
  52. },
  53. [MAX77686_CLK_CP] = {
  54. .name = "32khz_cp",
  55. .clk_reg = MAX77686_REG_32KHZ,
  56. .clk_enable_mask = BIT(MAX77686_CLK_CP),
  57. },
  58. [MAX77686_CLK_PMIC] = {
  59. .name = "32khz_pmic",
  60. .clk_reg = MAX77686_REG_32KHZ,
  61. .clk_enable_mask = BIT(MAX77686_CLK_PMIC),
  62. },
  63. };
  64. static const struct
  65. max77686_hw_clk_info max77802_hw_clks_info[MAX77802_CLKS_NUM] = {
  66. [MAX77802_CLK_32K_AP] = {
  67. .name = "32khz_ap",
  68. .clk_reg = MAX77802_REG_32KHZ,
  69. .clk_enable_mask = BIT(MAX77802_CLK_32K_AP),
  70. },
  71. [MAX77802_CLK_32K_CP] = {
  72. .name = "32khz_cp",
  73. .clk_reg = MAX77802_REG_32KHZ,
  74. .clk_enable_mask = BIT(MAX77802_CLK_32K_CP),
  75. },
  76. };
  77. static const struct
  78. max77686_hw_clk_info max77620_hw_clks_info[MAX77620_CLKS_NUM] = {
  79. [MAX77620_CLK_32K_OUT0] = {
  80. .name = "32khz_out0",
  81. .clk_reg = MAX77620_REG_CNFG1_32K,
  82. .clk_enable_mask = MAX77620_CNFG1_32K_OUT0_EN,
  83. },
  84. };
  85. static struct max77686_clk_init_data *to_max77686_clk_init_data(
  86. struct clk_hw *hw)
  87. {
  88. return container_of(hw, struct max77686_clk_init_data, hw);
  89. }
  90. static int max77686_clk_prepare(struct clk_hw *hw)
  91. {
  92. struct max77686_clk_init_data *max77686 = to_max77686_clk_init_data(hw);
  93. return regmap_update_bits(max77686->regmap, max77686->clk_info->clk_reg,
  94. max77686->clk_info->clk_enable_mask,
  95. max77686->clk_info->clk_enable_mask);
  96. }
  97. static void max77686_clk_unprepare(struct clk_hw *hw)
  98. {
  99. struct max77686_clk_init_data *max77686 = to_max77686_clk_init_data(hw);
  100. regmap_update_bits(max77686->regmap, max77686->clk_info->clk_reg,
  101. max77686->clk_info->clk_enable_mask,
  102. ~max77686->clk_info->clk_enable_mask);
  103. }
  104. static int max77686_clk_is_prepared(struct clk_hw *hw)
  105. {
  106. struct max77686_clk_init_data *max77686 = to_max77686_clk_init_data(hw);
  107. int ret;
  108. u32 val;
  109. ret = regmap_read(max77686->regmap, max77686->clk_info->clk_reg, &val);
  110. if (ret < 0)
  111. return -EINVAL;
  112. return val & max77686->clk_info->clk_enable_mask;
  113. }
  114. static unsigned long max77686_recalc_rate(struct clk_hw *hw,
  115. unsigned long parent_rate)
  116. {
  117. return 32768;
  118. }
  119. static const struct clk_ops max77686_clk_ops = {
  120. .prepare = max77686_clk_prepare,
  121. .unprepare = max77686_clk_unprepare,
  122. .is_prepared = max77686_clk_is_prepared,
  123. .recalc_rate = max77686_recalc_rate,
  124. };
  125. static struct clk_hw *
  126. of_clk_max77686_get(struct of_phandle_args *clkspec, void *data)
  127. {
  128. struct max77686_clk_driver_data *drv_data = data;
  129. unsigned int idx = clkspec->args[0];
  130. if (idx >= drv_data->num_clks) {
  131. pr_err("%s: invalid index %u\n", __func__, idx);
  132. return ERR_PTR(-EINVAL);
  133. }
  134. return &drv_data->max_clk_data[idx].hw;
  135. }
  136. static int max77686_clk_probe(struct platform_device *pdev)
  137. {
  138. struct device *dev = &pdev->dev;
  139. struct device *parent = dev->parent;
  140. const struct platform_device_id *id = platform_get_device_id(pdev);
  141. struct max77686_clk_driver_data *drv_data;
  142. const struct max77686_hw_clk_info *hw_clks;
  143. struct regmap *regmap;
  144. int i, ret, num_clks;
  145. drv_data = devm_kzalloc(dev, sizeof(*drv_data), GFP_KERNEL);
  146. if (!drv_data)
  147. return -ENOMEM;
  148. regmap = dev_get_regmap(parent, NULL);
  149. if (!regmap) {
  150. dev_err(dev, "Failed to get rtc regmap\n");
  151. return -ENODEV;
  152. }
  153. drv_data->chip = id->driver_data;
  154. switch (drv_data->chip) {
  155. case CHIP_MAX77686:
  156. num_clks = MAX77686_CLKS_NUM;
  157. hw_clks = max77686_hw_clks_info;
  158. break;
  159. case CHIP_MAX77802:
  160. num_clks = MAX77802_CLKS_NUM;
  161. hw_clks = max77802_hw_clks_info;
  162. break;
  163. case CHIP_MAX77620:
  164. num_clks = MAX77620_CLKS_NUM;
  165. hw_clks = max77620_hw_clks_info;
  166. break;
  167. default:
  168. dev_err(dev, "Unknown Chip ID\n");
  169. return -EINVAL;
  170. }
  171. drv_data->num_clks = num_clks;
  172. drv_data->max_clk_data = devm_kcalloc(dev, num_clks,
  173. sizeof(*drv_data->max_clk_data),
  174. GFP_KERNEL);
  175. if (!drv_data->max_clk_data)
  176. return -ENOMEM;
  177. for (i = 0; i < num_clks; i++) {
  178. struct max77686_clk_init_data *max_clk_data;
  179. const char *clk_name;
  180. max_clk_data = &drv_data->max_clk_data[i];
  181. max_clk_data->regmap = regmap;
  182. max_clk_data->clk_info = &hw_clks[i];
  183. max_clk_data->clk_idata.flags = hw_clks[i].flags;
  184. max_clk_data->clk_idata.ops = &max77686_clk_ops;
  185. if (parent->of_node &&
  186. !of_property_read_string_index(parent->of_node,
  187. "clock-output-names",
  188. i, &clk_name))
  189. max_clk_data->clk_idata.name = clk_name;
  190. else
  191. max_clk_data->clk_idata.name = hw_clks[i].name;
  192. max_clk_data->hw.init = &max_clk_data->clk_idata;
  193. ret = devm_clk_hw_register(dev, &max_clk_data->hw);
  194. if (ret) {
  195. dev_err(dev, "Failed to clock register: %d\n", ret);
  196. return ret;
  197. }
  198. ret = devm_clk_hw_register_clkdev(dev, &max_clk_data->hw,
  199. max_clk_data->clk_idata.name,
  200. NULL);
  201. if (ret < 0) {
  202. dev_err(dev, "Failed to clkdev register: %d\n", ret);
  203. return ret;
  204. }
  205. }
  206. if (parent->of_node) {
  207. ret = devm_of_clk_add_hw_provider(dev, of_clk_max77686_get,
  208. drv_data);
  209. if (ret < 0) {
  210. dev_err(dev, "Failed to register OF clock provider: %d\n",
  211. ret);
  212. return ret;
  213. }
  214. }
  215. /* MAX77802: Enable low-jitter mode on the 32khz clocks. */
  216. if (drv_data->chip == CHIP_MAX77802) {
  217. ret = regmap_update_bits(regmap, MAX77802_REG_32KHZ,
  218. 1 << MAX77802_CLOCK_LOW_JITTER_SHIFT,
  219. 1 << MAX77802_CLOCK_LOW_JITTER_SHIFT);
  220. if (ret < 0) {
  221. dev_err(dev, "Failed to config low-jitter: %d\n", ret);
  222. return ret;
  223. }
  224. }
  225. return 0;
  226. }
  227. static const struct platform_device_id max77686_clk_id[] = {
  228. { "max77686-clk", .driver_data = CHIP_MAX77686, },
  229. { "max77802-clk", .driver_data = CHIP_MAX77802, },
  230. { "max77620-clock", .driver_data = CHIP_MAX77620, },
  231. {},
  232. };
  233. MODULE_DEVICE_TABLE(platform, max77686_clk_id);
  234. static struct platform_driver max77686_clk_driver = {
  235. .driver = {
  236. .name = "max77686-clk",
  237. },
  238. .probe = max77686_clk_probe,
  239. .id_table = max77686_clk_id,
  240. };
  241. module_platform_driver(max77686_clk_driver);
  242. MODULE_DESCRIPTION("MAXIM 77686 Clock Driver");
  243. MODULE_AUTHOR("Jonghwa Lee <jonghwa3.lee@samsung.com>");
  244. MODULE_LICENSE("GPL");