clk-hsdk-pll.c 11 KB

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  1. /*
  2. * Synopsys HSDK SDP Generic PLL clock driver
  3. *
  4. * Copyright (C) 2017 Synopsys
  5. *
  6. * This file is licensed under the terms of the GNU General Public
  7. * License version 2. This program is licensed "as is" without any
  8. * warranty of any kind, whether express or implied.
  9. */
  10. #include <linux/clk-provider.h>
  11. #include <linux/delay.h>
  12. #include <linux/device.h>
  13. #include <linux/err.h>
  14. #include <linux/io.h>
  15. #include <linux/of.h>
  16. #include <linux/of_address.h>
  17. #include <linux/of_device.h>
  18. #include <linux/platform_device.h>
  19. #include <linux/slab.h>
  20. #define CGU_PLL_CTRL 0x000 /* ARC PLL control register */
  21. #define CGU_PLL_STATUS 0x004 /* ARC PLL status register */
  22. #define CGU_PLL_FMEAS 0x008 /* ARC PLL frequency measurement register */
  23. #define CGU_PLL_MON 0x00C /* ARC PLL monitor register */
  24. #define CGU_PLL_CTRL_ODIV_SHIFT 2
  25. #define CGU_PLL_CTRL_IDIV_SHIFT 4
  26. #define CGU_PLL_CTRL_FBDIV_SHIFT 9
  27. #define CGU_PLL_CTRL_BAND_SHIFT 20
  28. #define CGU_PLL_CTRL_ODIV_MASK GENMASK(3, CGU_PLL_CTRL_ODIV_SHIFT)
  29. #define CGU_PLL_CTRL_IDIV_MASK GENMASK(8, CGU_PLL_CTRL_IDIV_SHIFT)
  30. #define CGU_PLL_CTRL_FBDIV_MASK GENMASK(15, CGU_PLL_CTRL_FBDIV_SHIFT)
  31. #define CGU_PLL_CTRL_PD BIT(0)
  32. #define CGU_PLL_CTRL_BYPASS BIT(1)
  33. #define CGU_PLL_STATUS_LOCK BIT(0)
  34. #define CGU_PLL_STATUS_ERR BIT(1)
  35. #define HSDK_PLL_MAX_LOCK_TIME 100 /* 100 us */
  36. #define CGU_PLL_SOURCE_MAX 1
  37. #define CORE_IF_CLK_THRESHOLD_HZ 500000000
  38. #define CREG_CORE_IF_CLK_DIV_1 0x0
  39. #define CREG_CORE_IF_CLK_DIV_2 0x1
  40. struct hsdk_pll_cfg {
  41. u32 rate;
  42. u32 idiv;
  43. u32 fbdiv;
  44. u32 odiv;
  45. u32 band;
  46. u32 bypass;
  47. };
  48. static const struct hsdk_pll_cfg asdt_pll_cfg[] = {
  49. { 100000000, 0, 11, 3, 0, 0 },
  50. { 133000000, 0, 15, 3, 0, 0 },
  51. { 200000000, 1, 47, 3, 0, 0 },
  52. { 233000000, 1, 27, 2, 0, 0 },
  53. { 300000000, 1, 35, 2, 0, 0 },
  54. { 333000000, 1, 39, 2, 0, 0 },
  55. { 400000000, 1, 47, 2, 0, 0 },
  56. { 500000000, 0, 14, 1, 0, 0 },
  57. { 600000000, 0, 17, 1, 0, 0 },
  58. { 700000000, 0, 20, 1, 0, 0 },
  59. { 800000000, 0, 23, 1, 0, 0 },
  60. { 900000000, 1, 26, 0, 0, 0 },
  61. { 1000000000, 1, 29, 0, 0, 0 },
  62. { 1100000000, 1, 32, 0, 0, 0 },
  63. { 1200000000, 1, 35, 0, 0, 0 },
  64. { 1300000000, 1, 38, 0, 0, 0 },
  65. { 1400000000, 1, 41, 0, 0, 0 },
  66. { 1500000000, 1, 44, 0, 0, 0 },
  67. { 1600000000, 1, 47, 0, 0, 0 },
  68. {}
  69. };
  70. static const struct hsdk_pll_cfg hdmi_pll_cfg[] = {
  71. { 27000000, 0, 0, 0, 0, 1 },
  72. { 148500000, 0, 21, 3, 0, 0 },
  73. { 297000000, 0, 21, 2, 0, 0 },
  74. { 540000000, 0, 19, 1, 0, 0 },
  75. { 594000000, 0, 21, 1, 0, 0 },
  76. {}
  77. };
  78. struct hsdk_pll_clk {
  79. struct clk_hw hw;
  80. void __iomem *regs;
  81. void __iomem *spec_regs;
  82. const struct hsdk_pll_devdata *pll_devdata;
  83. struct device *dev;
  84. };
  85. struct hsdk_pll_devdata {
  86. const struct hsdk_pll_cfg *pll_cfg;
  87. int (*update_rate)(struct hsdk_pll_clk *clk, unsigned long rate,
  88. const struct hsdk_pll_cfg *cfg);
  89. };
  90. static int hsdk_pll_core_update_rate(struct hsdk_pll_clk *, unsigned long,
  91. const struct hsdk_pll_cfg *);
  92. static int hsdk_pll_comm_update_rate(struct hsdk_pll_clk *, unsigned long,
  93. const struct hsdk_pll_cfg *);
  94. static const struct hsdk_pll_devdata core_pll_devdata = {
  95. .pll_cfg = asdt_pll_cfg,
  96. .update_rate = hsdk_pll_core_update_rate,
  97. };
  98. static const struct hsdk_pll_devdata sdt_pll_devdata = {
  99. .pll_cfg = asdt_pll_cfg,
  100. .update_rate = hsdk_pll_comm_update_rate,
  101. };
  102. static const struct hsdk_pll_devdata hdmi_pll_devdata = {
  103. .pll_cfg = hdmi_pll_cfg,
  104. .update_rate = hsdk_pll_comm_update_rate,
  105. };
  106. static inline void hsdk_pll_write(struct hsdk_pll_clk *clk, u32 reg, u32 val)
  107. {
  108. iowrite32(val, clk->regs + reg);
  109. }
  110. static inline u32 hsdk_pll_read(struct hsdk_pll_clk *clk, u32 reg)
  111. {
  112. return ioread32(clk->regs + reg);
  113. }
  114. static inline void hsdk_pll_set_cfg(struct hsdk_pll_clk *clk,
  115. const struct hsdk_pll_cfg *cfg)
  116. {
  117. u32 val = 0;
  118. if (cfg->bypass) {
  119. val = hsdk_pll_read(clk, CGU_PLL_CTRL);
  120. val |= CGU_PLL_CTRL_BYPASS;
  121. } else {
  122. /* Powerdown and Bypass bits should be cleared */
  123. val |= cfg->idiv << CGU_PLL_CTRL_IDIV_SHIFT;
  124. val |= cfg->fbdiv << CGU_PLL_CTRL_FBDIV_SHIFT;
  125. val |= cfg->odiv << CGU_PLL_CTRL_ODIV_SHIFT;
  126. val |= cfg->band << CGU_PLL_CTRL_BAND_SHIFT;
  127. }
  128. dev_dbg(clk->dev, "write configuration: %#x\n", val);
  129. hsdk_pll_write(clk, CGU_PLL_CTRL, val);
  130. }
  131. static inline bool hsdk_pll_is_locked(struct hsdk_pll_clk *clk)
  132. {
  133. return !!(hsdk_pll_read(clk, CGU_PLL_STATUS) & CGU_PLL_STATUS_LOCK);
  134. }
  135. static inline bool hsdk_pll_is_err(struct hsdk_pll_clk *clk)
  136. {
  137. return !!(hsdk_pll_read(clk, CGU_PLL_STATUS) & CGU_PLL_STATUS_ERR);
  138. }
  139. static inline struct hsdk_pll_clk *to_hsdk_pll_clk(struct clk_hw *hw)
  140. {
  141. return container_of(hw, struct hsdk_pll_clk, hw);
  142. }
  143. static unsigned long hsdk_pll_recalc_rate(struct clk_hw *hw,
  144. unsigned long parent_rate)
  145. {
  146. u32 val;
  147. u64 rate;
  148. u32 idiv, fbdiv, odiv;
  149. struct hsdk_pll_clk *clk = to_hsdk_pll_clk(hw);
  150. val = hsdk_pll_read(clk, CGU_PLL_CTRL);
  151. dev_dbg(clk->dev, "current configuration: %#x\n", val);
  152. /* Check if PLL is bypassed */
  153. if (val & CGU_PLL_CTRL_BYPASS)
  154. return parent_rate;
  155. /* Check if PLL is disabled */
  156. if (val & CGU_PLL_CTRL_PD)
  157. return 0;
  158. /* input divider = reg.idiv + 1 */
  159. idiv = 1 + ((val & CGU_PLL_CTRL_IDIV_MASK) >> CGU_PLL_CTRL_IDIV_SHIFT);
  160. /* fb divider = 2*(reg.fbdiv + 1) */
  161. fbdiv = 2 * (1 + ((val & CGU_PLL_CTRL_FBDIV_MASK) >> CGU_PLL_CTRL_FBDIV_SHIFT));
  162. /* output divider = 2^(reg.odiv) */
  163. odiv = 1 << ((val & CGU_PLL_CTRL_ODIV_MASK) >> CGU_PLL_CTRL_ODIV_SHIFT);
  164. rate = (u64)parent_rate * fbdiv;
  165. do_div(rate, idiv * odiv);
  166. return rate;
  167. }
  168. static long hsdk_pll_round_rate(struct clk_hw *hw, unsigned long rate,
  169. unsigned long *prate)
  170. {
  171. int i;
  172. unsigned long best_rate;
  173. struct hsdk_pll_clk *clk = to_hsdk_pll_clk(hw);
  174. const struct hsdk_pll_cfg *pll_cfg = clk->pll_devdata->pll_cfg;
  175. if (pll_cfg[0].rate == 0)
  176. return -EINVAL;
  177. best_rate = pll_cfg[0].rate;
  178. for (i = 1; pll_cfg[i].rate != 0; i++) {
  179. if (abs(rate - pll_cfg[i].rate) < abs(rate - best_rate))
  180. best_rate = pll_cfg[i].rate;
  181. }
  182. dev_dbg(clk->dev, "chosen best rate: %lu\n", best_rate);
  183. return best_rate;
  184. }
  185. static int hsdk_pll_comm_update_rate(struct hsdk_pll_clk *clk,
  186. unsigned long rate,
  187. const struct hsdk_pll_cfg *cfg)
  188. {
  189. hsdk_pll_set_cfg(clk, cfg);
  190. /*
  191. * Wait until CGU relocks and check error status.
  192. * If after timeout CGU is unlocked yet return error.
  193. */
  194. udelay(HSDK_PLL_MAX_LOCK_TIME);
  195. if (!hsdk_pll_is_locked(clk))
  196. return -ETIMEDOUT;
  197. if (hsdk_pll_is_err(clk))
  198. return -EINVAL;
  199. return 0;
  200. }
  201. static int hsdk_pll_core_update_rate(struct hsdk_pll_clk *clk,
  202. unsigned long rate,
  203. const struct hsdk_pll_cfg *cfg)
  204. {
  205. /*
  206. * When core clock exceeds 500MHz, the divider for the interface
  207. * clock must be programmed to div-by-2.
  208. */
  209. if (rate > CORE_IF_CLK_THRESHOLD_HZ)
  210. iowrite32(CREG_CORE_IF_CLK_DIV_2, clk->spec_regs);
  211. hsdk_pll_set_cfg(clk, cfg);
  212. /*
  213. * Wait until CGU relocks and check error status.
  214. * If after timeout CGU is unlocked yet return error.
  215. */
  216. udelay(HSDK_PLL_MAX_LOCK_TIME);
  217. if (!hsdk_pll_is_locked(clk))
  218. return -ETIMEDOUT;
  219. if (hsdk_pll_is_err(clk))
  220. return -EINVAL;
  221. /*
  222. * Program divider to div-by-1 if we succesfuly set core clock below
  223. * 500MHz threshold.
  224. */
  225. if (rate <= CORE_IF_CLK_THRESHOLD_HZ)
  226. iowrite32(CREG_CORE_IF_CLK_DIV_1, clk->spec_regs);
  227. return 0;
  228. }
  229. static int hsdk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
  230. unsigned long parent_rate)
  231. {
  232. int i;
  233. struct hsdk_pll_clk *clk = to_hsdk_pll_clk(hw);
  234. const struct hsdk_pll_cfg *pll_cfg = clk->pll_devdata->pll_cfg;
  235. for (i = 0; pll_cfg[i].rate != 0; i++) {
  236. if (pll_cfg[i].rate == rate) {
  237. return clk->pll_devdata->update_rate(clk, rate,
  238. &pll_cfg[i]);
  239. }
  240. }
  241. dev_err(clk->dev, "invalid rate=%ld, parent_rate=%ld\n", rate,
  242. parent_rate);
  243. return -EINVAL;
  244. }
  245. static const struct clk_ops hsdk_pll_ops = {
  246. .recalc_rate = hsdk_pll_recalc_rate,
  247. .round_rate = hsdk_pll_round_rate,
  248. .set_rate = hsdk_pll_set_rate,
  249. };
  250. static int hsdk_pll_clk_probe(struct platform_device *pdev)
  251. {
  252. int ret;
  253. struct resource *mem;
  254. const char *parent_name;
  255. unsigned int num_parents;
  256. struct hsdk_pll_clk *pll_clk;
  257. struct clk_init_data init = { };
  258. struct device *dev = &pdev->dev;
  259. pll_clk = devm_kzalloc(dev, sizeof(*pll_clk), GFP_KERNEL);
  260. if (!pll_clk)
  261. return -ENOMEM;
  262. mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  263. pll_clk->regs = devm_ioremap_resource(dev, mem);
  264. if (IS_ERR(pll_clk->regs))
  265. return PTR_ERR(pll_clk->regs);
  266. init.name = dev->of_node->name;
  267. init.ops = &hsdk_pll_ops;
  268. parent_name = of_clk_get_parent_name(dev->of_node, 0);
  269. init.parent_names = &parent_name;
  270. num_parents = of_clk_get_parent_count(dev->of_node);
  271. if (num_parents == 0 || num_parents > CGU_PLL_SOURCE_MAX) {
  272. dev_err(dev, "wrong clock parents number: %u\n", num_parents);
  273. return -EINVAL;
  274. }
  275. init.num_parents = num_parents;
  276. pll_clk->hw.init = &init;
  277. pll_clk->dev = dev;
  278. pll_clk->pll_devdata = of_device_get_match_data(dev);
  279. if (!pll_clk->pll_devdata) {
  280. dev_err(dev, "No OF match data provided\n");
  281. return -EINVAL;
  282. }
  283. ret = devm_clk_hw_register(dev, &pll_clk->hw);
  284. if (ret) {
  285. dev_err(dev, "failed to register %s clock\n", init.name);
  286. return ret;
  287. }
  288. return of_clk_add_hw_provider(dev->of_node, of_clk_hw_simple_get,
  289. &pll_clk->hw);
  290. }
  291. static int hsdk_pll_clk_remove(struct platform_device *pdev)
  292. {
  293. of_clk_del_provider(pdev->dev.of_node);
  294. return 0;
  295. }
  296. static void __init of_hsdk_pll_clk_setup(struct device_node *node)
  297. {
  298. int ret;
  299. const char *parent_name;
  300. unsigned int num_parents;
  301. struct hsdk_pll_clk *pll_clk;
  302. struct clk_init_data init = { };
  303. pll_clk = kzalloc(sizeof(*pll_clk), GFP_KERNEL);
  304. if (!pll_clk)
  305. return;
  306. pll_clk->regs = of_iomap(node, 0);
  307. if (!pll_clk->regs) {
  308. pr_err("failed to map pll registers\n");
  309. goto err_free_pll_clk;
  310. }
  311. pll_clk->spec_regs = of_iomap(node, 1);
  312. if (!pll_clk->spec_regs) {
  313. pr_err("failed to map pll registers\n");
  314. goto err_unmap_comm_regs;
  315. }
  316. init.name = node->name;
  317. init.ops = &hsdk_pll_ops;
  318. parent_name = of_clk_get_parent_name(node, 0);
  319. init.parent_names = &parent_name;
  320. num_parents = of_clk_get_parent_count(node);
  321. if (num_parents > CGU_PLL_SOURCE_MAX) {
  322. pr_err("too much clock parents: %u\n", num_parents);
  323. goto err_unmap_spec_regs;
  324. }
  325. init.num_parents = num_parents;
  326. pll_clk->hw.init = &init;
  327. pll_clk->pll_devdata = &core_pll_devdata;
  328. ret = clk_hw_register(NULL, &pll_clk->hw);
  329. if (ret) {
  330. pr_err("failed to register %pOFn clock\n", node);
  331. goto err_unmap_spec_regs;
  332. }
  333. ret = of_clk_add_hw_provider(node, of_clk_hw_simple_get, &pll_clk->hw);
  334. if (ret) {
  335. pr_err("failed to add hw provider for %pOFn clock\n", node);
  336. goto err_unmap_spec_regs;
  337. }
  338. return;
  339. err_unmap_spec_regs:
  340. iounmap(pll_clk->spec_regs);
  341. err_unmap_comm_regs:
  342. iounmap(pll_clk->regs);
  343. err_free_pll_clk:
  344. kfree(pll_clk);
  345. }
  346. /* Core PLL needed early for ARC cpus timers */
  347. CLK_OF_DECLARE(hsdk_pll_clock, "snps,hsdk-core-pll-clock",
  348. of_hsdk_pll_clk_setup);
  349. static const struct of_device_id hsdk_pll_clk_id[] = {
  350. { .compatible = "snps,hsdk-gp-pll-clock", .data = &sdt_pll_devdata},
  351. { .compatible = "snps,hsdk-hdmi-pll-clock", .data = &hdmi_pll_devdata},
  352. { }
  353. };
  354. static struct platform_driver hsdk_pll_clk_driver = {
  355. .driver = {
  356. .name = "hsdk-gp-pll-clock",
  357. .of_match_table = hsdk_pll_clk_id,
  358. },
  359. .probe = hsdk_pll_clk_probe,
  360. .remove = hsdk_pll_clk_remove,
  361. };
  362. builtin_platform_driver(hsdk_pll_clk_driver);