clk-ast2600.c 23 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. // Copyright IBM Corp
  3. // Copyright ASPEED Technology
  4. #define pr_fmt(fmt) "clk-ast2600: " fmt
  5. #include <linux/mfd/syscon.h>
  6. #include <linux/of_address.h>
  7. #include <linux/of_device.h>
  8. #include <linux/platform_device.h>
  9. #include <linux/regmap.h>
  10. #include <linux/slab.h>
  11. #include <dt-bindings/clock/ast2600-clock.h>
  12. #include "clk-aspeed.h"
  13. #define ASPEED_G6_NUM_CLKS 71
  14. #define ASPEED_G6_SILICON_REV 0x014
  15. #define CHIP_REVISION_ID GENMASK(23, 16)
  16. #define ASPEED_G6_RESET_CTRL 0x040
  17. #define ASPEED_G6_RESET_CTRL2 0x050
  18. #define ASPEED_G6_CLK_STOP_CTRL 0x080
  19. #define ASPEED_G6_CLK_STOP_CTRL2 0x090
  20. #define ASPEED_G6_MISC_CTRL 0x0C0
  21. #define UART_DIV13_EN BIT(12)
  22. #define ASPEED_G6_CLK_SELECTION1 0x300
  23. #define ASPEED_G6_CLK_SELECTION2 0x304
  24. #define ASPEED_G6_CLK_SELECTION4 0x310
  25. #define ASPEED_HPLL_PARAM 0x200
  26. #define ASPEED_APLL_PARAM 0x210
  27. #define ASPEED_MPLL_PARAM 0x220
  28. #define ASPEED_EPLL_PARAM 0x240
  29. #define ASPEED_DPLL_PARAM 0x260
  30. #define ASPEED_G6_STRAP1 0x500
  31. #define ASPEED_MAC12_CLK_DLY 0x340
  32. #define ASPEED_MAC34_CLK_DLY 0x350
  33. /* Globally visible clocks */
  34. static DEFINE_SPINLOCK(aspeed_g6_clk_lock);
  35. /* Keeps track of all clocks */
  36. static struct clk_hw_onecell_data *aspeed_g6_clk_data;
  37. static void __iomem *scu_g6_base;
  38. /* AST2600 revision: A0, A1, A2, etc */
  39. static u8 soc_rev;
  40. /*
  41. * Clocks marked with CLK_IS_CRITICAL:
  42. *
  43. * ref0 and ref1 are essential for the SoC to operate
  44. * mpll is required if SDRAM is used
  45. */
  46. static const struct aspeed_gate_data aspeed_g6_gates[] = {
  47. /* clk rst name parent flags */
  48. [ASPEED_CLK_GATE_MCLK] = { 0, -1, "mclk-gate", "mpll", CLK_IS_CRITICAL }, /* SDRAM */
  49. [ASPEED_CLK_GATE_ECLK] = { 1, 6, "eclk-gate", "eclk", 0 }, /* Video Engine */
  50. [ASPEED_CLK_GATE_GCLK] = { 2, 7, "gclk-gate", NULL, 0 }, /* 2D engine */
  51. /* vclk parent - dclk/d1clk/hclk/mclk */
  52. [ASPEED_CLK_GATE_VCLK] = { 3, -1, "vclk-gate", NULL, 0 }, /* Video Capture */
  53. [ASPEED_CLK_GATE_BCLK] = { 4, 8, "bclk-gate", "bclk", 0 }, /* PCIe/PCI */
  54. /* From dpll */
  55. [ASPEED_CLK_GATE_DCLK] = { 5, -1, "dclk-gate", NULL, CLK_IS_CRITICAL }, /* DAC */
  56. [ASPEED_CLK_GATE_REF0CLK] = { 6, -1, "ref0clk-gate", "clkin", CLK_IS_CRITICAL },
  57. [ASPEED_CLK_GATE_USBPORT2CLK] = { 7, 3, "usb-port2-gate", NULL, 0 }, /* USB2.0 Host port 2 */
  58. /* Reserved 8 */
  59. [ASPEED_CLK_GATE_USBUHCICLK] = { 9, 15, "usb-uhci-gate", NULL, 0 }, /* USB1.1 (requires port 2 enabled) */
  60. /* From dpll/epll/40mhz usb p1 phy/gpioc6/dp phy pll */
  61. [ASPEED_CLK_GATE_D1CLK] = { 10, 13, "d1clk-gate", "d1clk", 0 }, /* GFX CRT */
  62. /* Reserved 11/12 */
  63. [ASPEED_CLK_GATE_YCLK] = { 13, 4, "yclk-gate", NULL, 0 }, /* HAC */
  64. [ASPEED_CLK_GATE_USBPORT1CLK] = { 14, 14, "usb-port1-gate", NULL, 0 }, /* USB2 hub/USB2 host port 1/USB1.1 dev */
  65. [ASPEED_CLK_GATE_UART5CLK] = { 15, -1, "uart5clk-gate", "uart", 0 }, /* UART5 */
  66. /* Reserved 16/19 */
  67. [ASPEED_CLK_GATE_MAC1CLK] = { 20, 11, "mac1clk-gate", "mac12", 0 }, /* MAC1 */
  68. [ASPEED_CLK_GATE_MAC2CLK] = { 21, 12, "mac2clk-gate", "mac12", 0 }, /* MAC2 */
  69. /* Reserved 22/23 */
  70. [ASPEED_CLK_GATE_RSACLK] = { 24, 4, "rsaclk-gate", NULL, 0 }, /* HAC */
  71. [ASPEED_CLK_GATE_RVASCLK] = { 25, 9, "rvasclk-gate", NULL, 0 }, /* RVAS */
  72. /* Reserved 26 */
  73. [ASPEED_CLK_GATE_EMMCCLK] = { 27, 16, "emmcclk-gate", NULL, 0 }, /* For card clk */
  74. /* Reserved 28/29/30 */
  75. [ASPEED_CLK_GATE_LCLK] = { 32, 32, "lclk-gate", NULL, 0 }, /* LPC */
  76. [ASPEED_CLK_GATE_ESPICLK] = { 33, -1, "espiclk-gate", NULL, 0 }, /* eSPI */
  77. [ASPEED_CLK_GATE_REF1CLK] = { 34, -1, "ref1clk-gate", "clkin", CLK_IS_CRITICAL },
  78. /* Reserved 35 */
  79. [ASPEED_CLK_GATE_SDCLK] = { 36, 56, "sdclk-gate", NULL, 0 }, /* SDIO/SD */
  80. [ASPEED_CLK_GATE_LHCCLK] = { 37, -1, "lhclk-gate", "lhclk", 0 }, /* LPC master/LPC+ */
  81. /* Reserved 38 RSA: no longer used */
  82. /* Reserved 39 */
  83. [ASPEED_CLK_GATE_I3C0CLK] = { 40, 40, "i3c0clk-gate", NULL, 0 }, /* I3C0 */
  84. [ASPEED_CLK_GATE_I3C1CLK] = { 41, 41, "i3c1clk-gate", NULL, 0 }, /* I3C1 */
  85. [ASPEED_CLK_GATE_I3C2CLK] = { 42, 42, "i3c2clk-gate", NULL, 0 }, /* I3C2 */
  86. [ASPEED_CLK_GATE_I3C3CLK] = { 43, 43, "i3c3clk-gate", NULL, 0 }, /* I3C3 */
  87. [ASPEED_CLK_GATE_I3C4CLK] = { 44, 44, "i3c4clk-gate", NULL, 0 }, /* I3C4 */
  88. [ASPEED_CLK_GATE_I3C5CLK] = { 45, 45, "i3c5clk-gate", NULL, 0 }, /* I3C5 */
  89. [ASPEED_CLK_GATE_I3C6CLK] = { 46, 46, "i3c6clk-gate", NULL, 0 }, /* I3C6 */
  90. [ASPEED_CLK_GATE_I3C7CLK] = { 47, 47, "i3c7clk-gate", NULL, 0 }, /* I3C7 */
  91. [ASPEED_CLK_GATE_UART1CLK] = { 48, -1, "uart1clk-gate", "uart", 0 }, /* UART1 */
  92. [ASPEED_CLK_GATE_UART2CLK] = { 49, -1, "uart2clk-gate", "uart", 0 }, /* UART2 */
  93. [ASPEED_CLK_GATE_UART3CLK] = { 50, -1, "uart3clk-gate", "uart", 0 }, /* UART3 */
  94. [ASPEED_CLK_GATE_UART4CLK] = { 51, -1, "uart4clk-gate", "uart", 0 }, /* UART4 */
  95. [ASPEED_CLK_GATE_MAC3CLK] = { 52, 52, "mac3clk-gate", "mac34", 0 }, /* MAC3 */
  96. [ASPEED_CLK_GATE_MAC4CLK] = { 53, 53, "mac4clk-gate", "mac34", 0 }, /* MAC4 */
  97. [ASPEED_CLK_GATE_UART6CLK] = { 54, -1, "uart6clk-gate", "uartx", 0 }, /* UART6 */
  98. [ASPEED_CLK_GATE_UART7CLK] = { 55, -1, "uart7clk-gate", "uartx", 0 }, /* UART7 */
  99. [ASPEED_CLK_GATE_UART8CLK] = { 56, -1, "uart8clk-gate", "uartx", 0 }, /* UART8 */
  100. [ASPEED_CLK_GATE_UART9CLK] = { 57, -1, "uart9clk-gate", "uartx", 0 }, /* UART9 */
  101. [ASPEED_CLK_GATE_UART10CLK] = { 58, -1, "uart10clk-gate", "uartx", 0 }, /* UART10 */
  102. [ASPEED_CLK_GATE_UART11CLK] = { 59, -1, "uart11clk-gate", "uartx", 0 }, /* UART11 */
  103. [ASPEED_CLK_GATE_UART12CLK] = { 60, -1, "uart12clk-gate", "uartx", 0 }, /* UART12 */
  104. [ASPEED_CLK_GATE_UART13CLK] = { 61, -1, "uart13clk-gate", "uartx", 0 }, /* UART13 */
  105. [ASPEED_CLK_GATE_FSICLK] = { 62, 59, "fsiclk-gate", NULL, 0 }, /* FSI */
  106. };
  107. static const struct clk_div_table ast2600_eclk_div_table[] = {
  108. { 0x0, 2 },
  109. { 0x1, 2 },
  110. { 0x2, 3 },
  111. { 0x3, 4 },
  112. { 0x4, 5 },
  113. { 0x5, 6 },
  114. { 0x6, 7 },
  115. { 0x7, 8 },
  116. { 0 }
  117. };
  118. static const struct clk_div_table ast2600_emmc_extclk_div_table[] = {
  119. { 0x0, 2 },
  120. { 0x1, 4 },
  121. { 0x2, 6 },
  122. { 0x3, 8 },
  123. { 0x4, 10 },
  124. { 0x5, 12 },
  125. { 0x6, 14 },
  126. { 0x7, 16 },
  127. { 0 }
  128. };
  129. static const struct clk_div_table ast2600_mac_div_table[] = {
  130. { 0x0, 4 },
  131. { 0x1, 4 },
  132. { 0x2, 6 },
  133. { 0x3, 8 },
  134. { 0x4, 10 },
  135. { 0x5, 12 },
  136. { 0x6, 14 },
  137. { 0x7, 16 },
  138. { 0 }
  139. };
  140. static const struct clk_div_table ast2600_div_table[] = {
  141. { 0x0, 4 },
  142. { 0x1, 8 },
  143. { 0x2, 12 },
  144. { 0x3, 16 },
  145. { 0x4, 20 },
  146. { 0x5, 24 },
  147. { 0x6, 28 },
  148. { 0x7, 32 },
  149. { 0 }
  150. };
  151. /* For hpll/dpll/epll/mpll */
  152. static struct clk_hw *ast2600_calc_pll(const char *name, u32 val)
  153. {
  154. unsigned int mult, div;
  155. if (val & BIT(24)) {
  156. /* Pass through mode */
  157. mult = div = 1;
  158. } else {
  159. /* F = 25Mhz * [(M + 2) / (n + 1)] / (p + 1) */
  160. u32 m = val & 0x1fff;
  161. u32 n = (val >> 13) & 0x3f;
  162. u32 p = (val >> 19) & 0xf;
  163. mult = (m + 1) / (n + 1);
  164. div = (p + 1);
  165. }
  166. return clk_hw_register_fixed_factor(NULL, name, "clkin", 0,
  167. mult, div);
  168. };
  169. static struct clk_hw *ast2600_calc_apll(const char *name, u32 val)
  170. {
  171. unsigned int mult, div;
  172. if (soc_rev >= 2) {
  173. if (val & BIT(24)) {
  174. /* Pass through mode */
  175. mult = div = 1;
  176. } else {
  177. /* F = 25Mhz * [(m + 1) / (n + 1)] / (p + 1) */
  178. u32 m = val & 0x1fff;
  179. u32 n = (val >> 13) & 0x3f;
  180. u32 p = (val >> 19) & 0xf;
  181. mult = (m + 1);
  182. div = (n + 1) * (p + 1);
  183. }
  184. } else {
  185. if (val & BIT(20)) {
  186. /* Pass through mode */
  187. mult = div = 1;
  188. } else {
  189. /* F = 25Mhz * (2-od) * [(m + 2) / (n + 1)] */
  190. u32 m = (val >> 5) & 0x3f;
  191. u32 od = (val >> 4) & 0x1;
  192. u32 n = val & 0xf;
  193. mult = (2 - od) * (m + 2);
  194. div = n + 1;
  195. }
  196. }
  197. return clk_hw_register_fixed_factor(NULL, name, "clkin", 0,
  198. mult, div);
  199. };
  200. static u32 get_bit(u8 idx)
  201. {
  202. return BIT(idx % 32);
  203. }
  204. static u32 get_reset_reg(struct aspeed_clk_gate *gate)
  205. {
  206. if (gate->reset_idx < 32)
  207. return ASPEED_G6_RESET_CTRL;
  208. return ASPEED_G6_RESET_CTRL2;
  209. }
  210. static u32 get_clock_reg(struct aspeed_clk_gate *gate)
  211. {
  212. if (gate->clock_idx < 32)
  213. return ASPEED_G6_CLK_STOP_CTRL;
  214. return ASPEED_G6_CLK_STOP_CTRL2;
  215. }
  216. static int aspeed_g6_clk_is_enabled(struct clk_hw *hw)
  217. {
  218. struct aspeed_clk_gate *gate = to_aspeed_clk_gate(hw);
  219. u32 clk = get_bit(gate->clock_idx);
  220. u32 rst = get_bit(gate->reset_idx);
  221. u32 reg;
  222. u32 enval;
  223. /*
  224. * If the IP is in reset, treat the clock as not enabled,
  225. * this happens with some clocks such as the USB one when
  226. * coming from cold reset. Without this, aspeed_clk_enable()
  227. * will fail to lift the reset.
  228. */
  229. if (gate->reset_idx >= 0) {
  230. regmap_read(gate->map, get_reset_reg(gate), &reg);
  231. if (reg & rst)
  232. return 0;
  233. }
  234. regmap_read(gate->map, get_clock_reg(gate), &reg);
  235. enval = (gate->flags & CLK_GATE_SET_TO_DISABLE) ? 0 : clk;
  236. return ((reg & clk) == enval) ? 1 : 0;
  237. }
  238. static int aspeed_g6_clk_enable(struct clk_hw *hw)
  239. {
  240. struct aspeed_clk_gate *gate = to_aspeed_clk_gate(hw);
  241. unsigned long flags;
  242. u32 clk = get_bit(gate->clock_idx);
  243. u32 rst = get_bit(gate->reset_idx);
  244. spin_lock_irqsave(gate->lock, flags);
  245. if (aspeed_g6_clk_is_enabled(hw)) {
  246. spin_unlock_irqrestore(gate->lock, flags);
  247. return 0;
  248. }
  249. if (gate->reset_idx >= 0) {
  250. /* Put IP in reset */
  251. regmap_write(gate->map, get_reset_reg(gate), rst);
  252. /* Delay 100us */
  253. udelay(100);
  254. }
  255. /* Enable clock */
  256. if (gate->flags & CLK_GATE_SET_TO_DISABLE) {
  257. /* Clock is clear to enable, so use set to clear register */
  258. regmap_write(gate->map, get_clock_reg(gate) + 0x04, clk);
  259. } else {
  260. /* Clock is set to enable, so use write to set register */
  261. regmap_write(gate->map, get_clock_reg(gate), clk);
  262. }
  263. if (gate->reset_idx >= 0) {
  264. /* A delay of 10ms is specified by the ASPEED docs */
  265. mdelay(10);
  266. /* Take IP out of reset */
  267. regmap_write(gate->map, get_reset_reg(gate) + 0x4, rst);
  268. }
  269. spin_unlock_irqrestore(gate->lock, flags);
  270. return 0;
  271. }
  272. static void aspeed_g6_clk_disable(struct clk_hw *hw)
  273. {
  274. struct aspeed_clk_gate *gate = to_aspeed_clk_gate(hw);
  275. unsigned long flags;
  276. u32 clk = get_bit(gate->clock_idx);
  277. spin_lock_irqsave(gate->lock, flags);
  278. if (gate->flags & CLK_GATE_SET_TO_DISABLE) {
  279. regmap_write(gate->map, get_clock_reg(gate), clk);
  280. } else {
  281. /* Use set to clear register */
  282. regmap_write(gate->map, get_clock_reg(gate) + 0x4, clk);
  283. }
  284. spin_unlock_irqrestore(gate->lock, flags);
  285. }
  286. static const struct clk_ops aspeed_g6_clk_gate_ops = {
  287. .enable = aspeed_g6_clk_enable,
  288. .disable = aspeed_g6_clk_disable,
  289. .is_enabled = aspeed_g6_clk_is_enabled,
  290. };
  291. static int aspeed_g6_reset_deassert(struct reset_controller_dev *rcdev,
  292. unsigned long id)
  293. {
  294. struct aspeed_reset *ar = to_aspeed_reset(rcdev);
  295. u32 rst = get_bit(id);
  296. u32 reg = id >= 32 ? ASPEED_G6_RESET_CTRL2 : ASPEED_G6_RESET_CTRL;
  297. /* Use set to clear register */
  298. return regmap_write(ar->map, reg + 0x04, rst);
  299. }
  300. static int aspeed_g6_reset_assert(struct reset_controller_dev *rcdev,
  301. unsigned long id)
  302. {
  303. struct aspeed_reset *ar = to_aspeed_reset(rcdev);
  304. u32 rst = get_bit(id);
  305. u32 reg = id >= 32 ? ASPEED_G6_RESET_CTRL2 : ASPEED_G6_RESET_CTRL;
  306. return regmap_write(ar->map, reg, rst);
  307. }
  308. static int aspeed_g6_reset_status(struct reset_controller_dev *rcdev,
  309. unsigned long id)
  310. {
  311. struct aspeed_reset *ar = to_aspeed_reset(rcdev);
  312. int ret;
  313. u32 val;
  314. u32 rst = get_bit(id);
  315. u32 reg = id >= 32 ? ASPEED_G6_RESET_CTRL2 : ASPEED_G6_RESET_CTRL;
  316. ret = regmap_read(ar->map, reg, &val);
  317. if (ret)
  318. return ret;
  319. return !!(val & rst);
  320. }
  321. static const struct reset_control_ops aspeed_g6_reset_ops = {
  322. .assert = aspeed_g6_reset_assert,
  323. .deassert = aspeed_g6_reset_deassert,
  324. .status = aspeed_g6_reset_status,
  325. };
  326. static struct clk_hw *aspeed_g6_clk_hw_register_gate(struct device *dev,
  327. const char *name, const char *parent_name, unsigned long flags,
  328. struct regmap *map, u8 clock_idx, u8 reset_idx,
  329. u8 clk_gate_flags, spinlock_t *lock)
  330. {
  331. struct aspeed_clk_gate *gate;
  332. struct clk_init_data init;
  333. struct clk_hw *hw;
  334. int ret;
  335. gate = kzalloc(sizeof(*gate), GFP_KERNEL);
  336. if (!gate)
  337. return ERR_PTR(-ENOMEM);
  338. init.name = name;
  339. init.ops = &aspeed_g6_clk_gate_ops;
  340. init.flags = flags;
  341. init.parent_names = parent_name ? &parent_name : NULL;
  342. init.num_parents = parent_name ? 1 : 0;
  343. gate->map = map;
  344. gate->clock_idx = clock_idx;
  345. gate->reset_idx = reset_idx;
  346. gate->flags = clk_gate_flags;
  347. gate->lock = lock;
  348. gate->hw.init = &init;
  349. hw = &gate->hw;
  350. ret = clk_hw_register(dev, hw);
  351. if (ret) {
  352. kfree(gate);
  353. hw = ERR_PTR(ret);
  354. }
  355. return hw;
  356. }
  357. static const char *const emmc_extclk_parent_names[] = {
  358. "emmc_extclk_hpll_in",
  359. "mpll",
  360. };
  361. static const char * const vclk_parent_names[] = {
  362. "dpll",
  363. "d1pll",
  364. "hclk",
  365. "mclk",
  366. };
  367. static const char * const d1clk_parent_names[] = {
  368. "dpll",
  369. "epll",
  370. "usb-phy-40m",
  371. "gpioc6_clkin",
  372. "dp_phy_pll",
  373. };
  374. static int aspeed_g6_clk_probe(struct platform_device *pdev)
  375. {
  376. struct device *dev = &pdev->dev;
  377. struct aspeed_reset *ar;
  378. struct regmap *map;
  379. struct clk_hw *hw;
  380. u32 val, rate;
  381. int i, ret;
  382. map = syscon_node_to_regmap(dev->of_node);
  383. if (IS_ERR(map)) {
  384. dev_err(dev, "no syscon regmap\n");
  385. return PTR_ERR(map);
  386. }
  387. ar = devm_kzalloc(dev, sizeof(*ar), GFP_KERNEL);
  388. if (!ar)
  389. return -ENOMEM;
  390. ar->map = map;
  391. ar->rcdev.owner = THIS_MODULE;
  392. ar->rcdev.nr_resets = 64;
  393. ar->rcdev.ops = &aspeed_g6_reset_ops;
  394. ar->rcdev.of_node = dev->of_node;
  395. ret = devm_reset_controller_register(dev, &ar->rcdev);
  396. if (ret) {
  397. dev_err(dev, "could not register reset controller\n");
  398. return ret;
  399. }
  400. /* UART clock div13 setting */
  401. regmap_read(map, ASPEED_G6_MISC_CTRL, &val);
  402. if (val & UART_DIV13_EN)
  403. rate = 24000000 / 13;
  404. else
  405. rate = 24000000;
  406. hw = clk_hw_register_fixed_rate(dev, "uart", NULL, 0, rate);
  407. if (IS_ERR(hw))
  408. return PTR_ERR(hw);
  409. aspeed_g6_clk_data->hws[ASPEED_CLK_UART] = hw;
  410. /* UART6~13 clock div13 setting */
  411. regmap_read(map, 0x80, &val);
  412. if (val & BIT(31))
  413. rate = 24000000 / 13;
  414. else
  415. rate = 24000000;
  416. hw = clk_hw_register_fixed_rate(dev, "uartx", NULL, 0, rate);
  417. if (IS_ERR(hw))
  418. return PTR_ERR(hw);
  419. aspeed_g6_clk_data->hws[ASPEED_CLK_UARTX] = hw;
  420. /* EMMC ext clock */
  421. hw = clk_hw_register_fixed_factor(dev, "emmc_extclk_hpll_in", "hpll",
  422. 0, 1, 2);
  423. if (IS_ERR(hw))
  424. return PTR_ERR(hw);
  425. hw = clk_hw_register_mux(dev, "emmc_extclk_mux",
  426. emmc_extclk_parent_names,
  427. ARRAY_SIZE(emmc_extclk_parent_names), 0,
  428. scu_g6_base + ASPEED_G6_CLK_SELECTION1, 11, 1,
  429. 0, &aspeed_g6_clk_lock);
  430. if (IS_ERR(hw))
  431. return PTR_ERR(hw);
  432. hw = clk_hw_register_gate(dev, "emmc_extclk_gate", "emmc_extclk_mux",
  433. 0, scu_g6_base + ASPEED_G6_CLK_SELECTION1,
  434. 15, 0, &aspeed_g6_clk_lock);
  435. if (IS_ERR(hw))
  436. return PTR_ERR(hw);
  437. hw = clk_hw_register_divider_table(dev, "emmc_extclk",
  438. "emmc_extclk_gate", 0,
  439. scu_g6_base +
  440. ASPEED_G6_CLK_SELECTION1, 12,
  441. 3, 0, ast2600_emmc_extclk_div_table,
  442. &aspeed_g6_clk_lock);
  443. if (IS_ERR(hw))
  444. return PTR_ERR(hw);
  445. aspeed_g6_clk_data->hws[ASPEED_CLK_EMMC] = hw;
  446. /* SD/SDIO clock divider and gate */
  447. hw = clk_hw_register_gate(dev, "sd_extclk_gate", "hpll", 0,
  448. scu_g6_base + ASPEED_G6_CLK_SELECTION4, 31, 0,
  449. &aspeed_g6_clk_lock);
  450. if (IS_ERR(hw))
  451. return PTR_ERR(hw);
  452. hw = clk_hw_register_divider_table(dev, "sd_extclk", "sd_extclk_gate",
  453. 0, scu_g6_base + ASPEED_G6_CLK_SELECTION4, 28, 3, 0,
  454. ast2600_div_table,
  455. &aspeed_g6_clk_lock);
  456. if (IS_ERR(hw))
  457. return PTR_ERR(hw);
  458. aspeed_g6_clk_data->hws[ASPEED_CLK_SDIO] = hw;
  459. /* MAC1/2 RMII 50MHz RCLK */
  460. hw = clk_hw_register_fixed_rate(dev, "mac12rclk", "hpll", 0, 50000000);
  461. if (IS_ERR(hw))
  462. return PTR_ERR(hw);
  463. /* MAC1/2 AHB bus clock divider */
  464. hw = clk_hw_register_divider_table(dev, "mac12", "hpll", 0,
  465. scu_g6_base + ASPEED_G6_CLK_SELECTION1, 16, 3, 0,
  466. ast2600_mac_div_table,
  467. &aspeed_g6_clk_lock);
  468. if (IS_ERR(hw))
  469. return PTR_ERR(hw);
  470. aspeed_g6_clk_data->hws[ASPEED_CLK_MAC12] = hw;
  471. /* RMII1 50MHz (RCLK) output enable */
  472. hw = clk_hw_register_gate(dev, "mac1rclk", "mac12rclk", 0,
  473. scu_g6_base + ASPEED_MAC12_CLK_DLY, 29, 0,
  474. &aspeed_g6_clk_lock);
  475. if (IS_ERR(hw))
  476. return PTR_ERR(hw);
  477. aspeed_g6_clk_data->hws[ASPEED_CLK_MAC1RCLK] = hw;
  478. /* RMII2 50MHz (RCLK) output enable */
  479. hw = clk_hw_register_gate(dev, "mac2rclk", "mac12rclk", 0,
  480. scu_g6_base + ASPEED_MAC12_CLK_DLY, 30, 0,
  481. &aspeed_g6_clk_lock);
  482. if (IS_ERR(hw))
  483. return PTR_ERR(hw);
  484. aspeed_g6_clk_data->hws[ASPEED_CLK_MAC2RCLK] = hw;
  485. /* MAC1/2 RMII 50MHz RCLK */
  486. hw = clk_hw_register_fixed_rate(dev, "mac34rclk", "hclk", 0, 50000000);
  487. if (IS_ERR(hw))
  488. return PTR_ERR(hw);
  489. /* MAC3/4 AHB bus clock divider */
  490. hw = clk_hw_register_divider_table(dev, "mac34", "hpll", 0,
  491. scu_g6_base + 0x310, 24, 3, 0,
  492. ast2600_mac_div_table,
  493. &aspeed_g6_clk_lock);
  494. if (IS_ERR(hw))
  495. return PTR_ERR(hw);
  496. aspeed_g6_clk_data->hws[ASPEED_CLK_MAC34] = hw;
  497. /* RMII3 50MHz (RCLK) output enable */
  498. hw = clk_hw_register_gate(dev, "mac3rclk", "mac34rclk", 0,
  499. scu_g6_base + ASPEED_MAC34_CLK_DLY, 29, 0,
  500. &aspeed_g6_clk_lock);
  501. if (IS_ERR(hw))
  502. return PTR_ERR(hw);
  503. aspeed_g6_clk_data->hws[ASPEED_CLK_MAC3RCLK] = hw;
  504. /* RMII4 50MHz (RCLK) output enable */
  505. hw = clk_hw_register_gate(dev, "mac4rclk", "mac34rclk", 0,
  506. scu_g6_base + ASPEED_MAC34_CLK_DLY, 30, 0,
  507. &aspeed_g6_clk_lock);
  508. if (IS_ERR(hw))
  509. return PTR_ERR(hw);
  510. aspeed_g6_clk_data->hws[ASPEED_CLK_MAC4RCLK] = hw;
  511. /* LPC Host (LHCLK) clock divider */
  512. hw = clk_hw_register_divider_table(dev, "lhclk", "hpll", 0,
  513. scu_g6_base + ASPEED_G6_CLK_SELECTION1, 20, 3, 0,
  514. ast2600_div_table,
  515. &aspeed_g6_clk_lock);
  516. if (IS_ERR(hw))
  517. return PTR_ERR(hw);
  518. aspeed_g6_clk_data->hws[ASPEED_CLK_LHCLK] = hw;
  519. /* gfx d1clk : use dp clk */
  520. regmap_update_bits(map, ASPEED_G6_CLK_SELECTION1, GENMASK(10, 8), BIT(10));
  521. /* SoC Display clock selection */
  522. hw = clk_hw_register_mux(dev, "d1clk", d1clk_parent_names,
  523. ARRAY_SIZE(d1clk_parent_names), 0,
  524. scu_g6_base + ASPEED_G6_CLK_SELECTION1, 8, 3, 0,
  525. &aspeed_g6_clk_lock);
  526. if (IS_ERR(hw))
  527. return PTR_ERR(hw);
  528. aspeed_g6_clk_data->hws[ASPEED_CLK_D1CLK] = hw;
  529. /* d1 clk div 0x308[17:15] x [14:12] - 8,7,6,5,4,3,2,1 */
  530. regmap_write(map, 0x308, 0x12000); /* 3x3 = 9 */
  531. /* P-Bus (BCLK) clock divider */
  532. hw = clk_hw_register_divider_table(dev, "bclk", "hpll", 0,
  533. scu_g6_base + ASPEED_G6_CLK_SELECTION1, 20, 3, 0,
  534. ast2600_div_table,
  535. &aspeed_g6_clk_lock);
  536. if (IS_ERR(hw))
  537. return PTR_ERR(hw);
  538. aspeed_g6_clk_data->hws[ASPEED_CLK_BCLK] = hw;
  539. /* Video Capture clock selection */
  540. hw = clk_hw_register_mux(dev, "vclk", vclk_parent_names,
  541. ARRAY_SIZE(vclk_parent_names), 0,
  542. scu_g6_base + ASPEED_G6_CLK_SELECTION2, 12, 3, 0,
  543. &aspeed_g6_clk_lock);
  544. if (IS_ERR(hw))
  545. return PTR_ERR(hw);
  546. aspeed_g6_clk_data->hws[ASPEED_CLK_VCLK] = hw;
  547. /* Video Engine clock divider */
  548. hw = clk_hw_register_divider_table(dev, "eclk", NULL, 0,
  549. scu_g6_base + ASPEED_G6_CLK_SELECTION1, 28, 3, 0,
  550. ast2600_eclk_div_table,
  551. &aspeed_g6_clk_lock);
  552. if (IS_ERR(hw))
  553. return PTR_ERR(hw);
  554. aspeed_g6_clk_data->hws[ASPEED_CLK_ECLK] = hw;
  555. for (i = 0; i < ARRAY_SIZE(aspeed_g6_gates); i++) {
  556. const struct aspeed_gate_data *gd = &aspeed_g6_gates[i];
  557. u32 gate_flags;
  558. /*
  559. * Special case: the USB port 1 clock (bit 14) is always
  560. * working the opposite way from the other ones.
  561. */
  562. gate_flags = (gd->clock_idx == 14) ? 0 : CLK_GATE_SET_TO_DISABLE;
  563. hw = aspeed_g6_clk_hw_register_gate(dev,
  564. gd->name,
  565. gd->parent_name,
  566. gd->flags,
  567. map,
  568. gd->clock_idx,
  569. gd->reset_idx,
  570. gate_flags,
  571. &aspeed_g6_clk_lock);
  572. if (IS_ERR(hw))
  573. return PTR_ERR(hw);
  574. aspeed_g6_clk_data->hws[i] = hw;
  575. }
  576. return 0;
  577. };
  578. static const struct of_device_id aspeed_g6_clk_dt_ids[] = {
  579. { .compatible = "aspeed,ast2600-scu" },
  580. { }
  581. };
  582. static struct platform_driver aspeed_g6_clk_driver = {
  583. .probe = aspeed_g6_clk_probe,
  584. .driver = {
  585. .name = "ast2600-clk",
  586. .of_match_table = aspeed_g6_clk_dt_ids,
  587. .suppress_bind_attrs = true,
  588. },
  589. };
  590. builtin_platform_driver(aspeed_g6_clk_driver);
  591. static const u32 ast2600_a0_axi_ahb_div_table[] = {
  592. 2, 2, 3, 5,
  593. };
  594. static const u32 ast2600_a1_axi_ahb_div0_tbl[] = {
  595. 3, 2, 3, 4,
  596. };
  597. static const u32 ast2600_a1_axi_ahb_div1_tbl[] = {
  598. 3, 4, 6, 8,
  599. };
  600. static const u32 ast2600_a1_axi_ahb200_tbl[] = {
  601. 3, 4, 3, 4, 2, 2, 2, 2,
  602. };
  603. static void __init aspeed_g6_cc(struct regmap *map)
  604. {
  605. struct clk_hw *hw;
  606. u32 val, div, divbits, axi_div, ahb_div;
  607. clk_hw_register_fixed_rate(NULL, "clkin", NULL, 0, 25000000);
  608. /*
  609. * High-speed PLL clock derived from the crystal. This the CPU clock,
  610. * and we assume that it is enabled
  611. */
  612. regmap_read(map, ASPEED_HPLL_PARAM, &val);
  613. aspeed_g6_clk_data->hws[ASPEED_CLK_HPLL] = ast2600_calc_pll("hpll", val);
  614. regmap_read(map, ASPEED_MPLL_PARAM, &val);
  615. aspeed_g6_clk_data->hws[ASPEED_CLK_MPLL] = ast2600_calc_pll("mpll", val);
  616. regmap_read(map, ASPEED_DPLL_PARAM, &val);
  617. aspeed_g6_clk_data->hws[ASPEED_CLK_DPLL] = ast2600_calc_pll("dpll", val);
  618. regmap_read(map, ASPEED_EPLL_PARAM, &val);
  619. aspeed_g6_clk_data->hws[ASPEED_CLK_EPLL] = ast2600_calc_pll("epll", val);
  620. regmap_read(map, ASPEED_APLL_PARAM, &val);
  621. aspeed_g6_clk_data->hws[ASPEED_CLK_APLL] = ast2600_calc_apll("apll", val);
  622. /* Strap bits 12:11 define the AXI/AHB clock frequency ratio (aka HCLK)*/
  623. regmap_read(map, ASPEED_G6_STRAP1, &val);
  624. if (val & BIT(16))
  625. axi_div = 1;
  626. else
  627. axi_div = 2;
  628. divbits = (val >> 11) & 0x3;
  629. if (soc_rev >= 1) {
  630. if (!divbits) {
  631. ahb_div = ast2600_a1_axi_ahb200_tbl[(val >> 8) & 0x3];
  632. if (val & BIT(16))
  633. ahb_div *= 2;
  634. } else {
  635. if (val & BIT(16))
  636. ahb_div = ast2600_a1_axi_ahb_div1_tbl[divbits];
  637. else
  638. ahb_div = ast2600_a1_axi_ahb_div0_tbl[divbits];
  639. }
  640. } else {
  641. ahb_div = ast2600_a0_axi_ahb_div_table[(val >> 11) & 0x3];
  642. }
  643. hw = clk_hw_register_fixed_factor(NULL, "ahb", "hpll", 0, 1, axi_div * ahb_div);
  644. aspeed_g6_clk_data->hws[ASPEED_CLK_AHB] = hw;
  645. regmap_read(map, ASPEED_G6_CLK_SELECTION1, &val);
  646. val = (val >> 23) & 0x7;
  647. div = 4 * (val + 1);
  648. hw = clk_hw_register_fixed_factor(NULL, "apb1", "hpll", 0, 1, div);
  649. aspeed_g6_clk_data->hws[ASPEED_CLK_APB1] = hw;
  650. regmap_read(map, ASPEED_G6_CLK_SELECTION4, &val);
  651. val = (val >> 9) & 0x7;
  652. div = 2 * (val + 1);
  653. hw = clk_hw_register_fixed_factor(NULL, "apb2", "ahb", 0, 1, div);
  654. aspeed_g6_clk_data->hws[ASPEED_CLK_APB2] = hw;
  655. /* USB 2.0 port1 phy 40MHz clock */
  656. hw = clk_hw_register_fixed_rate(NULL, "usb-phy-40m", NULL, 0, 40000000);
  657. aspeed_g6_clk_data->hws[ASPEED_CLK_USBPHY_40M] = hw;
  658. };
  659. static void __init aspeed_g6_cc_init(struct device_node *np)
  660. {
  661. struct regmap *map;
  662. int ret;
  663. int i;
  664. scu_g6_base = of_iomap(np, 0);
  665. if (!scu_g6_base)
  666. return;
  667. soc_rev = (readl(scu_g6_base + ASPEED_G6_SILICON_REV) & CHIP_REVISION_ID) >> 16;
  668. aspeed_g6_clk_data = kzalloc(struct_size(aspeed_g6_clk_data, hws,
  669. ASPEED_G6_NUM_CLKS), GFP_KERNEL);
  670. if (!aspeed_g6_clk_data)
  671. return;
  672. /*
  673. * This way all clocks fetched before the platform device probes,
  674. * except those we assign here for early use, will be deferred.
  675. */
  676. for (i = 0; i < ASPEED_G6_NUM_CLKS; i++)
  677. aspeed_g6_clk_data->hws[i] = ERR_PTR(-EPROBE_DEFER);
  678. /*
  679. * We check that the regmap works on this very first access,
  680. * but as this is an MMIO-backed regmap, subsequent regmap
  681. * access is not going to fail and we skip error checks from
  682. * this point.
  683. */
  684. map = syscon_node_to_regmap(np);
  685. if (IS_ERR(map)) {
  686. pr_err("no syscon regmap\n");
  687. return;
  688. }
  689. aspeed_g6_cc(map);
  690. aspeed_g6_clk_data->num = ASPEED_G6_NUM_CLKS;
  691. ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, aspeed_g6_clk_data);
  692. if (ret)
  693. pr_err("failed to add DT provider: %d\n", ret);
  694. };
  695. CLK_OF_DECLARE_DRIVER(aspeed_cc_g6, "aspeed,ast2600-scu", aspeed_g6_cc_init);