clk-artpec6.c 6.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * ARTPEC-6 clock initialization
  4. *
  5. * Copyright 2015-2016 Axis Comunications AB.
  6. */
  7. #include <linux/clk-provider.h>
  8. #include <linux/device.h>
  9. #include <linux/io.h>
  10. #include <linux/of.h>
  11. #include <linux/of_address.h>
  12. #include <linux/platform_device.h>
  13. #include <linux/slab.h>
  14. #include <dt-bindings/clock/axis,artpec6-clkctrl.h>
  15. #define NUM_I2S_CLOCKS 2
  16. struct artpec6_clkctrl_drvdata {
  17. struct clk *clk_table[ARTPEC6_CLK_NUMCLOCKS];
  18. void __iomem *syscon_base;
  19. struct clk_onecell_data clk_data;
  20. spinlock_t i2scfg_lock;
  21. };
  22. static struct artpec6_clkctrl_drvdata *clkdata;
  23. static const char *const i2s_clk_names[NUM_I2S_CLOCKS] = {
  24. "i2s0",
  25. "i2s1",
  26. };
  27. static const int i2s_clk_indexes[NUM_I2S_CLOCKS] = {
  28. ARTPEC6_CLK_I2S0_CLK,
  29. ARTPEC6_CLK_I2S1_CLK,
  30. };
  31. static void of_artpec6_clkctrl_setup(struct device_node *np)
  32. {
  33. int i;
  34. const char *sys_refclk_name;
  35. u32 pll_mode, pll_m, pll_n;
  36. struct clk **clks;
  37. /* Mandatory parent clock. */
  38. i = of_property_match_string(np, "clock-names", "sys_refclk");
  39. if (i < 0)
  40. return;
  41. sys_refclk_name = of_clk_get_parent_name(np, i);
  42. clkdata = kzalloc(sizeof(*clkdata), GFP_KERNEL);
  43. if (!clkdata)
  44. return;
  45. clks = clkdata->clk_table;
  46. for (i = 0; i < ARTPEC6_CLK_NUMCLOCKS; ++i)
  47. clks[i] = ERR_PTR(-EPROBE_DEFER);
  48. clkdata->syscon_base = of_iomap(np, 0);
  49. BUG_ON(clkdata->syscon_base == NULL);
  50. /* Read PLL1 factors configured by boot strap pins. */
  51. pll_mode = (readl(clkdata->syscon_base) >> 6) & 3;
  52. switch (pll_mode) {
  53. case 0: /* DDR3-2133 mode */
  54. pll_m = 4;
  55. pll_n = 85;
  56. break;
  57. case 1: /* DDR3-1866 mode */
  58. pll_m = 6;
  59. pll_n = 112;
  60. break;
  61. case 2: /* DDR3-1600 mode */
  62. pll_m = 4;
  63. pll_n = 64;
  64. break;
  65. case 3: /* DDR3-1333 mode */
  66. pll_m = 8;
  67. pll_n = 106;
  68. break;
  69. }
  70. clks[ARTPEC6_CLK_CPU] =
  71. clk_register_fixed_factor(NULL, "cpu", sys_refclk_name, 0, pll_n,
  72. pll_m);
  73. clks[ARTPEC6_CLK_CPU_PERIPH] =
  74. clk_register_fixed_factor(NULL, "cpu_periph", "cpu", 0, 1, 2);
  75. /* EPROBE_DEFER on the apb_clock is not handled in amba devices. */
  76. clks[ARTPEC6_CLK_UART_PCLK] =
  77. clk_register_fixed_factor(NULL, "uart_pclk", "cpu", 0, 1, 8);
  78. clks[ARTPEC6_CLK_UART_REFCLK] =
  79. clk_register_fixed_rate(NULL, "uart_ref", sys_refclk_name, 0,
  80. 50000000);
  81. clks[ARTPEC6_CLK_SPI_PCLK] =
  82. clk_register_fixed_factor(NULL, "spi_pclk", "cpu", 0, 1, 8);
  83. clks[ARTPEC6_CLK_SPI_SSPCLK] =
  84. clk_register_fixed_rate(NULL, "spi_sspclk", sys_refclk_name, 0,
  85. 50000000);
  86. clks[ARTPEC6_CLK_DBG_PCLK] =
  87. clk_register_fixed_factor(NULL, "dbg_pclk", "cpu", 0, 1, 8);
  88. clkdata->clk_data.clks = clkdata->clk_table;
  89. clkdata->clk_data.clk_num = ARTPEC6_CLK_NUMCLOCKS;
  90. of_clk_add_provider(np, of_clk_src_onecell_get, &clkdata->clk_data);
  91. }
  92. CLK_OF_DECLARE_DRIVER(artpec6_clkctrl, "axis,artpec6-clkctrl",
  93. of_artpec6_clkctrl_setup);
  94. static int artpec6_clkctrl_probe(struct platform_device *pdev)
  95. {
  96. int propidx;
  97. struct device_node *np = pdev->dev.of_node;
  98. struct device *dev = &pdev->dev;
  99. struct clk **clks = clkdata->clk_table;
  100. const char *sys_refclk_name;
  101. const char *i2s_refclk_name = NULL;
  102. const char *frac_clk_name[2] = { NULL, NULL };
  103. const char *i2s_mux_parents[2];
  104. u32 muxreg;
  105. int i;
  106. int err = 0;
  107. /* Mandatory parent clock. */
  108. propidx = of_property_match_string(np, "clock-names", "sys_refclk");
  109. if (propidx < 0)
  110. return -EINVAL;
  111. sys_refclk_name = of_clk_get_parent_name(np, propidx);
  112. /* Find clock names of optional parent clocks. */
  113. propidx = of_property_match_string(np, "clock-names", "i2s_refclk");
  114. if (propidx >= 0)
  115. i2s_refclk_name = of_clk_get_parent_name(np, propidx);
  116. propidx = of_property_match_string(np, "clock-names", "frac_clk0");
  117. if (propidx >= 0)
  118. frac_clk_name[0] = of_clk_get_parent_name(np, propidx);
  119. propidx = of_property_match_string(np, "clock-names", "frac_clk1");
  120. if (propidx >= 0)
  121. frac_clk_name[1] = of_clk_get_parent_name(np, propidx);
  122. spin_lock_init(&clkdata->i2scfg_lock);
  123. clks[ARTPEC6_CLK_NAND_CLKA] =
  124. clk_register_fixed_factor(dev, "nand_clka", "cpu", 0, 1, 8);
  125. clks[ARTPEC6_CLK_NAND_CLKB] =
  126. clk_register_fixed_rate(dev, "nand_clkb", sys_refclk_name, 0,
  127. 100000000);
  128. clks[ARTPEC6_CLK_ETH_ACLK] =
  129. clk_register_fixed_factor(dev, "eth_aclk", "cpu", 0, 1, 4);
  130. clks[ARTPEC6_CLK_DMA_ACLK] =
  131. clk_register_fixed_factor(dev, "dma_aclk", "cpu", 0, 1, 4);
  132. clks[ARTPEC6_CLK_PTP_REF] =
  133. clk_register_fixed_rate(dev, "ptp_ref", sys_refclk_name, 0,
  134. 100000000);
  135. clks[ARTPEC6_CLK_SD_PCLK] =
  136. clk_register_fixed_rate(dev, "sd_pclk", sys_refclk_name, 0,
  137. 100000000);
  138. clks[ARTPEC6_CLK_SD_IMCLK] =
  139. clk_register_fixed_rate(dev, "sd_imclk", sys_refclk_name, 0,
  140. 100000000);
  141. clks[ARTPEC6_CLK_I2S_HST] =
  142. clk_register_fixed_factor(dev, "i2s_hst", "cpu", 0, 1, 8);
  143. for (i = 0; i < NUM_I2S_CLOCKS; ++i) {
  144. if (i2s_refclk_name && frac_clk_name[i]) {
  145. i2s_mux_parents[0] = frac_clk_name[i];
  146. i2s_mux_parents[1] = i2s_refclk_name;
  147. clks[i2s_clk_indexes[i]] =
  148. clk_register_mux(dev, i2s_clk_names[i],
  149. i2s_mux_parents, 2,
  150. CLK_SET_RATE_NO_REPARENT |
  151. CLK_SET_RATE_PARENT,
  152. clkdata->syscon_base + 0x14, i, 1,
  153. 0, &clkdata->i2scfg_lock);
  154. } else if (frac_clk_name[i]) {
  155. /* Lock the mux for internal clock reference. */
  156. muxreg = readl(clkdata->syscon_base + 0x14);
  157. muxreg &= ~BIT(i);
  158. writel(muxreg, clkdata->syscon_base + 0x14);
  159. clks[i2s_clk_indexes[i]] =
  160. clk_register_fixed_factor(dev, i2s_clk_names[i],
  161. frac_clk_name[i], 0, 1,
  162. 1);
  163. } else if (i2s_refclk_name) {
  164. /* Lock the mux for external clock reference. */
  165. muxreg = readl(clkdata->syscon_base + 0x14);
  166. muxreg |= BIT(i);
  167. writel(muxreg, clkdata->syscon_base + 0x14);
  168. clks[i2s_clk_indexes[i]] =
  169. clk_register_fixed_factor(dev, i2s_clk_names[i],
  170. i2s_refclk_name, 0, 1, 1);
  171. }
  172. }
  173. clks[ARTPEC6_CLK_I2C] =
  174. clk_register_fixed_rate(dev, "i2c", sys_refclk_name, 0, 100000000);
  175. clks[ARTPEC6_CLK_SYS_TIMER] =
  176. clk_register_fixed_rate(dev, "timer", sys_refclk_name, 0,
  177. 100000000);
  178. clks[ARTPEC6_CLK_FRACDIV_IN] =
  179. clk_register_fixed_rate(dev, "fracdiv_in", sys_refclk_name, 0,
  180. 600000000);
  181. for (i = 0; i < ARTPEC6_CLK_NUMCLOCKS; ++i) {
  182. if (IS_ERR(clks[i]) && PTR_ERR(clks[i]) != -EPROBE_DEFER) {
  183. dev_err(dev,
  184. "Failed to register clock at index %d err=%ld\n",
  185. i, PTR_ERR(clks[i]));
  186. err = PTR_ERR(clks[i]);
  187. }
  188. }
  189. return err;
  190. }
  191. static const struct of_device_id artpec_clkctrl_of_match[] = {
  192. { .compatible = "axis,artpec6-clkctrl" },
  193. {}
  194. };
  195. static struct platform_driver artpec6_clkctrl_driver = {
  196. .probe = artpec6_clkctrl_probe,
  197. .driver = {
  198. .name = "artpec6_clkctrl",
  199. .of_match_table = artpec_clkctrl_of_match,
  200. },
  201. };
  202. builtin_platform_driver(artpec6_clkctrl_driver);