sama5d3.c 6.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. #include <linux/clk-provider.h>
  3. #include <linux/mfd/syscon.h>
  4. #include <linux/slab.h>
  5. #include <dt-bindings/clock/at91.h>
  6. #include "pmc.h"
  7. static const struct clk_master_characteristics mck_characteristics = {
  8. .output = { .min = 0, .max = 166000000 },
  9. .divisors = { 1, 2, 4, 3 },
  10. };
  11. static u8 plla_out[] = { 0 };
  12. static u16 plla_icpll[] = { 0 };
  13. static const struct clk_range plla_outputs[] = {
  14. { .min = 400000000, .max = 1000000000 },
  15. };
  16. static const struct clk_pll_characteristics plla_characteristics = {
  17. .input = { .min = 8000000, .max = 50000000 },
  18. .num_output = ARRAY_SIZE(plla_outputs),
  19. .output = plla_outputs,
  20. .icpll = plla_icpll,
  21. .out = plla_out,
  22. };
  23. static const struct clk_pcr_layout sama5d3_pcr_layout = {
  24. .offset = 0x10c,
  25. .cmd = BIT(12),
  26. .pid_mask = GENMASK(6, 0),
  27. .div_mask = GENMASK(17, 16),
  28. };
  29. static const struct {
  30. char *n;
  31. char *p;
  32. u8 id;
  33. } sama5d3_systemck[] = {
  34. { .n = "ddrck", .p = "masterck", .id = 2 },
  35. { .n = "lcdck", .p = "masterck", .id = 3 },
  36. { .n = "smdck", .p = "smdclk", .id = 4 },
  37. { .n = "uhpck", .p = "usbck", .id = 6 },
  38. { .n = "udpck", .p = "usbck", .id = 7 },
  39. { .n = "pck0", .p = "prog0", .id = 8 },
  40. { .n = "pck1", .p = "prog1", .id = 9 },
  41. { .n = "pck2", .p = "prog2", .id = 10 },
  42. };
  43. static const struct {
  44. char *n;
  45. u8 id;
  46. struct clk_range r;
  47. } sama5d3_periphck[] = {
  48. { .n = "dbgu_clk", .id = 2, },
  49. { .n = "hsmc_clk", .id = 5, },
  50. { .n = "pioA_clk", .id = 6, },
  51. { .n = "pioB_clk", .id = 7, },
  52. { .n = "pioC_clk", .id = 8, },
  53. { .n = "pioD_clk", .id = 9, },
  54. { .n = "pioE_clk", .id = 10, },
  55. { .n = "usart0_clk", .id = 12, .r = { .min = 0, .max = 83000000 }, },
  56. { .n = "usart1_clk", .id = 13, .r = { .min = 0, .max = 83000000 }, },
  57. { .n = "usart2_clk", .id = 14, .r = { .min = 0, .max = 83000000 }, },
  58. { .n = "usart3_clk", .id = 15, .r = { .min = 0, .max = 83000000 }, },
  59. { .n = "uart0_clk", .id = 16, .r = { .min = 0, .max = 83000000 }, },
  60. { .n = "uart1_clk", .id = 17, .r = { .min = 0, .max = 83000000 }, },
  61. { .n = "twi0_clk", .id = 18, .r = { .min = 0, .max = 41500000 }, },
  62. { .n = "twi1_clk", .id = 19, .r = { .min = 0, .max = 41500000 }, },
  63. { .n = "twi2_clk", .id = 20, .r = { .min = 0, .max = 41500000 }, },
  64. { .n = "mci0_clk", .id = 21, },
  65. { .n = "mci1_clk", .id = 22, },
  66. { .n = "mci2_clk", .id = 23, },
  67. { .n = "spi0_clk", .id = 24, .r = { .min = 0, .max = 166000000 }, },
  68. { .n = "spi1_clk", .id = 25, .r = { .min = 0, .max = 166000000 }, },
  69. { .n = "tcb0_clk", .id = 26, .r = { .min = 0, .max = 166000000 }, },
  70. { .n = "tcb1_clk", .id = 27, .r = { .min = 0, .max = 166000000 }, },
  71. { .n = "pwm_clk", .id = 28, },
  72. { .n = "adc_clk", .id = 29, .r = { .min = 0, .max = 83000000 }, },
  73. { .n = "dma0_clk", .id = 30, },
  74. { .n = "dma1_clk", .id = 31, },
  75. { .n = "uhphs_clk", .id = 32, },
  76. { .n = "udphs_clk", .id = 33, },
  77. { .n = "macb0_clk", .id = 34, },
  78. { .n = "macb1_clk", .id = 35, },
  79. { .n = "lcdc_clk", .id = 36, },
  80. { .n = "isi_clk", .id = 37, },
  81. { .n = "ssc0_clk", .id = 38, .r = { .min = 0, .max = 83000000 }, },
  82. { .n = "ssc1_clk", .id = 39, .r = { .min = 0, .max = 83000000 }, },
  83. { .n = "can0_clk", .id = 40, .r = { .min = 0, .max = 83000000 }, },
  84. { .n = "can1_clk", .id = 41, .r = { .min = 0, .max = 83000000 }, },
  85. { .n = "sha_clk", .id = 42, },
  86. { .n = "aes_clk", .id = 43, },
  87. { .n = "tdes_clk", .id = 44, },
  88. { .n = "trng_clk", .id = 45, },
  89. { .n = "fuse_clk", .id = 48, },
  90. { .n = "mpddr_clk", .id = 49, },
  91. };
  92. static void __init sama5d3_pmc_setup(struct device_node *np)
  93. {
  94. const char *slck_name, *mainxtal_name;
  95. struct pmc_data *sama5d3_pmc;
  96. const char *parent_names[5];
  97. struct regmap *regmap;
  98. struct clk_hw *hw;
  99. int i;
  100. bool bypass;
  101. i = of_property_match_string(np, "clock-names", "slow_clk");
  102. if (i < 0)
  103. return;
  104. slck_name = of_clk_get_parent_name(np, i);
  105. i = of_property_match_string(np, "clock-names", "main_xtal");
  106. if (i < 0)
  107. return;
  108. mainxtal_name = of_clk_get_parent_name(np, i);
  109. regmap = device_node_to_regmap(np);
  110. if (IS_ERR(regmap))
  111. return;
  112. sama5d3_pmc = pmc_data_allocate(PMC_PLLACK + 1,
  113. nck(sama5d3_systemck),
  114. nck(sama5d3_periphck), 0, 3);
  115. if (!sama5d3_pmc)
  116. return;
  117. hw = at91_clk_register_main_rc_osc(regmap, "main_rc_osc", 12000000,
  118. 50000000);
  119. if (IS_ERR(hw))
  120. goto err_free;
  121. bypass = of_property_read_bool(np, "atmel,osc-bypass");
  122. hw = at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name,
  123. bypass);
  124. if (IS_ERR(hw))
  125. goto err_free;
  126. parent_names[0] = "main_rc_osc";
  127. parent_names[1] = "main_osc";
  128. hw = at91_clk_register_sam9x5_main(regmap, "mainck", parent_names, 2);
  129. if (IS_ERR(hw))
  130. goto err_free;
  131. hw = at91_clk_register_pll(regmap, "pllack", "mainck", 0,
  132. &sama5d3_pll_layout, &plla_characteristics);
  133. if (IS_ERR(hw))
  134. goto err_free;
  135. hw = at91_clk_register_plldiv(regmap, "plladivck", "pllack");
  136. if (IS_ERR(hw))
  137. goto err_free;
  138. sama5d3_pmc->chws[PMC_PLLACK] = hw;
  139. hw = at91_clk_register_utmi(regmap, NULL, "utmick", "mainck");
  140. if (IS_ERR(hw))
  141. goto err_free;
  142. sama5d3_pmc->chws[PMC_UTMI] = hw;
  143. parent_names[0] = slck_name;
  144. parent_names[1] = "mainck";
  145. parent_names[2] = "plladivck";
  146. parent_names[3] = "utmick";
  147. hw = at91_clk_register_master(regmap, "masterck", 4, parent_names,
  148. &at91sam9x5_master_layout,
  149. &mck_characteristics);
  150. if (IS_ERR(hw))
  151. goto err_free;
  152. sama5d3_pmc->chws[PMC_MCK] = hw;
  153. parent_names[0] = "plladivck";
  154. parent_names[1] = "utmick";
  155. hw = at91sam9x5_clk_register_usb(regmap, "usbck", parent_names, 2);
  156. if (IS_ERR(hw))
  157. goto err_free;
  158. hw = at91sam9x5_clk_register_smd(regmap, "smdclk", parent_names, 2);
  159. if (IS_ERR(hw))
  160. goto err_free;
  161. parent_names[0] = slck_name;
  162. parent_names[1] = "mainck";
  163. parent_names[2] = "plladivck";
  164. parent_names[3] = "utmick";
  165. parent_names[4] = "masterck";
  166. for (i = 0; i < 3; i++) {
  167. char name[6];
  168. snprintf(name, sizeof(name), "prog%d", i);
  169. hw = at91_clk_register_programmable(regmap, name,
  170. parent_names, 5, i,
  171. &at91sam9x5_programmable_layout,
  172. NULL);
  173. if (IS_ERR(hw))
  174. goto err_free;
  175. sama5d3_pmc->pchws[i] = hw;
  176. }
  177. for (i = 0; i < ARRAY_SIZE(sama5d3_systemck); i++) {
  178. hw = at91_clk_register_system(regmap, sama5d3_systemck[i].n,
  179. sama5d3_systemck[i].p,
  180. sama5d3_systemck[i].id);
  181. if (IS_ERR(hw))
  182. goto err_free;
  183. sama5d3_pmc->shws[sama5d3_systemck[i].id] = hw;
  184. }
  185. for (i = 0; i < ARRAY_SIZE(sama5d3_periphck); i++) {
  186. hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock,
  187. &sama5d3_pcr_layout,
  188. sama5d3_periphck[i].n,
  189. "masterck",
  190. sama5d3_periphck[i].id,
  191. &sama5d3_periphck[i].r,
  192. INT_MIN);
  193. if (IS_ERR(hw))
  194. goto err_free;
  195. sama5d3_pmc->phws[sama5d3_periphck[i].id] = hw;
  196. }
  197. of_clk_add_hw_provider(np, of_clk_hw_pmc_get, sama5d3_pmc);
  198. return;
  199. err_free:
  200. kfree(sama5d3_pmc);
  201. }
  202. /*
  203. * The TCB is used as the clocksource so its clock is needed early. This means
  204. * this can't be a platform driver.
  205. */
  206. CLK_OF_DECLARE_DRIVER(sama5d3_pmc, "atmel,sama5d3-pmc", sama5d3_pmc_setup);