sama5d2.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. #include <linux/clk-provider.h>
  3. #include <linux/mfd/syscon.h>
  4. #include <linux/slab.h>
  5. #include <dt-bindings/clock/at91.h>
  6. #include "pmc.h"
  7. static const struct clk_master_characteristics mck_characteristics = {
  8. .output = { .min = 124000000, .max = 166000000 },
  9. .divisors = { 1, 2, 4, 3 },
  10. };
  11. static u8 plla_out[] = { 0 };
  12. static u16 plla_icpll[] = { 0 };
  13. static const struct clk_range plla_outputs[] = {
  14. { .min = 600000000, .max = 1200000000 },
  15. };
  16. static const struct clk_pll_characteristics plla_characteristics = {
  17. .input = { .min = 12000000, .max = 24000000 },
  18. .num_output = ARRAY_SIZE(plla_outputs),
  19. .output = plla_outputs,
  20. .icpll = plla_icpll,
  21. .out = plla_out,
  22. };
  23. static const struct clk_pcr_layout sama5d2_pcr_layout = {
  24. .offset = 0x10c,
  25. .cmd = BIT(12),
  26. .gckcss_mask = GENMASK(10, 8),
  27. .pid_mask = GENMASK(6, 0),
  28. };
  29. static const struct {
  30. char *n;
  31. char *p;
  32. u8 id;
  33. } sama5d2_systemck[] = {
  34. { .n = "ddrck", .p = "masterck", .id = 2 },
  35. { .n = "lcdck", .p = "masterck", .id = 3 },
  36. { .n = "uhpck", .p = "usbck", .id = 6 },
  37. { .n = "udpck", .p = "usbck", .id = 7 },
  38. { .n = "pck0", .p = "prog0", .id = 8 },
  39. { .n = "pck1", .p = "prog1", .id = 9 },
  40. { .n = "pck2", .p = "prog2", .id = 10 },
  41. { .n = "iscck", .p = "masterck", .id = 18 },
  42. };
  43. static const struct {
  44. char *n;
  45. u8 id;
  46. struct clk_range r;
  47. } sama5d2_periph32ck[] = {
  48. { .n = "macb0_clk", .id = 5, .r = { .min = 0, .max = 83000000 }, },
  49. { .n = "tdes_clk", .id = 11, .r = { .min = 0, .max = 83000000 }, },
  50. { .n = "matrix1_clk", .id = 14, },
  51. { .n = "hsmc_clk", .id = 17, },
  52. { .n = "pioA_clk", .id = 18, .r = { .min = 0, .max = 83000000 }, },
  53. { .n = "flx0_clk", .id = 19, .r = { .min = 0, .max = 83000000 }, },
  54. { .n = "flx1_clk", .id = 20, .r = { .min = 0, .max = 83000000 }, },
  55. { .n = "flx2_clk", .id = 21, .r = { .min = 0, .max = 83000000 }, },
  56. { .n = "flx3_clk", .id = 22, .r = { .min = 0, .max = 83000000 }, },
  57. { .n = "flx4_clk", .id = 23, .r = { .min = 0, .max = 83000000 }, },
  58. { .n = "uart0_clk", .id = 24, .r = { .min = 0, .max = 83000000 }, },
  59. { .n = "uart1_clk", .id = 25, .r = { .min = 0, .max = 83000000 }, },
  60. { .n = "uart2_clk", .id = 26, .r = { .min = 0, .max = 83000000 }, },
  61. { .n = "uart3_clk", .id = 27, .r = { .min = 0, .max = 83000000 }, },
  62. { .n = "uart4_clk", .id = 28, .r = { .min = 0, .max = 83000000 }, },
  63. { .n = "twi0_clk", .id = 29, .r = { .min = 0, .max = 83000000 }, },
  64. { .n = "twi1_clk", .id = 30, .r = { .min = 0, .max = 83000000 }, },
  65. { .n = "spi0_clk", .id = 33, .r = { .min = 0, .max = 83000000 }, },
  66. { .n = "spi1_clk", .id = 34, .r = { .min = 0, .max = 83000000 }, },
  67. { .n = "tcb0_clk", .id = 35, .r = { .min = 0, .max = 83000000 }, },
  68. { .n = "tcb1_clk", .id = 36, .r = { .min = 0, .max = 83000000 }, },
  69. { .n = "pwm_clk", .id = 38, .r = { .min = 0, .max = 83000000 }, },
  70. { .n = "adc_clk", .id = 40, .r = { .min = 0, .max = 83000000 }, },
  71. { .n = "uhphs_clk", .id = 41, .r = { .min = 0, .max = 83000000 }, },
  72. { .n = "udphs_clk", .id = 42, .r = { .min = 0, .max = 83000000 }, },
  73. { .n = "ssc0_clk", .id = 43, .r = { .min = 0, .max = 83000000 }, },
  74. { .n = "ssc1_clk", .id = 44, .r = { .min = 0, .max = 83000000 }, },
  75. { .n = "trng_clk", .id = 47, .r = { .min = 0, .max = 83000000 }, },
  76. { .n = "pdmic_clk", .id = 48, .r = { .min = 0, .max = 83000000 }, },
  77. { .n = "securam_clk", .id = 51, },
  78. { .n = "i2s0_clk", .id = 54, .r = { .min = 0, .max = 83000000 }, },
  79. { .n = "i2s1_clk", .id = 55, .r = { .min = 0, .max = 83000000 }, },
  80. { .n = "can0_clk", .id = 56, .r = { .min = 0, .max = 83000000 }, },
  81. { .n = "can1_clk", .id = 57, .r = { .min = 0, .max = 83000000 }, },
  82. { .n = "ptc_clk", .id = 58, .r = { .min = 0, .max = 83000000 }, },
  83. { .n = "classd_clk", .id = 59, .r = { .min = 0, .max = 83000000 }, },
  84. };
  85. static const struct {
  86. char *n;
  87. u8 id;
  88. } sama5d2_periphck[] = {
  89. { .n = "dma0_clk", .id = 6, },
  90. { .n = "dma1_clk", .id = 7, },
  91. { .n = "aes_clk", .id = 9, },
  92. { .n = "aesb_clk", .id = 10, },
  93. { .n = "sha_clk", .id = 12, },
  94. { .n = "mpddr_clk", .id = 13, },
  95. { .n = "matrix0_clk", .id = 15, },
  96. { .n = "sdmmc0_hclk", .id = 31, },
  97. { .n = "sdmmc1_hclk", .id = 32, },
  98. { .n = "lcdc_clk", .id = 45, },
  99. { .n = "isc_clk", .id = 46, },
  100. { .n = "qspi0_clk", .id = 52, },
  101. { .n = "qspi1_clk", .id = 53, },
  102. };
  103. static const struct {
  104. char *n;
  105. u8 id;
  106. struct clk_range r;
  107. int chg_pid;
  108. } sama5d2_gck[] = {
  109. { .n = "sdmmc0_gclk", .id = 31, .chg_pid = INT_MIN, },
  110. { .n = "sdmmc1_gclk", .id = 32, .chg_pid = INT_MIN, },
  111. { .n = "tcb0_gclk", .id = 35, .chg_pid = INT_MIN, .r = { .min = 0, .max = 83000000 }, },
  112. { .n = "tcb1_gclk", .id = 36, .chg_pid = INT_MIN, .r = { .min = 0, .max = 83000000 }, },
  113. { .n = "pwm_gclk", .id = 38, .chg_pid = INT_MIN, .r = { .min = 0, .max = 83000000 }, },
  114. { .n = "isc_gclk", .id = 46, .chg_pid = INT_MIN, },
  115. { .n = "pdmic_gclk", .id = 48, .chg_pid = INT_MIN, },
  116. { .n = "i2s0_gclk", .id = 54, .chg_pid = 5, },
  117. { .n = "i2s1_gclk", .id = 55, .chg_pid = 5, },
  118. { .n = "can0_gclk", .id = 56, .chg_pid = INT_MIN, .r = { .min = 0, .max = 80000000 }, },
  119. { .n = "can1_gclk", .id = 57, .chg_pid = INT_MIN, .r = { .min = 0, .max = 80000000 }, },
  120. { .n = "classd_gclk", .id = 59, .chg_pid = 5, .r = { .min = 0, .max = 100000000 }, },
  121. };
  122. static const struct clk_programmable_layout sama5d2_programmable_layout = {
  123. .pres_mask = 0xff,
  124. .pres_shift = 4,
  125. .css_mask = 0x7,
  126. .have_slck_mck = 0,
  127. .is_pres_direct = 1,
  128. };
  129. static void __init sama5d2_pmc_setup(struct device_node *np)
  130. {
  131. struct clk_range range = CLK_RANGE(0, 0);
  132. const char *slck_name, *mainxtal_name;
  133. struct pmc_data *sama5d2_pmc;
  134. const char *parent_names[6];
  135. struct regmap *regmap, *regmap_sfr;
  136. struct clk_hw *hw;
  137. int i;
  138. bool bypass;
  139. i = of_property_match_string(np, "clock-names", "slow_clk");
  140. if (i < 0)
  141. return;
  142. slck_name = of_clk_get_parent_name(np, i);
  143. i = of_property_match_string(np, "clock-names", "main_xtal");
  144. if (i < 0)
  145. return;
  146. mainxtal_name = of_clk_get_parent_name(np, i);
  147. regmap = device_node_to_regmap(np);
  148. if (IS_ERR(regmap))
  149. return;
  150. sama5d2_pmc = pmc_data_allocate(PMC_AUDIOPLLCK + 1,
  151. nck(sama5d2_systemck),
  152. nck(sama5d2_periph32ck),
  153. nck(sama5d2_gck), 3);
  154. if (!sama5d2_pmc)
  155. return;
  156. hw = at91_clk_register_main_rc_osc(regmap, "main_rc_osc", 12000000,
  157. 100000000);
  158. if (IS_ERR(hw))
  159. goto err_free;
  160. bypass = of_property_read_bool(np, "atmel,osc-bypass");
  161. hw = at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name,
  162. bypass);
  163. if (IS_ERR(hw))
  164. goto err_free;
  165. parent_names[0] = "main_rc_osc";
  166. parent_names[1] = "main_osc";
  167. hw = at91_clk_register_sam9x5_main(regmap, "mainck", parent_names, 2);
  168. if (IS_ERR(hw))
  169. goto err_free;
  170. sama5d2_pmc->chws[PMC_MAIN] = hw;
  171. hw = at91_clk_register_pll(regmap, "pllack", "mainck", 0,
  172. &sama5d3_pll_layout, &plla_characteristics);
  173. if (IS_ERR(hw))
  174. goto err_free;
  175. hw = at91_clk_register_plldiv(regmap, "plladivck", "pllack");
  176. if (IS_ERR(hw))
  177. goto err_free;
  178. sama5d2_pmc->chws[PMC_PLLACK] = hw;
  179. hw = at91_clk_register_audio_pll_frac(regmap, "audiopll_fracck",
  180. "mainck");
  181. if (IS_ERR(hw))
  182. goto err_free;
  183. hw = at91_clk_register_audio_pll_pad(regmap, "audiopll_padck",
  184. "audiopll_fracck");
  185. if (IS_ERR(hw))
  186. goto err_free;
  187. hw = at91_clk_register_audio_pll_pmc(regmap, "audiopll_pmcck",
  188. "audiopll_fracck");
  189. if (IS_ERR(hw))
  190. goto err_free;
  191. sama5d2_pmc->chws[PMC_AUDIOPLLCK] = hw;
  192. regmap_sfr = syscon_regmap_lookup_by_compatible("atmel,sama5d2-sfr");
  193. if (IS_ERR(regmap_sfr))
  194. regmap_sfr = NULL;
  195. hw = at91_clk_register_utmi(regmap, regmap_sfr, "utmick", "mainck");
  196. if (IS_ERR(hw))
  197. goto err_free;
  198. sama5d2_pmc->chws[PMC_UTMI] = hw;
  199. parent_names[0] = slck_name;
  200. parent_names[1] = "mainck";
  201. parent_names[2] = "plladivck";
  202. parent_names[3] = "utmick";
  203. hw = at91_clk_register_master(regmap, "masterck", 4, parent_names,
  204. &at91sam9x5_master_layout,
  205. &mck_characteristics);
  206. if (IS_ERR(hw))
  207. goto err_free;
  208. sama5d2_pmc->chws[PMC_MCK] = hw;
  209. hw = at91_clk_register_h32mx(regmap, "h32mxck", "masterck");
  210. if (IS_ERR(hw))
  211. goto err_free;
  212. sama5d2_pmc->chws[PMC_MCK2] = hw;
  213. parent_names[0] = "plladivck";
  214. parent_names[1] = "utmick";
  215. hw = at91sam9x5_clk_register_usb(regmap, "usbck", parent_names, 2);
  216. if (IS_ERR(hw))
  217. goto err_free;
  218. parent_names[0] = slck_name;
  219. parent_names[1] = "mainck";
  220. parent_names[2] = "plladivck";
  221. parent_names[3] = "utmick";
  222. parent_names[4] = "masterck";
  223. parent_names[5] = "audiopll_pmcck";
  224. for (i = 0; i < 3; i++) {
  225. char name[6];
  226. snprintf(name, sizeof(name), "prog%d", i);
  227. hw = at91_clk_register_programmable(regmap, name,
  228. parent_names, 6, i,
  229. &sama5d2_programmable_layout,
  230. NULL);
  231. if (IS_ERR(hw))
  232. goto err_free;
  233. sama5d2_pmc->pchws[i] = hw;
  234. }
  235. for (i = 0; i < ARRAY_SIZE(sama5d2_systemck); i++) {
  236. hw = at91_clk_register_system(regmap, sama5d2_systemck[i].n,
  237. sama5d2_systemck[i].p,
  238. sama5d2_systemck[i].id);
  239. if (IS_ERR(hw))
  240. goto err_free;
  241. sama5d2_pmc->shws[sama5d2_systemck[i].id] = hw;
  242. }
  243. for (i = 0; i < ARRAY_SIZE(sama5d2_periphck); i++) {
  244. hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock,
  245. &sama5d2_pcr_layout,
  246. sama5d2_periphck[i].n,
  247. "masterck",
  248. sama5d2_periphck[i].id,
  249. &range, INT_MIN);
  250. if (IS_ERR(hw))
  251. goto err_free;
  252. sama5d2_pmc->phws[sama5d2_periphck[i].id] = hw;
  253. }
  254. for (i = 0; i < ARRAY_SIZE(sama5d2_periph32ck); i++) {
  255. hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock,
  256. &sama5d2_pcr_layout,
  257. sama5d2_periph32ck[i].n,
  258. "h32mxck",
  259. sama5d2_periph32ck[i].id,
  260. &sama5d2_periph32ck[i].r,
  261. INT_MIN);
  262. if (IS_ERR(hw))
  263. goto err_free;
  264. sama5d2_pmc->phws[sama5d2_periph32ck[i].id] = hw;
  265. }
  266. parent_names[0] = slck_name;
  267. parent_names[1] = "mainck";
  268. parent_names[2] = "plladivck";
  269. parent_names[3] = "utmick";
  270. parent_names[4] = "masterck";
  271. parent_names[5] = "audiopll_pmcck";
  272. for (i = 0; i < ARRAY_SIZE(sama5d2_gck); i++) {
  273. hw = at91_clk_register_generated(regmap, &pmc_pcr_lock,
  274. &sama5d2_pcr_layout,
  275. sama5d2_gck[i].n,
  276. parent_names, NULL, 6,
  277. sama5d2_gck[i].id,
  278. &sama5d2_gck[i].r,
  279. sama5d2_gck[i].chg_pid);
  280. if (IS_ERR(hw))
  281. goto err_free;
  282. sama5d2_pmc->ghws[sama5d2_gck[i].id] = hw;
  283. }
  284. if (regmap_sfr) {
  285. parent_names[0] = "i2s0_clk";
  286. parent_names[1] = "i2s0_gclk";
  287. hw = at91_clk_i2s_mux_register(regmap_sfr, "i2s0_muxclk",
  288. parent_names, 2, 0);
  289. if (IS_ERR(hw))
  290. goto err_free;
  291. sama5d2_pmc->chws[PMC_I2S0_MUX] = hw;
  292. parent_names[0] = "i2s1_clk";
  293. parent_names[1] = "i2s1_gclk";
  294. hw = at91_clk_i2s_mux_register(regmap_sfr, "i2s1_muxclk",
  295. parent_names, 2, 1);
  296. if (IS_ERR(hw))
  297. goto err_free;
  298. sama5d2_pmc->chws[PMC_I2S1_MUX] = hw;
  299. }
  300. of_clk_add_hw_provider(np, of_clk_hw_pmc_get, sama5d2_pmc);
  301. return;
  302. err_free:
  303. kfree(sama5d2_pmc);
  304. }
  305. CLK_OF_DECLARE_DRIVER(sama5d2_pmc, "atmel,sama5d2-pmc", sama5d2_pmc_setup);