pmc.c 6.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
  4. */
  5. #include <linux/clk-provider.h>
  6. #include <linux/clkdev.h>
  7. #include <linux/clk/at91_pmc.h>
  8. #include <linux/of.h>
  9. #include <linux/mfd/syscon.h>
  10. #include <linux/platform_device.h>
  11. #include <linux/regmap.h>
  12. #include <linux/syscore_ops.h>
  13. #include <asm/proc-fns.h>
  14. #include <dt-bindings/clock/at91.h>
  15. #include "pmc.h"
  16. #define PMC_MAX_IDS 128
  17. #define PMC_MAX_PCKS 8
  18. int of_at91_get_clk_range(struct device_node *np, const char *propname,
  19. struct clk_range *range)
  20. {
  21. u32 min, max;
  22. int ret;
  23. ret = of_property_read_u32_index(np, propname, 0, &min);
  24. if (ret)
  25. return ret;
  26. ret = of_property_read_u32_index(np, propname, 1, &max);
  27. if (ret)
  28. return ret;
  29. if (range) {
  30. range->min = min;
  31. range->max = max;
  32. }
  33. return 0;
  34. }
  35. EXPORT_SYMBOL_GPL(of_at91_get_clk_range);
  36. struct clk_hw *of_clk_hw_pmc_get(struct of_phandle_args *clkspec, void *data)
  37. {
  38. unsigned int type = clkspec->args[0];
  39. unsigned int idx = clkspec->args[1];
  40. struct pmc_data *pmc_data = data;
  41. switch (type) {
  42. case PMC_TYPE_CORE:
  43. if (idx < pmc_data->ncore)
  44. return pmc_data->chws[idx];
  45. break;
  46. case PMC_TYPE_SYSTEM:
  47. if (idx < pmc_data->nsystem)
  48. return pmc_data->shws[idx];
  49. break;
  50. case PMC_TYPE_PERIPHERAL:
  51. if (idx < pmc_data->nperiph)
  52. return pmc_data->phws[idx];
  53. break;
  54. case PMC_TYPE_GCK:
  55. if (idx < pmc_data->ngck)
  56. return pmc_data->ghws[idx];
  57. break;
  58. case PMC_TYPE_PROGRAMMABLE:
  59. if (idx < pmc_data->npck)
  60. return pmc_data->pchws[idx];
  61. break;
  62. default:
  63. break;
  64. }
  65. pr_err("%s: invalid type (%u) or index (%u)\n", __func__, type, idx);
  66. return ERR_PTR(-EINVAL);
  67. }
  68. struct pmc_data *pmc_data_allocate(unsigned int ncore, unsigned int nsystem,
  69. unsigned int nperiph, unsigned int ngck,
  70. unsigned int npck)
  71. {
  72. unsigned int num_clks = ncore + nsystem + nperiph + ngck + npck;
  73. struct pmc_data *pmc_data;
  74. pmc_data = kzalloc(struct_size(pmc_data, hwtable, num_clks),
  75. GFP_KERNEL);
  76. if (!pmc_data)
  77. return NULL;
  78. pmc_data->ncore = ncore;
  79. pmc_data->chws = pmc_data->hwtable;
  80. pmc_data->nsystem = nsystem;
  81. pmc_data->shws = pmc_data->chws + ncore;
  82. pmc_data->nperiph = nperiph;
  83. pmc_data->phws = pmc_data->shws + nsystem;
  84. pmc_data->ngck = ngck;
  85. pmc_data->ghws = pmc_data->phws + nperiph;
  86. pmc_data->npck = npck;
  87. pmc_data->pchws = pmc_data->ghws + ngck;
  88. return pmc_data;
  89. }
  90. #ifdef CONFIG_PM
  91. static struct regmap *pmcreg;
  92. static u8 registered_ids[PMC_MAX_IDS];
  93. static u8 registered_pcks[PMC_MAX_PCKS];
  94. static struct
  95. {
  96. u32 scsr;
  97. u32 pcsr0;
  98. u32 uckr;
  99. u32 mor;
  100. u32 mcfr;
  101. u32 pllar;
  102. u32 mckr;
  103. u32 usb;
  104. u32 imr;
  105. u32 pcsr1;
  106. u32 pcr[PMC_MAX_IDS];
  107. u32 audio_pll0;
  108. u32 audio_pll1;
  109. u32 pckr[PMC_MAX_PCKS];
  110. } pmc_cache;
  111. /*
  112. * As Peripheral ID 0 is invalid on AT91 chips, the identifier is stored
  113. * without alteration in the table, and 0 is for unused clocks.
  114. */
  115. void pmc_register_id(u8 id)
  116. {
  117. int i;
  118. for (i = 0; i < PMC_MAX_IDS; i++) {
  119. if (registered_ids[i] == 0) {
  120. registered_ids[i] = id;
  121. break;
  122. }
  123. if (registered_ids[i] == id)
  124. break;
  125. }
  126. }
  127. /*
  128. * As Programmable Clock 0 is valid on AT91 chips, there is an offset
  129. * of 1 between the stored value and the real clock ID.
  130. */
  131. void pmc_register_pck(u8 pck)
  132. {
  133. int i;
  134. for (i = 0; i < PMC_MAX_PCKS; i++) {
  135. if (registered_pcks[i] == 0) {
  136. registered_pcks[i] = pck + 1;
  137. break;
  138. }
  139. if (registered_pcks[i] == (pck + 1))
  140. break;
  141. }
  142. }
  143. static int pmc_suspend(void)
  144. {
  145. int i;
  146. u8 num;
  147. regmap_read(pmcreg, AT91_PMC_SCSR, &pmc_cache.scsr);
  148. regmap_read(pmcreg, AT91_PMC_PCSR, &pmc_cache.pcsr0);
  149. regmap_read(pmcreg, AT91_CKGR_UCKR, &pmc_cache.uckr);
  150. regmap_read(pmcreg, AT91_CKGR_MOR, &pmc_cache.mor);
  151. regmap_read(pmcreg, AT91_CKGR_MCFR, &pmc_cache.mcfr);
  152. regmap_read(pmcreg, AT91_CKGR_PLLAR, &pmc_cache.pllar);
  153. regmap_read(pmcreg, AT91_PMC_MCKR, &pmc_cache.mckr);
  154. regmap_read(pmcreg, AT91_PMC_USB, &pmc_cache.usb);
  155. regmap_read(pmcreg, AT91_PMC_IMR, &pmc_cache.imr);
  156. regmap_read(pmcreg, AT91_PMC_PCSR1, &pmc_cache.pcsr1);
  157. for (i = 0; registered_ids[i]; i++) {
  158. regmap_write(pmcreg, AT91_PMC_PCR,
  159. (registered_ids[i] & AT91_PMC_PCR_PID_MASK));
  160. regmap_read(pmcreg, AT91_PMC_PCR,
  161. &pmc_cache.pcr[registered_ids[i]]);
  162. }
  163. for (i = 0; registered_pcks[i]; i++) {
  164. num = registered_pcks[i] - 1;
  165. regmap_read(pmcreg, AT91_PMC_PCKR(num), &pmc_cache.pckr[num]);
  166. }
  167. return 0;
  168. }
  169. static bool pmc_ready(unsigned int mask)
  170. {
  171. unsigned int status;
  172. regmap_read(pmcreg, AT91_PMC_SR, &status);
  173. return ((status & mask) == mask) ? 1 : 0;
  174. }
  175. static void pmc_resume(void)
  176. {
  177. int i;
  178. u8 num;
  179. u32 tmp;
  180. u32 mask = AT91_PMC_MCKRDY | AT91_PMC_LOCKA;
  181. regmap_read(pmcreg, AT91_PMC_MCKR, &tmp);
  182. if (pmc_cache.mckr != tmp)
  183. pr_warn("MCKR was not configured properly by the firmware\n");
  184. regmap_read(pmcreg, AT91_CKGR_PLLAR, &tmp);
  185. if (pmc_cache.pllar != tmp)
  186. pr_warn("PLLAR was not configured properly by the firmware\n");
  187. regmap_write(pmcreg, AT91_PMC_SCER, pmc_cache.scsr);
  188. regmap_write(pmcreg, AT91_PMC_PCER, pmc_cache.pcsr0);
  189. regmap_write(pmcreg, AT91_CKGR_UCKR, pmc_cache.uckr);
  190. regmap_write(pmcreg, AT91_CKGR_MOR, pmc_cache.mor);
  191. regmap_write(pmcreg, AT91_CKGR_MCFR, pmc_cache.mcfr);
  192. regmap_write(pmcreg, AT91_PMC_USB, pmc_cache.usb);
  193. regmap_write(pmcreg, AT91_PMC_IMR, pmc_cache.imr);
  194. regmap_write(pmcreg, AT91_PMC_PCER1, pmc_cache.pcsr1);
  195. for (i = 0; registered_ids[i]; i++) {
  196. regmap_write(pmcreg, AT91_PMC_PCR,
  197. pmc_cache.pcr[registered_ids[i]] |
  198. AT91_PMC_PCR_CMD);
  199. }
  200. for (i = 0; registered_pcks[i]; i++) {
  201. num = registered_pcks[i] - 1;
  202. regmap_write(pmcreg, AT91_PMC_PCKR(num), pmc_cache.pckr[num]);
  203. }
  204. if (pmc_cache.uckr & AT91_PMC_UPLLEN)
  205. mask |= AT91_PMC_LOCKU;
  206. while (!pmc_ready(mask))
  207. cpu_relax();
  208. }
  209. static struct syscore_ops pmc_syscore_ops = {
  210. .suspend = pmc_suspend,
  211. .resume = pmc_resume,
  212. };
  213. static const struct of_device_id sama5d2_pmc_dt_ids[] = {
  214. { .compatible = "atmel,sama5d2-pmc" },
  215. { /* sentinel */ }
  216. };
  217. static int __init pmc_register_ops(void)
  218. {
  219. struct device_node *np;
  220. np = of_find_matching_node(NULL, sama5d2_pmc_dt_ids);
  221. if (!np)
  222. return -ENODEV;
  223. if (!of_device_is_available(np)) {
  224. of_node_put(np);
  225. return -ENODEV;
  226. }
  227. pmcreg = device_node_to_regmap(np);
  228. of_node_put(np);
  229. if (IS_ERR(pmcreg))
  230. return PTR_ERR(pmcreg);
  231. register_syscore_ops(&pmc_syscore_ops);
  232. return 0;
  233. }
  234. /* This has to happen before arch_initcall because of the tcb_clksrc driver */
  235. postcore_initcall(pmc_register_ops);
  236. #endif