clk-generated.c 8.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Copyright (C) 2015 Atmel Corporation,
  4. * Nicolas Ferre <nicolas.ferre@atmel.com>
  5. *
  6. * Based on clk-programmable & clk-peripheral drivers by Boris BREZILLON.
  7. */
  8. #include <linux/bitfield.h>
  9. #include <linux/clk-provider.h>
  10. #include <linux/clkdev.h>
  11. #include <linux/clk/at91_pmc.h>
  12. #include <linux/of.h>
  13. #include <linux/mfd/syscon.h>
  14. #include <linux/regmap.h>
  15. #include "pmc.h"
  16. #define GENERATED_MAX_DIV 255
  17. struct clk_generated {
  18. struct clk_hw hw;
  19. struct regmap *regmap;
  20. struct clk_range range;
  21. spinlock_t *lock;
  22. u32 *mux_table;
  23. u32 id;
  24. u32 gckdiv;
  25. const struct clk_pcr_layout *layout;
  26. u8 parent_id;
  27. int chg_pid;
  28. };
  29. #define to_clk_generated(hw) \
  30. container_of(hw, struct clk_generated, hw)
  31. static int clk_generated_enable(struct clk_hw *hw)
  32. {
  33. struct clk_generated *gck = to_clk_generated(hw);
  34. unsigned long flags;
  35. pr_debug("GCLK: %s, gckdiv = %d, parent id = %d\n",
  36. __func__, gck->gckdiv, gck->parent_id);
  37. spin_lock_irqsave(gck->lock, flags);
  38. regmap_write(gck->regmap, gck->layout->offset,
  39. (gck->id & gck->layout->pid_mask));
  40. regmap_update_bits(gck->regmap, gck->layout->offset,
  41. AT91_PMC_PCR_GCKDIV_MASK | gck->layout->gckcss_mask |
  42. gck->layout->cmd | AT91_PMC_PCR_GCKEN,
  43. field_prep(gck->layout->gckcss_mask, gck->parent_id) |
  44. gck->layout->cmd |
  45. FIELD_PREP(AT91_PMC_PCR_GCKDIV_MASK, gck->gckdiv) |
  46. AT91_PMC_PCR_GCKEN);
  47. spin_unlock_irqrestore(gck->lock, flags);
  48. return 0;
  49. }
  50. static void clk_generated_disable(struct clk_hw *hw)
  51. {
  52. struct clk_generated *gck = to_clk_generated(hw);
  53. unsigned long flags;
  54. spin_lock_irqsave(gck->lock, flags);
  55. regmap_write(gck->regmap, gck->layout->offset,
  56. (gck->id & gck->layout->pid_mask));
  57. regmap_update_bits(gck->regmap, gck->layout->offset,
  58. gck->layout->cmd | AT91_PMC_PCR_GCKEN,
  59. gck->layout->cmd);
  60. spin_unlock_irqrestore(gck->lock, flags);
  61. }
  62. static int clk_generated_is_enabled(struct clk_hw *hw)
  63. {
  64. struct clk_generated *gck = to_clk_generated(hw);
  65. unsigned long flags;
  66. unsigned int status;
  67. spin_lock_irqsave(gck->lock, flags);
  68. regmap_write(gck->regmap, gck->layout->offset,
  69. (gck->id & gck->layout->pid_mask));
  70. regmap_read(gck->regmap, gck->layout->offset, &status);
  71. spin_unlock_irqrestore(gck->lock, flags);
  72. return !!(status & AT91_PMC_PCR_GCKEN);
  73. }
  74. static unsigned long
  75. clk_generated_recalc_rate(struct clk_hw *hw,
  76. unsigned long parent_rate)
  77. {
  78. struct clk_generated *gck = to_clk_generated(hw);
  79. return DIV_ROUND_CLOSEST(parent_rate, gck->gckdiv + 1);
  80. }
  81. static void clk_generated_best_diff(struct clk_rate_request *req,
  82. struct clk_hw *parent,
  83. unsigned long parent_rate, u32 div,
  84. int *best_diff, long *best_rate)
  85. {
  86. unsigned long tmp_rate;
  87. int tmp_diff;
  88. if (!div)
  89. tmp_rate = parent_rate;
  90. else
  91. tmp_rate = parent_rate / div;
  92. tmp_diff = abs(req->rate - tmp_rate);
  93. if (*best_diff < 0 || *best_diff >= tmp_diff) {
  94. *best_rate = tmp_rate;
  95. *best_diff = tmp_diff;
  96. req->best_parent_rate = parent_rate;
  97. req->best_parent_hw = parent;
  98. }
  99. }
  100. static int clk_generated_determine_rate(struct clk_hw *hw,
  101. struct clk_rate_request *req)
  102. {
  103. struct clk_generated *gck = to_clk_generated(hw);
  104. struct clk_hw *parent = NULL;
  105. struct clk_rate_request req_parent = *req;
  106. long best_rate = -EINVAL;
  107. unsigned long min_rate, parent_rate;
  108. int best_diff = -1;
  109. int i;
  110. u32 div;
  111. /* do not look for a rate that is outside of our range */
  112. if (gck->range.max && req->rate > gck->range.max)
  113. req->rate = gck->range.max;
  114. if (gck->range.min && req->rate < gck->range.min)
  115. req->rate = gck->range.min;
  116. for (i = 0; i < clk_hw_get_num_parents(hw); i++) {
  117. if (gck->chg_pid == i)
  118. continue;
  119. parent = clk_hw_get_parent_by_index(hw, i);
  120. if (!parent)
  121. continue;
  122. parent_rate = clk_hw_get_rate(parent);
  123. min_rate = DIV_ROUND_CLOSEST(parent_rate, GENERATED_MAX_DIV + 1);
  124. if (!parent_rate ||
  125. (gck->range.max && min_rate > gck->range.max))
  126. continue;
  127. div = DIV_ROUND_CLOSEST(parent_rate, req->rate);
  128. if (div > GENERATED_MAX_DIV + 1)
  129. div = GENERATED_MAX_DIV + 1;
  130. clk_generated_best_diff(req, parent, parent_rate, div,
  131. &best_diff, &best_rate);
  132. if (!best_diff)
  133. break;
  134. }
  135. /*
  136. * The audio_pll rate can be modified, unlike the five others clocks
  137. * that should never be altered.
  138. * The audio_pll can technically be used by multiple consumers. However,
  139. * with the rate locking, the first consumer to enable to clock will be
  140. * the one definitely setting the rate of the clock.
  141. * Since audio IPs are most likely to request the same rate, we enforce
  142. * that the only clks able to modify gck rate are those of audio IPs.
  143. */
  144. if (gck->chg_pid < 0)
  145. goto end;
  146. parent = clk_hw_get_parent_by_index(hw, gck->chg_pid);
  147. if (!parent)
  148. goto end;
  149. for (div = 1; div < GENERATED_MAX_DIV + 2; div++) {
  150. req_parent.rate = req->rate * div;
  151. if (__clk_determine_rate(parent, &req_parent))
  152. continue;
  153. clk_generated_best_diff(req, parent, req_parent.rate, div,
  154. &best_diff, &best_rate);
  155. if (!best_diff)
  156. break;
  157. }
  158. end:
  159. pr_debug("GCLK: %s, best_rate = %ld, parent clk: %s @ %ld\n",
  160. __func__, best_rate,
  161. __clk_get_name((req->best_parent_hw)->clk),
  162. req->best_parent_rate);
  163. if (best_rate < 0 || (gck->range.max && best_rate > gck->range.max))
  164. return -EINVAL;
  165. req->rate = best_rate;
  166. return 0;
  167. }
  168. /* No modification of hardware as we have the flag CLK_SET_PARENT_GATE set */
  169. static int clk_generated_set_parent(struct clk_hw *hw, u8 index)
  170. {
  171. struct clk_generated *gck = to_clk_generated(hw);
  172. if (index >= clk_hw_get_num_parents(hw))
  173. return -EINVAL;
  174. if (gck->mux_table)
  175. gck->parent_id = clk_mux_index_to_val(gck->mux_table, 0, index);
  176. else
  177. gck->parent_id = index;
  178. return 0;
  179. }
  180. static u8 clk_generated_get_parent(struct clk_hw *hw)
  181. {
  182. struct clk_generated *gck = to_clk_generated(hw);
  183. return gck->parent_id;
  184. }
  185. /* No modification of hardware as we have the flag CLK_SET_RATE_GATE set */
  186. static int clk_generated_set_rate(struct clk_hw *hw,
  187. unsigned long rate,
  188. unsigned long parent_rate)
  189. {
  190. struct clk_generated *gck = to_clk_generated(hw);
  191. u32 div;
  192. if (!rate)
  193. return -EINVAL;
  194. if (gck->range.max && rate > gck->range.max)
  195. return -EINVAL;
  196. div = DIV_ROUND_CLOSEST(parent_rate, rate);
  197. if (div > GENERATED_MAX_DIV + 1 || !div)
  198. return -EINVAL;
  199. gck->gckdiv = div - 1;
  200. return 0;
  201. }
  202. static const struct clk_ops generated_ops = {
  203. .enable = clk_generated_enable,
  204. .disable = clk_generated_disable,
  205. .is_enabled = clk_generated_is_enabled,
  206. .recalc_rate = clk_generated_recalc_rate,
  207. .determine_rate = clk_generated_determine_rate,
  208. .get_parent = clk_generated_get_parent,
  209. .set_parent = clk_generated_set_parent,
  210. .set_rate = clk_generated_set_rate,
  211. };
  212. /**
  213. * clk_generated_startup - Initialize a given clock to its default parent and
  214. * divisor parameter.
  215. *
  216. * @gck: Generated clock to set the startup parameters for.
  217. *
  218. * Take parameters from the hardware and update local clock configuration
  219. * accordingly.
  220. */
  221. static void clk_generated_startup(struct clk_generated *gck)
  222. {
  223. u32 tmp;
  224. unsigned long flags;
  225. spin_lock_irqsave(gck->lock, flags);
  226. regmap_write(gck->regmap, gck->layout->offset,
  227. (gck->id & gck->layout->pid_mask));
  228. regmap_read(gck->regmap, gck->layout->offset, &tmp);
  229. spin_unlock_irqrestore(gck->lock, flags);
  230. gck->parent_id = field_get(gck->layout->gckcss_mask, tmp);
  231. gck->gckdiv = FIELD_GET(AT91_PMC_PCR_GCKDIV_MASK, tmp);
  232. }
  233. struct clk_hw * __init
  234. at91_clk_register_generated(struct regmap *regmap, spinlock_t *lock,
  235. const struct clk_pcr_layout *layout,
  236. const char *name, const char **parent_names,
  237. u32 *mux_table, u8 num_parents, u8 id,
  238. const struct clk_range *range,
  239. int chg_pid)
  240. {
  241. struct clk_generated *gck;
  242. struct clk_init_data init;
  243. struct clk_hw *hw;
  244. int ret;
  245. gck = kzalloc(sizeof(*gck), GFP_KERNEL);
  246. if (!gck)
  247. return ERR_PTR(-ENOMEM);
  248. init.name = name;
  249. init.ops = &generated_ops;
  250. init.parent_names = parent_names;
  251. init.num_parents = num_parents;
  252. init.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE;
  253. if (chg_pid >= 0)
  254. init.flags |= CLK_SET_RATE_PARENT;
  255. gck->id = id;
  256. gck->hw.init = &init;
  257. gck->regmap = regmap;
  258. gck->lock = lock;
  259. gck->range = *range;
  260. gck->chg_pid = chg_pid;
  261. gck->layout = layout;
  262. gck->mux_table = mux_table;
  263. clk_generated_startup(gck);
  264. hw = &gck->hw;
  265. ret = clk_hw_register(NULL, &gck->hw);
  266. if (ret) {
  267. kfree(gck);
  268. hw = ERR_PTR(ret);
  269. } else {
  270. pmc_register_id(id);
  271. }
  272. return hw;
  273. }