clk-audio-pll.c 14 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Copyright (C) 2016 Atmel Corporation,
  4. * Songjun Wu <songjun.wu@atmel.com>,
  5. * Nicolas Ferre <nicolas.ferre@atmel.com>
  6. * Copyright (C) 2017 Free Electrons,
  7. * Quentin Schulz <quentin.schulz@free-electrons.com>
  8. *
  9. * The Sama5d2 SoC has two audio PLLs (PMC and PAD) that shares the same parent
  10. * (FRAC). FRAC can output between 620 and 700MHz and only multiply the rate of
  11. * its own parent. PMC and PAD can then divide the FRAC rate to best match the
  12. * asked rate.
  13. *
  14. * Traits of FRAC clock:
  15. * enable - clk_enable writes nd, fracr parameters and enables PLL
  16. * rate - rate is adjustable.
  17. * clk->rate = parent->rate * ((nd + 1) + (fracr / 2^22))
  18. * parent - fixed parent. No clk_set_parent support
  19. *
  20. * Traits of PMC clock:
  21. * enable - clk_enable writes qdpmc, and enables PMC output
  22. * rate - rate is adjustable.
  23. * clk->rate = parent->rate / (qdpmc + 1)
  24. * parent - fixed parent. No clk_set_parent support
  25. *
  26. * Traits of PAD clock:
  27. * enable - clk_enable writes divisors and enables PAD output
  28. * rate - rate is adjustable.
  29. * clk->rate = parent->rate / (qdaudio * div))
  30. * parent - fixed parent. No clk_set_parent support
  31. */
  32. #include <linux/clk.h>
  33. #include <linux/clk-provider.h>
  34. #include <linux/clk/at91_pmc.h>
  35. #include <linux/of.h>
  36. #include <linux/mfd/syscon.h>
  37. #include <linux/regmap.h>
  38. #include <linux/slab.h>
  39. #include "pmc.h"
  40. #define AUDIO_PLL_DIV_FRAC BIT(22)
  41. #define AUDIO_PLL_ND_MAX (AT91_PMC_AUDIO_PLL_ND_MASK >> \
  42. AT91_PMC_AUDIO_PLL_ND_OFFSET)
  43. #define AUDIO_PLL_QDPAD(qd, div) ((AT91_PMC_AUDIO_PLL_QDPAD_EXTDIV(qd) & \
  44. AT91_PMC_AUDIO_PLL_QDPAD_EXTDIV_MASK) | \
  45. (AT91_PMC_AUDIO_PLL_QDPAD_DIV(div) & \
  46. AT91_PMC_AUDIO_PLL_QDPAD_DIV_MASK))
  47. #define AUDIO_PLL_QDPMC_MAX (AT91_PMC_AUDIO_PLL_QDPMC_MASK >> \
  48. AT91_PMC_AUDIO_PLL_QDPMC_OFFSET)
  49. #define AUDIO_PLL_FOUT_MIN 620000000UL
  50. #define AUDIO_PLL_FOUT_MAX 700000000UL
  51. struct clk_audio_frac {
  52. struct clk_hw hw;
  53. struct regmap *regmap;
  54. u32 fracr;
  55. u8 nd;
  56. };
  57. struct clk_audio_pad {
  58. struct clk_hw hw;
  59. struct regmap *regmap;
  60. u8 qdaudio;
  61. u8 div;
  62. };
  63. struct clk_audio_pmc {
  64. struct clk_hw hw;
  65. struct regmap *regmap;
  66. u8 qdpmc;
  67. };
  68. #define to_clk_audio_frac(hw) container_of(hw, struct clk_audio_frac, hw)
  69. #define to_clk_audio_pad(hw) container_of(hw, struct clk_audio_pad, hw)
  70. #define to_clk_audio_pmc(hw) container_of(hw, struct clk_audio_pmc, hw)
  71. static int clk_audio_pll_frac_enable(struct clk_hw *hw)
  72. {
  73. struct clk_audio_frac *frac = to_clk_audio_frac(hw);
  74. regmap_update_bits(frac->regmap, AT91_PMC_AUDIO_PLL0,
  75. AT91_PMC_AUDIO_PLL_RESETN, 0);
  76. regmap_update_bits(frac->regmap, AT91_PMC_AUDIO_PLL0,
  77. AT91_PMC_AUDIO_PLL_RESETN,
  78. AT91_PMC_AUDIO_PLL_RESETN);
  79. regmap_update_bits(frac->regmap, AT91_PMC_AUDIO_PLL1,
  80. AT91_PMC_AUDIO_PLL_FRACR_MASK, frac->fracr);
  81. /*
  82. * reset and enable have to be done in 2 separated writes
  83. * for AT91_PMC_AUDIO_PLL0
  84. */
  85. regmap_update_bits(frac->regmap, AT91_PMC_AUDIO_PLL0,
  86. AT91_PMC_AUDIO_PLL_PLLEN |
  87. AT91_PMC_AUDIO_PLL_ND_MASK,
  88. AT91_PMC_AUDIO_PLL_PLLEN |
  89. AT91_PMC_AUDIO_PLL_ND(frac->nd));
  90. return 0;
  91. }
  92. static int clk_audio_pll_pad_enable(struct clk_hw *hw)
  93. {
  94. struct clk_audio_pad *apad_ck = to_clk_audio_pad(hw);
  95. regmap_update_bits(apad_ck->regmap, AT91_PMC_AUDIO_PLL1,
  96. AT91_PMC_AUDIO_PLL_QDPAD_MASK,
  97. AUDIO_PLL_QDPAD(apad_ck->qdaudio, apad_ck->div));
  98. regmap_update_bits(apad_ck->regmap, AT91_PMC_AUDIO_PLL0,
  99. AT91_PMC_AUDIO_PLL_PADEN, AT91_PMC_AUDIO_PLL_PADEN);
  100. return 0;
  101. }
  102. static int clk_audio_pll_pmc_enable(struct clk_hw *hw)
  103. {
  104. struct clk_audio_pmc *apmc_ck = to_clk_audio_pmc(hw);
  105. regmap_update_bits(apmc_ck->regmap, AT91_PMC_AUDIO_PLL0,
  106. AT91_PMC_AUDIO_PLL_PMCEN |
  107. AT91_PMC_AUDIO_PLL_QDPMC_MASK,
  108. AT91_PMC_AUDIO_PLL_PMCEN |
  109. AT91_PMC_AUDIO_PLL_QDPMC(apmc_ck->qdpmc));
  110. return 0;
  111. }
  112. static void clk_audio_pll_frac_disable(struct clk_hw *hw)
  113. {
  114. struct clk_audio_frac *frac = to_clk_audio_frac(hw);
  115. regmap_update_bits(frac->regmap, AT91_PMC_AUDIO_PLL0,
  116. AT91_PMC_AUDIO_PLL_PLLEN, 0);
  117. /* do it in 2 separated writes */
  118. regmap_update_bits(frac->regmap, AT91_PMC_AUDIO_PLL0,
  119. AT91_PMC_AUDIO_PLL_RESETN, 0);
  120. }
  121. static void clk_audio_pll_pad_disable(struct clk_hw *hw)
  122. {
  123. struct clk_audio_pad *apad_ck = to_clk_audio_pad(hw);
  124. regmap_update_bits(apad_ck->regmap, AT91_PMC_AUDIO_PLL0,
  125. AT91_PMC_AUDIO_PLL_PADEN, 0);
  126. }
  127. static void clk_audio_pll_pmc_disable(struct clk_hw *hw)
  128. {
  129. struct clk_audio_pmc *apmc_ck = to_clk_audio_pmc(hw);
  130. regmap_update_bits(apmc_ck->regmap, AT91_PMC_AUDIO_PLL0,
  131. AT91_PMC_AUDIO_PLL_PMCEN, 0);
  132. }
  133. static unsigned long clk_audio_pll_fout(unsigned long parent_rate,
  134. unsigned long nd, unsigned long fracr)
  135. {
  136. unsigned long long fr = (unsigned long long)parent_rate * fracr;
  137. pr_debug("A PLL: %s, fr = %llu\n", __func__, fr);
  138. fr = DIV_ROUND_CLOSEST_ULL(fr, AUDIO_PLL_DIV_FRAC);
  139. pr_debug("A PLL: %s, fr = %llu\n", __func__, fr);
  140. return parent_rate * (nd + 1) + fr;
  141. }
  142. static unsigned long clk_audio_pll_frac_recalc_rate(struct clk_hw *hw,
  143. unsigned long parent_rate)
  144. {
  145. struct clk_audio_frac *frac = to_clk_audio_frac(hw);
  146. unsigned long fout;
  147. fout = clk_audio_pll_fout(parent_rate, frac->nd, frac->fracr);
  148. pr_debug("A PLL: %s, fout = %lu (nd = %u, fracr = %lu)\n", __func__,
  149. fout, frac->nd, (unsigned long)frac->fracr);
  150. return fout;
  151. }
  152. static unsigned long clk_audio_pll_pad_recalc_rate(struct clk_hw *hw,
  153. unsigned long parent_rate)
  154. {
  155. struct clk_audio_pad *apad_ck = to_clk_audio_pad(hw);
  156. unsigned long apad_rate = 0;
  157. if (apad_ck->qdaudio && apad_ck->div)
  158. apad_rate = parent_rate / (apad_ck->qdaudio * apad_ck->div);
  159. pr_debug("A PLL/PAD: %s, apad_rate = %lu (div = %u, qdaudio = %u)\n",
  160. __func__, apad_rate, apad_ck->div, apad_ck->qdaudio);
  161. return apad_rate;
  162. }
  163. static unsigned long clk_audio_pll_pmc_recalc_rate(struct clk_hw *hw,
  164. unsigned long parent_rate)
  165. {
  166. struct clk_audio_pmc *apmc_ck = to_clk_audio_pmc(hw);
  167. unsigned long apmc_rate = 0;
  168. apmc_rate = parent_rate / (apmc_ck->qdpmc + 1);
  169. pr_debug("A PLL/PMC: %s, apmc_rate = %lu (qdpmc = %u)\n", __func__,
  170. apmc_rate, apmc_ck->qdpmc);
  171. return apmc_rate;
  172. }
  173. static int clk_audio_pll_frac_compute_frac(unsigned long rate,
  174. unsigned long parent_rate,
  175. unsigned long *nd,
  176. unsigned long *fracr)
  177. {
  178. unsigned long long tmp, rem;
  179. if (!rate)
  180. return -EINVAL;
  181. tmp = rate;
  182. rem = do_div(tmp, parent_rate);
  183. if (!tmp || tmp >= AUDIO_PLL_ND_MAX)
  184. return -EINVAL;
  185. *nd = tmp - 1;
  186. tmp = rem * AUDIO_PLL_DIV_FRAC;
  187. tmp = DIV_ROUND_CLOSEST_ULL(tmp, parent_rate);
  188. if (tmp > AT91_PMC_AUDIO_PLL_FRACR_MASK)
  189. return -EINVAL;
  190. /* we can cast here as we verified the bounds just above */
  191. *fracr = (unsigned long)tmp;
  192. return 0;
  193. }
  194. static int clk_audio_pll_frac_determine_rate(struct clk_hw *hw,
  195. struct clk_rate_request *req)
  196. {
  197. unsigned long fracr, nd;
  198. int ret;
  199. pr_debug("A PLL: %s, rate = %lu (parent_rate = %lu)\n", __func__,
  200. req->rate, req->best_parent_rate);
  201. req->rate = clamp(req->rate, AUDIO_PLL_FOUT_MIN, AUDIO_PLL_FOUT_MAX);
  202. req->min_rate = max(req->min_rate, AUDIO_PLL_FOUT_MIN);
  203. req->max_rate = min(req->max_rate, AUDIO_PLL_FOUT_MAX);
  204. ret = clk_audio_pll_frac_compute_frac(req->rate, req->best_parent_rate,
  205. &nd, &fracr);
  206. if (ret)
  207. return ret;
  208. req->rate = clk_audio_pll_fout(req->best_parent_rate, nd, fracr);
  209. req->best_parent_hw = clk_hw_get_parent(hw);
  210. pr_debug("A PLL: %s, best_rate = %lu (nd = %lu, fracr = %lu)\n",
  211. __func__, req->rate, nd, fracr);
  212. return 0;
  213. }
  214. static long clk_audio_pll_pad_round_rate(struct clk_hw *hw, unsigned long rate,
  215. unsigned long *parent_rate)
  216. {
  217. struct clk_hw *pclk = clk_hw_get_parent(hw);
  218. long best_rate = -EINVAL;
  219. unsigned long best_parent_rate;
  220. unsigned long tmp_qd;
  221. u32 div;
  222. long tmp_rate;
  223. int tmp_diff;
  224. int best_diff = -1;
  225. pr_debug("A PLL/PAD: %s, rate = %lu (parent_rate = %lu)\n", __func__,
  226. rate, *parent_rate);
  227. /*
  228. * Rate divisor is actually made of two different divisors, multiplied
  229. * between themselves before dividing the rate.
  230. * tmp_qd goes from 1 to 31 and div is either 2 or 3.
  231. * In order to avoid testing twice the rate divisor (e.g. divisor 12 can
  232. * be found with (tmp_qd, div) = (2, 6) or (3, 4)), we remove any loop
  233. * for a rate divisor when div is 2 and tmp_qd is a multiple of 3.
  234. * We cannot inverse it (condition div is 3 and tmp_qd is even) or we
  235. * would miss some rate divisor that aren't reachable with div being 2
  236. * (e.g. rate divisor 90 is made with div = 3 and tmp_qd = 30, thus
  237. * tmp_qd is even so we skip it because we think div 2 could make this
  238. * rate divisor which isn't possible since tmp_qd has to be <= 31).
  239. */
  240. for (tmp_qd = 1; tmp_qd < AT91_PMC_AUDIO_PLL_QDPAD_EXTDIV_MAX; tmp_qd++)
  241. for (div = 2; div <= 3; div++) {
  242. if (div == 2 && tmp_qd % 3 == 0)
  243. continue;
  244. best_parent_rate = clk_hw_round_rate(pclk,
  245. rate * tmp_qd * div);
  246. tmp_rate = best_parent_rate / (div * tmp_qd);
  247. tmp_diff = abs(rate - tmp_rate);
  248. if (best_diff < 0 || best_diff > tmp_diff) {
  249. *parent_rate = best_parent_rate;
  250. best_rate = tmp_rate;
  251. best_diff = tmp_diff;
  252. }
  253. }
  254. pr_debug("A PLL/PAD: %s, best_rate = %ld, best_parent_rate = %lu\n",
  255. __func__, best_rate, best_parent_rate);
  256. return best_rate;
  257. }
  258. static long clk_audio_pll_pmc_round_rate(struct clk_hw *hw, unsigned long rate,
  259. unsigned long *parent_rate)
  260. {
  261. struct clk_hw *pclk = clk_hw_get_parent(hw);
  262. long best_rate = -EINVAL;
  263. unsigned long best_parent_rate = 0;
  264. u32 tmp_qd = 0, div;
  265. long tmp_rate;
  266. int tmp_diff;
  267. int best_diff = -1;
  268. pr_debug("A PLL/PMC: %s, rate = %lu (parent_rate = %lu)\n", __func__,
  269. rate, *parent_rate);
  270. if (!rate)
  271. return 0;
  272. best_parent_rate = clk_round_rate(pclk->clk, 1);
  273. div = max(best_parent_rate / rate, 1UL);
  274. for (; div <= AUDIO_PLL_QDPMC_MAX; div++) {
  275. best_parent_rate = clk_round_rate(pclk->clk, rate * div);
  276. tmp_rate = best_parent_rate / div;
  277. tmp_diff = abs(rate - tmp_rate);
  278. if (best_diff < 0 || best_diff > tmp_diff) {
  279. *parent_rate = best_parent_rate;
  280. best_rate = tmp_rate;
  281. best_diff = tmp_diff;
  282. tmp_qd = div;
  283. if (!best_diff)
  284. break; /* got exact match */
  285. }
  286. }
  287. pr_debug("A PLL/PMC: %s, best_rate = %ld, best_parent_rate = %lu (qd = %d)\n",
  288. __func__, best_rate, *parent_rate, tmp_qd - 1);
  289. return best_rate;
  290. }
  291. static int clk_audio_pll_frac_set_rate(struct clk_hw *hw, unsigned long rate,
  292. unsigned long parent_rate)
  293. {
  294. struct clk_audio_frac *frac = to_clk_audio_frac(hw);
  295. unsigned long fracr, nd;
  296. int ret;
  297. pr_debug("A PLL: %s, rate = %lu (parent_rate = %lu)\n", __func__, rate,
  298. parent_rate);
  299. if (rate < AUDIO_PLL_FOUT_MIN || rate > AUDIO_PLL_FOUT_MAX)
  300. return -EINVAL;
  301. ret = clk_audio_pll_frac_compute_frac(rate, parent_rate, &nd, &fracr);
  302. if (ret)
  303. return ret;
  304. frac->nd = nd;
  305. frac->fracr = fracr;
  306. return 0;
  307. }
  308. static int clk_audio_pll_pad_set_rate(struct clk_hw *hw, unsigned long rate,
  309. unsigned long parent_rate)
  310. {
  311. struct clk_audio_pad *apad_ck = to_clk_audio_pad(hw);
  312. u8 tmp_div;
  313. pr_debug("A PLL/PAD: %s, rate = %lu (parent_rate = %lu)\n", __func__,
  314. rate, parent_rate);
  315. if (!rate)
  316. return -EINVAL;
  317. tmp_div = parent_rate / rate;
  318. if (tmp_div % 3 == 0) {
  319. apad_ck->qdaudio = tmp_div / 3;
  320. apad_ck->div = 3;
  321. } else {
  322. apad_ck->qdaudio = tmp_div / 2;
  323. apad_ck->div = 2;
  324. }
  325. return 0;
  326. }
  327. static int clk_audio_pll_pmc_set_rate(struct clk_hw *hw, unsigned long rate,
  328. unsigned long parent_rate)
  329. {
  330. struct clk_audio_pmc *apmc_ck = to_clk_audio_pmc(hw);
  331. if (!rate)
  332. return -EINVAL;
  333. pr_debug("A PLL/PMC: %s, rate = %lu (parent_rate = %lu)\n", __func__,
  334. rate, parent_rate);
  335. apmc_ck->qdpmc = parent_rate / rate - 1;
  336. return 0;
  337. }
  338. static const struct clk_ops audio_pll_frac_ops = {
  339. .enable = clk_audio_pll_frac_enable,
  340. .disable = clk_audio_pll_frac_disable,
  341. .recalc_rate = clk_audio_pll_frac_recalc_rate,
  342. .determine_rate = clk_audio_pll_frac_determine_rate,
  343. .set_rate = clk_audio_pll_frac_set_rate,
  344. };
  345. static const struct clk_ops audio_pll_pad_ops = {
  346. .enable = clk_audio_pll_pad_enable,
  347. .disable = clk_audio_pll_pad_disable,
  348. .recalc_rate = clk_audio_pll_pad_recalc_rate,
  349. .round_rate = clk_audio_pll_pad_round_rate,
  350. .set_rate = clk_audio_pll_pad_set_rate,
  351. };
  352. static const struct clk_ops audio_pll_pmc_ops = {
  353. .enable = clk_audio_pll_pmc_enable,
  354. .disable = clk_audio_pll_pmc_disable,
  355. .recalc_rate = clk_audio_pll_pmc_recalc_rate,
  356. .round_rate = clk_audio_pll_pmc_round_rate,
  357. .set_rate = clk_audio_pll_pmc_set_rate,
  358. };
  359. struct clk_hw * __init
  360. at91_clk_register_audio_pll_frac(struct regmap *regmap, const char *name,
  361. const char *parent_name)
  362. {
  363. struct clk_audio_frac *frac_ck;
  364. struct clk_init_data init = {};
  365. int ret;
  366. frac_ck = kzalloc(sizeof(*frac_ck), GFP_KERNEL);
  367. if (!frac_ck)
  368. return ERR_PTR(-ENOMEM);
  369. init.name = name;
  370. init.ops = &audio_pll_frac_ops;
  371. init.parent_names = &parent_name;
  372. init.num_parents = 1;
  373. init.flags = CLK_SET_RATE_GATE;
  374. frac_ck->hw.init = &init;
  375. frac_ck->regmap = regmap;
  376. ret = clk_hw_register(NULL, &frac_ck->hw);
  377. if (ret) {
  378. kfree(frac_ck);
  379. return ERR_PTR(ret);
  380. }
  381. return &frac_ck->hw;
  382. }
  383. struct clk_hw * __init
  384. at91_clk_register_audio_pll_pad(struct regmap *regmap, const char *name,
  385. const char *parent_name)
  386. {
  387. struct clk_audio_pad *apad_ck;
  388. struct clk_init_data init;
  389. int ret;
  390. apad_ck = kzalloc(sizeof(*apad_ck), GFP_KERNEL);
  391. if (!apad_ck)
  392. return ERR_PTR(-ENOMEM);
  393. init.name = name;
  394. init.ops = &audio_pll_pad_ops;
  395. init.parent_names = &parent_name;
  396. init.num_parents = 1;
  397. init.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE |
  398. CLK_SET_RATE_PARENT;
  399. apad_ck->hw.init = &init;
  400. apad_ck->regmap = regmap;
  401. ret = clk_hw_register(NULL, &apad_ck->hw);
  402. if (ret) {
  403. kfree(apad_ck);
  404. return ERR_PTR(ret);
  405. }
  406. return &apad_ck->hw;
  407. }
  408. struct clk_hw * __init
  409. at91_clk_register_audio_pll_pmc(struct regmap *regmap, const char *name,
  410. const char *parent_name)
  411. {
  412. struct clk_audio_pmc *apmc_ck;
  413. struct clk_init_data init;
  414. int ret;
  415. apmc_ck = kzalloc(sizeof(*apmc_ck), GFP_KERNEL);
  416. if (!apmc_ck)
  417. return ERR_PTR(-ENOMEM);
  418. init.name = name;
  419. init.ops = &audio_pll_pmc_ops;
  420. init.parent_names = &parent_name;
  421. init.num_parents = 1;
  422. init.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE |
  423. CLK_SET_RATE_PARENT;
  424. apmc_ck->hw.init = &init;
  425. apmc_ck->regmap = regmap;
  426. ret = clk_hw_register(NULL, &apmc_ck->hw);
  427. if (ret) {
  428. kfree(apmc_ck);
  429. return ERR_PTR(ret);
  430. }
  431. return &apmc_ck->hw;
  432. }