at91sam9n12.c 6.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. #include <linux/clk-provider.h>
  3. #include <linux/mfd/syscon.h>
  4. #include <linux/slab.h>
  5. #include <dt-bindings/clock/at91.h>
  6. #include "pmc.h"
  7. static const struct clk_master_characteristics mck_characteristics = {
  8. .output = { .min = 0, .max = 133333333 },
  9. .divisors = { 1, 2, 4, 3 },
  10. .have_div3_pres = 1,
  11. };
  12. static u8 plla_out[] = { 0, 1, 2, 3, 0, 1, 2, 3 };
  13. static u16 plla_icpll[] = { 0, 0, 0, 0, 1, 1, 1, 1 };
  14. static const struct clk_range plla_outputs[] = {
  15. { .min = 745000000, .max = 800000000 },
  16. { .min = 695000000, .max = 750000000 },
  17. { .min = 645000000, .max = 700000000 },
  18. { .min = 595000000, .max = 650000000 },
  19. { .min = 545000000, .max = 600000000 },
  20. { .min = 495000000, .max = 555000000 },
  21. { .min = 445000000, .max = 500000000 },
  22. { .min = 400000000, .max = 450000000 },
  23. };
  24. static const struct clk_pll_characteristics plla_characteristics = {
  25. .input = { .min = 2000000, .max = 32000000 },
  26. .num_output = ARRAY_SIZE(plla_outputs),
  27. .output = plla_outputs,
  28. .icpll = plla_icpll,
  29. .out = plla_out,
  30. };
  31. static u8 pllb_out[] = { 0 };
  32. static const struct clk_range pllb_outputs[] = {
  33. { .min = 30000000, .max = 100000000 },
  34. };
  35. static const struct clk_pll_characteristics pllb_characteristics = {
  36. .input = { .min = 2000000, .max = 32000000 },
  37. .num_output = ARRAY_SIZE(pllb_outputs),
  38. .output = pllb_outputs,
  39. .out = pllb_out,
  40. };
  41. static const struct {
  42. char *n;
  43. char *p;
  44. u8 id;
  45. } at91sam9n12_systemck[] = {
  46. { .n = "ddrck", .p = "masterck", .id = 2 },
  47. { .n = "lcdck", .p = "masterck", .id = 3 },
  48. { .n = "uhpck", .p = "usbck", .id = 6 },
  49. { .n = "udpck", .p = "usbck", .id = 7 },
  50. { .n = "pck0", .p = "prog0", .id = 8 },
  51. { .n = "pck1", .p = "prog1", .id = 9 },
  52. };
  53. static const struct clk_pcr_layout at91sam9n12_pcr_layout = {
  54. .offset = 0x10c,
  55. .cmd = BIT(12),
  56. .pid_mask = GENMASK(5, 0),
  57. .div_mask = GENMASK(17, 16),
  58. };
  59. struct pck {
  60. char *n;
  61. u8 id;
  62. };
  63. static const struct pck at91sam9n12_periphck[] = {
  64. { .n = "pioAB_clk", .id = 2, },
  65. { .n = "pioCD_clk", .id = 3, },
  66. { .n = "fuse_clk", .id = 4, },
  67. { .n = "usart0_clk", .id = 5, },
  68. { .n = "usart1_clk", .id = 6, },
  69. { .n = "usart2_clk", .id = 7, },
  70. { .n = "usart3_clk", .id = 8, },
  71. { .n = "twi0_clk", .id = 9, },
  72. { .n = "twi1_clk", .id = 10, },
  73. { .n = "mci0_clk", .id = 12, },
  74. { .n = "spi0_clk", .id = 13, },
  75. { .n = "spi1_clk", .id = 14, },
  76. { .n = "uart0_clk", .id = 15, },
  77. { .n = "uart1_clk", .id = 16, },
  78. { .n = "tcb_clk", .id = 17, },
  79. { .n = "pwm_clk", .id = 18, },
  80. { .n = "adc_clk", .id = 19, },
  81. { .n = "dma0_clk", .id = 20, },
  82. { .n = "uhphs_clk", .id = 22, },
  83. { .n = "udphs_clk", .id = 23, },
  84. { .n = "lcdc_clk", .id = 25, },
  85. { .n = "sha_clk", .id = 27, },
  86. { .n = "ssc0_clk", .id = 28, },
  87. { .n = "aes_clk", .id = 29, },
  88. { .n = "trng_clk", .id = 30, },
  89. };
  90. static void __init at91sam9n12_pmc_setup(struct device_node *np)
  91. {
  92. struct clk_range range = CLK_RANGE(0, 0);
  93. const char *slck_name, *mainxtal_name;
  94. struct pmc_data *at91sam9n12_pmc;
  95. const char *parent_names[6];
  96. struct regmap *regmap;
  97. struct clk_hw *hw;
  98. int i;
  99. bool bypass;
  100. i = of_property_match_string(np, "clock-names", "slow_clk");
  101. if (i < 0)
  102. return;
  103. slck_name = of_clk_get_parent_name(np, i);
  104. i = of_property_match_string(np, "clock-names", "main_xtal");
  105. if (i < 0)
  106. return;
  107. mainxtal_name = of_clk_get_parent_name(np, i);
  108. regmap = device_node_to_regmap(np);
  109. if (IS_ERR(regmap))
  110. return;
  111. at91sam9n12_pmc = pmc_data_allocate(PMC_PLLBCK + 1,
  112. nck(at91sam9n12_systemck), 31, 0, 2);
  113. if (!at91sam9n12_pmc)
  114. return;
  115. hw = at91_clk_register_main_rc_osc(regmap, "main_rc_osc", 12000000,
  116. 50000000);
  117. if (IS_ERR(hw))
  118. goto err_free;
  119. bypass = of_property_read_bool(np, "atmel,osc-bypass");
  120. hw = at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name,
  121. bypass);
  122. if (IS_ERR(hw))
  123. goto err_free;
  124. parent_names[0] = "main_rc_osc";
  125. parent_names[1] = "main_osc";
  126. hw = at91_clk_register_sam9x5_main(regmap, "mainck", parent_names, 2);
  127. if (IS_ERR(hw))
  128. goto err_free;
  129. at91sam9n12_pmc->chws[PMC_MAIN] = hw;
  130. hw = at91_clk_register_pll(regmap, "pllack", "mainck", 0,
  131. &at91rm9200_pll_layout, &plla_characteristics);
  132. if (IS_ERR(hw))
  133. goto err_free;
  134. hw = at91_clk_register_plldiv(regmap, "plladivck", "pllack");
  135. if (IS_ERR(hw))
  136. goto err_free;
  137. at91sam9n12_pmc->chws[PMC_PLLACK] = hw;
  138. hw = at91_clk_register_pll(regmap, "pllbck", "mainck", 1,
  139. &at91rm9200_pll_layout, &pllb_characteristics);
  140. if (IS_ERR(hw))
  141. goto err_free;
  142. at91sam9n12_pmc->chws[PMC_PLLBCK] = hw;
  143. parent_names[0] = slck_name;
  144. parent_names[1] = "mainck";
  145. parent_names[2] = "plladivck";
  146. parent_names[3] = "pllbck";
  147. hw = at91_clk_register_master(regmap, "masterck", 4, parent_names,
  148. &at91sam9x5_master_layout,
  149. &mck_characteristics);
  150. if (IS_ERR(hw))
  151. goto err_free;
  152. at91sam9n12_pmc->chws[PMC_MCK] = hw;
  153. hw = at91sam9n12_clk_register_usb(regmap, "usbck", "pllbck");
  154. if (IS_ERR(hw))
  155. goto err_free;
  156. parent_names[0] = slck_name;
  157. parent_names[1] = "mainck";
  158. parent_names[2] = "plladivck";
  159. parent_names[3] = "pllbck";
  160. parent_names[4] = "masterck";
  161. for (i = 0; i < 2; i++) {
  162. char name[6];
  163. snprintf(name, sizeof(name), "prog%d", i);
  164. hw = at91_clk_register_programmable(regmap, name,
  165. parent_names, 5, i,
  166. &at91sam9x5_programmable_layout,
  167. NULL);
  168. if (IS_ERR(hw))
  169. goto err_free;
  170. at91sam9n12_pmc->pchws[i] = hw;
  171. }
  172. for (i = 0; i < ARRAY_SIZE(at91sam9n12_systemck); i++) {
  173. hw = at91_clk_register_system(regmap, at91sam9n12_systemck[i].n,
  174. at91sam9n12_systemck[i].p,
  175. at91sam9n12_systemck[i].id);
  176. if (IS_ERR(hw))
  177. goto err_free;
  178. at91sam9n12_pmc->shws[at91sam9n12_systemck[i].id] = hw;
  179. }
  180. for (i = 0; i < ARRAY_SIZE(at91sam9n12_periphck); i++) {
  181. hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock,
  182. &at91sam9n12_pcr_layout,
  183. at91sam9n12_periphck[i].n,
  184. "masterck",
  185. at91sam9n12_periphck[i].id,
  186. &range, INT_MIN);
  187. if (IS_ERR(hw))
  188. goto err_free;
  189. at91sam9n12_pmc->phws[at91sam9n12_periphck[i].id] = hw;
  190. }
  191. of_clk_add_hw_provider(np, of_clk_hw_pmc_get, at91sam9n12_pmc);
  192. return;
  193. err_free:
  194. kfree(at91sam9n12_pmc);
  195. }
  196. /*
  197. * The TCB is used as the clocksource so its clock is needed early. This means
  198. * this can't be a platform driver.
  199. */
  200. CLK_OF_DECLARE_DRIVER(at91sam9n12_pmc, "atmel,at91sam9n12-pmc",
  201. at91sam9n12_pmc_setup);