synclink_cs.c 108 KB

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  1. /*
  2. * linux/drivers/char/pcmcia/synclink_cs.c
  3. *
  4. * $Id: synclink_cs.c,v 4.34 2005/09/08 13:20:54 paulkf Exp $
  5. *
  6. * Device driver for Microgate SyncLink PC Card
  7. * multiprotocol serial adapter.
  8. *
  9. * written by Paul Fulghum for Microgate Corporation
  10. * paulkf@microgate.com
  11. *
  12. * Microgate and SyncLink are trademarks of Microgate Corporation
  13. *
  14. * This code is released under the GNU General Public License (GPL)
  15. *
  16. * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  17. * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  18. * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  19. * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
  20. * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  21. * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  22. * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  23. * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  24. * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  25. * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
  26. * OF THE POSSIBILITY OF SUCH DAMAGE.
  27. */
  28. #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq))
  29. #if defined(__i386__)
  30. # define BREAKPOINT() asm(" int $3");
  31. #else
  32. # define BREAKPOINT() { }
  33. #endif
  34. #define MAX_DEVICE_COUNT 4
  35. #include <linux/module.h>
  36. #include <linux/errno.h>
  37. #include <linux/signal.h>
  38. #include <linux/sched.h>
  39. #include <linux/timer.h>
  40. #include <linux/time.h>
  41. #include <linux/interrupt.h>
  42. #include <linux/tty.h>
  43. #include <linux/tty_flip.h>
  44. #include <linux/serial.h>
  45. #include <linux/major.h>
  46. #include <linux/string.h>
  47. #include <linux/fcntl.h>
  48. #include <linux/ptrace.h>
  49. #include <linux/ioport.h>
  50. #include <linux/mm.h>
  51. #include <linux/seq_file.h>
  52. #include <linux/slab.h>
  53. #include <linux/netdevice.h>
  54. #include <linux/vmalloc.h>
  55. #include <linux/init.h>
  56. #include <linux/delay.h>
  57. #include <linux/ioctl.h>
  58. #include <linux/synclink.h>
  59. #include <asm/io.h>
  60. #include <asm/irq.h>
  61. #include <asm/dma.h>
  62. #include <linux/bitops.h>
  63. #include <asm/types.h>
  64. #include <linux/termios.h>
  65. #include <linux/workqueue.h>
  66. #include <linux/hdlc.h>
  67. #include <pcmcia/cistpl.h>
  68. #include <pcmcia/cisreg.h>
  69. #include <pcmcia/ds.h>
  70. #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINK_CS_MODULE))
  71. #define SYNCLINK_GENERIC_HDLC 1
  72. #else
  73. #define SYNCLINK_GENERIC_HDLC 0
  74. #endif
  75. #define GET_USER(error,value,addr) error = get_user(value,addr)
  76. #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0
  77. #define PUT_USER(error,value,addr) error = put_user(value,addr)
  78. #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0
  79. #include <linux/uaccess.h>
  80. static MGSL_PARAMS default_params = {
  81. MGSL_MODE_HDLC, /* unsigned long mode */
  82. 0, /* unsigned char loopback; */
  83. HDLC_FLAG_UNDERRUN_ABORT15, /* unsigned short flags; */
  84. HDLC_ENCODING_NRZI_SPACE, /* unsigned char encoding; */
  85. 0, /* unsigned long clock_speed; */
  86. 0xff, /* unsigned char addr_filter; */
  87. HDLC_CRC_16_CCITT, /* unsigned short crc_type; */
  88. HDLC_PREAMBLE_LENGTH_8BITS, /* unsigned char preamble_length; */
  89. HDLC_PREAMBLE_PATTERN_NONE, /* unsigned char preamble; */
  90. 9600, /* unsigned long data_rate; */
  91. 8, /* unsigned char data_bits; */
  92. 1, /* unsigned char stop_bits; */
  93. ASYNC_PARITY_NONE /* unsigned char parity; */
  94. };
  95. typedef struct {
  96. int count;
  97. unsigned char status;
  98. char data[1];
  99. } RXBUF;
  100. /* The queue of BH actions to be performed */
  101. #define BH_RECEIVE 1
  102. #define BH_TRANSMIT 2
  103. #define BH_STATUS 4
  104. #define IO_PIN_SHUTDOWN_LIMIT 100
  105. #define RELEVANT_IFLAG(iflag) (iflag & (IGNBRK|BRKINT|IGNPAR|PARMRK|INPCK))
  106. struct _input_signal_events {
  107. int ri_up;
  108. int ri_down;
  109. int dsr_up;
  110. int dsr_down;
  111. int dcd_up;
  112. int dcd_down;
  113. int cts_up;
  114. int cts_down;
  115. };
  116. /*
  117. * Device instance data structure
  118. */
  119. typedef struct _mgslpc_info {
  120. struct tty_port port;
  121. void *if_ptr; /* General purpose pointer (used by SPPP) */
  122. int magic;
  123. int line;
  124. struct mgsl_icount icount;
  125. int timeout;
  126. int x_char; /* xon/xoff character */
  127. unsigned char read_status_mask;
  128. unsigned char ignore_status_mask;
  129. unsigned char *tx_buf;
  130. int tx_put;
  131. int tx_get;
  132. int tx_count;
  133. /* circular list of fixed length rx buffers */
  134. unsigned char *rx_buf; /* memory allocated for all rx buffers */
  135. int rx_buf_total_size; /* size of memory allocated for rx buffers */
  136. int rx_put; /* index of next empty rx buffer */
  137. int rx_get; /* index of next full rx buffer */
  138. int rx_buf_size; /* size in bytes of single rx buffer */
  139. int rx_buf_count; /* total number of rx buffers */
  140. int rx_frame_count; /* number of full rx buffers */
  141. wait_queue_head_t status_event_wait_q;
  142. wait_queue_head_t event_wait_q;
  143. struct timer_list tx_timer; /* HDLC transmit timeout timer */
  144. struct _mgslpc_info *next_device; /* device list link */
  145. unsigned short imra_value;
  146. unsigned short imrb_value;
  147. unsigned char pim_value;
  148. spinlock_t lock;
  149. struct work_struct task; /* task structure for scheduling bh */
  150. u32 max_frame_size;
  151. u32 pending_bh;
  152. bool bh_running;
  153. bool bh_requested;
  154. int dcd_chkcount; /* check counts to prevent */
  155. int cts_chkcount; /* too many IRQs if a signal */
  156. int dsr_chkcount; /* is floating */
  157. int ri_chkcount;
  158. bool rx_enabled;
  159. bool rx_overflow;
  160. bool tx_enabled;
  161. bool tx_active;
  162. bool tx_aborting;
  163. u32 idle_mode;
  164. int if_mode; /* serial interface selection (RS-232, v.35 etc) */
  165. char device_name[25]; /* device instance name */
  166. unsigned int io_base; /* base I/O address of adapter */
  167. unsigned int irq_level;
  168. MGSL_PARAMS params; /* communications parameters */
  169. unsigned char serial_signals; /* current serial signal states */
  170. bool irq_occurred; /* for diagnostics use */
  171. char testing_irq;
  172. unsigned int init_error; /* startup error (DIAGS) */
  173. char *flag_buf;
  174. bool drop_rts_on_tx_done;
  175. struct _input_signal_events input_signal_events;
  176. /* PCMCIA support */
  177. struct pcmcia_device *p_dev;
  178. int stop;
  179. /* SPPP/Cisco HDLC device parts */
  180. int netcount;
  181. spinlock_t netlock;
  182. #if SYNCLINK_GENERIC_HDLC
  183. struct net_device *netdev;
  184. #endif
  185. } MGSLPC_INFO;
  186. #define MGSLPC_MAGIC 0x5402
  187. /*
  188. * The size of the serial xmit buffer is 1 page, or 4096 bytes
  189. */
  190. #define TXBUFSIZE 4096
  191. #define CHA 0x00 /* channel A offset */
  192. #define CHB 0x40 /* channel B offset */
  193. /*
  194. * FIXME: PPC has PVR defined in asm/reg.h. For now we just undef it.
  195. */
  196. #undef PVR
  197. #define RXFIFO 0
  198. #define TXFIFO 0
  199. #define STAR 0x20
  200. #define CMDR 0x20
  201. #define RSTA 0x21
  202. #define PRE 0x21
  203. #define MODE 0x22
  204. #define TIMR 0x23
  205. #define XAD1 0x24
  206. #define XAD2 0x25
  207. #define RAH1 0x26
  208. #define RAH2 0x27
  209. #define DAFO 0x27
  210. #define RAL1 0x28
  211. #define RFC 0x28
  212. #define RHCR 0x29
  213. #define RAL2 0x29
  214. #define RBCL 0x2a
  215. #define XBCL 0x2a
  216. #define RBCH 0x2b
  217. #define XBCH 0x2b
  218. #define CCR0 0x2c
  219. #define CCR1 0x2d
  220. #define CCR2 0x2e
  221. #define CCR3 0x2f
  222. #define VSTR 0x34
  223. #define BGR 0x34
  224. #define RLCR 0x35
  225. #define AML 0x36
  226. #define AMH 0x37
  227. #define GIS 0x38
  228. #define IVA 0x38
  229. #define IPC 0x39
  230. #define ISR 0x3a
  231. #define IMR 0x3a
  232. #define PVR 0x3c
  233. #define PIS 0x3d
  234. #define PIM 0x3d
  235. #define PCR 0x3e
  236. #define CCR4 0x3f
  237. // IMR/ISR
  238. #define IRQ_BREAK_ON BIT15 // rx break detected
  239. #define IRQ_DATAOVERRUN BIT14 // receive data overflow
  240. #define IRQ_ALLSENT BIT13 // all sent
  241. #define IRQ_UNDERRUN BIT12 // transmit data underrun
  242. #define IRQ_TIMER BIT11 // timer interrupt
  243. #define IRQ_CTS BIT10 // CTS status change
  244. #define IRQ_TXREPEAT BIT9 // tx message repeat
  245. #define IRQ_TXFIFO BIT8 // transmit pool ready
  246. #define IRQ_RXEOM BIT7 // receive message end
  247. #define IRQ_EXITHUNT BIT6 // receive frame start
  248. #define IRQ_RXTIME BIT6 // rx char timeout
  249. #define IRQ_DCD BIT2 // carrier detect status change
  250. #define IRQ_OVERRUN BIT1 // receive frame overflow
  251. #define IRQ_RXFIFO BIT0 // receive pool full
  252. // STAR
  253. #define XFW BIT6 // transmit FIFO write enable
  254. #define CEC BIT2 // command executing
  255. #define CTS BIT1 // CTS state
  256. #define PVR_DTR BIT0
  257. #define PVR_DSR BIT1
  258. #define PVR_RI BIT2
  259. #define PVR_AUTOCTS BIT3
  260. #define PVR_RS232 0x20 /* 0010b */
  261. #define PVR_V35 0xe0 /* 1110b */
  262. #define PVR_RS422 0x40 /* 0100b */
  263. /* Register access functions */
  264. #define write_reg(info, reg, val) outb((val),(info)->io_base + (reg))
  265. #define read_reg(info, reg) inb((info)->io_base + (reg))
  266. #define read_reg16(info, reg) inw((info)->io_base + (reg))
  267. #define write_reg16(info, reg, val) outw((val), (info)->io_base + (reg))
  268. #define set_reg_bits(info, reg, mask) \
  269. write_reg(info, (reg), \
  270. (unsigned char) (read_reg(info, (reg)) | (mask)))
  271. #define clear_reg_bits(info, reg, mask) \
  272. write_reg(info, (reg), \
  273. (unsigned char) (read_reg(info, (reg)) & ~(mask)))
  274. /*
  275. * interrupt enable/disable routines
  276. */
  277. static void irq_disable(MGSLPC_INFO *info, unsigned char channel, unsigned short mask)
  278. {
  279. if (channel == CHA) {
  280. info->imra_value |= mask;
  281. write_reg16(info, CHA + IMR, info->imra_value);
  282. } else {
  283. info->imrb_value |= mask;
  284. write_reg16(info, CHB + IMR, info->imrb_value);
  285. }
  286. }
  287. static void irq_enable(MGSLPC_INFO *info, unsigned char channel, unsigned short mask)
  288. {
  289. if (channel == CHA) {
  290. info->imra_value &= ~mask;
  291. write_reg16(info, CHA + IMR, info->imra_value);
  292. } else {
  293. info->imrb_value &= ~mask;
  294. write_reg16(info, CHB + IMR, info->imrb_value);
  295. }
  296. }
  297. #define port_irq_disable(info, mask) \
  298. { info->pim_value |= (mask); write_reg(info, PIM, info->pim_value); }
  299. #define port_irq_enable(info, mask) \
  300. { info->pim_value &= ~(mask); write_reg(info, PIM, info->pim_value); }
  301. static void rx_start(MGSLPC_INFO *info);
  302. static void rx_stop(MGSLPC_INFO *info);
  303. static void tx_start(MGSLPC_INFO *info, struct tty_struct *tty);
  304. static void tx_stop(MGSLPC_INFO *info);
  305. static void tx_set_idle(MGSLPC_INFO *info);
  306. static void get_signals(MGSLPC_INFO *info);
  307. static void set_signals(MGSLPC_INFO *info);
  308. static void reset_device(MGSLPC_INFO *info);
  309. static void hdlc_mode(MGSLPC_INFO *info);
  310. static void async_mode(MGSLPC_INFO *info);
  311. static void tx_timeout(struct timer_list *t);
  312. static int carrier_raised(struct tty_port *port);
  313. static void dtr_rts(struct tty_port *port, int onoff);
  314. #if SYNCLINK_GENERIC_HDLC
  315. #define dev_to_port(D) (dev_to_hdlc(D)->priv)
  316. static void hdlcdev_tx_done(MGSLPC_INFO *info);
  317. static void hdlcdev_rx(MGSLPC_INFO *info, char *buf, int size);
  318. static int hdlcdev_init(MGSLPC_INFO *info);
  319. static void hdlcdev_exit(MGSLPC_INFO *info);
  320. #endif
  321. static void trace_block(MGSLPC_INFO *info,const char* data, int count, int xmit);
  322. static bool register_test(MGSLPC_INFO *info);
  323. static bool irq_test(MGSLPC_INFO *info);
  324. static int adapter_test(MGSLPC_INFO *info);
  325. static int claim_resources(MGSLPC_INFO *info);
  326. static void release_resources(MGSLPC_INFO *info);
  327. static int mgslpc_add_device(MGSLPC_INFO *info);
  328. static void mgslpc_remove_device(MGSLPC_INFO *info);
  329. static bool rx_get_frame(MGSLPC_INFO *info, struct tty_struct *tty);
  330. static void rx_reset_buffers(MGSLPC_INFO *info);
  331. static int rx_alloc_buffers(MGSLPC_INFO *info);
  332. static void rx_free_buffers(MGSLPC_INFO *info);
  333. static irqreturn_t mgslpc_isr(int irq, void *dev_id);
  334. /*
  335. * Bottom half interrupt handlers
  336. */
  337. static void bh_handler(struct work_struct *work);
  338. static void bh_transmit(MGSLPC_INFO *info, struct tty_struct *tty);
  339. static void bh_status(MGSLPC_INFO *info);
  340. /*
  341. * ioctl handlers
  342. */
  343. static int tiocmget(struct tty_struct *tty);
  344. static int tiocmset(struct tty_struct *tty,
  345. unsigned int set, unsigned int clear);
  346. static int get_stats(MGSLPC_INFO *info, struct mgsl_icount __user *user_icount);
  347. static int get_params(MGSLPC_INFO *info, MGSL_PARAMS __user *user_params);
  348. static int set_params(MGSLPC_INFO *info, MGSL_PARAMS __user *new_params, struct tty_struct *tty);
  349. static int get_txidle(MGSLPC_INFO *info, int __user *idle_mode);
  350. static int set_txidle(MGSLPC_INFO *info, int idle_mode);
  351. static int set_txenable(MGSLPC_INFO *info, int enable, struct tty_struct *tty);
  352. static int tx_abort(MGSLPC_INFO *info);
  353. static int set_rxenable(MGSLPC_INFO *info, int enable);
  354. static int wait_events(MGSLPC_INFO *info, int __user *mask);
  355. static MGSLPC_INFO *mgslpc_device_list = NULL;
  356. static int mgslpc_device_count = 0;
  357. /*
  358. * Set this param to non-zero to load eax with the
  359. * .text section address and breakpoint on module load.
  360. * This is useful for use with gdb and add-symbol-file command.
  361. */
  362. static bool break_on_load;
  363. /*
  364. * Driver major number, defaults to zero to get auto
  365. * assigned major number. May be forced as module parameter.
  366. */
  367. static int ttymajor=0;
  368. static int debug_level = 0;
  369. static int maxframe[MAX_DEVICE_COUNT] = {0,};
  370. module_param(break_on_load, bool, 0);
  371. module_param(ttymajor, int, 0);
  372. module_param(debug_level, int, 0);
  373. module_param_array(maxframe, int, NULL, 0);
  374. MODULE_LICENSE("GPL");
  375. static char *driver_name = "SyncLink PC Card driver";
  376. static char *driver_version = "$Revision: 4.34 $";
  377. static struct tty_driver *serial_driver;
  378. /* number of characters left in xmit buffer before we ask for more */
  379. #define WAKEUP_CHARS 256
  380. static void mgslpc_change_params(MGSLPC_INFO *info, struct tty_struct *tty);
  381. static void mgslpc_wait_until_sent(struct tty_struct *tty, int timeout);
  382. /* PCMCIA prototypes */
  383. static int mgslpc_config(struct pcmcia_device *link);
  384. static void mgslpc_release(u_long arg);
  385. static void mgslpc_detach(struct pcmcia_device *p_dev);
  386. /*
  387. * 1st function defined in .text section. Calling this function in
  388. * init_module() followed by a breakpoint allows a remote debugger
  389. * (gdb) to get the .text address for the add-symbol-file command.
  390. * This allows remote debugging of dynamically loadable modules.
  391. */
  392. static void* mgslpc_get_text_ptr(void)
  393. {
  394. return mgslpc_get_text_ptr;
  395. }
  396. /**
  397. * line discipline callback wrappers
  398. *
  399. * The wrappers maintain line discipline references
  400. * while calling into the line discipline.
  401. *
  402. * ldisc_receive_buf - pass receive data to line discipline
  403. */
  404. static void ldisc_receive_buf(struct tty_struct *tty,
  405. const __u8 *data, char *flags, int count)
  406. {
  407. struct tty_ldisc *ld;
  408. if (!tty)
  409. return;
  410. ld = tty_ldisc_ref(tty);
  411. if (ld) {
  412. if (ld->ops->receive_buf)
  413. ld->ops->receive_buf(tty, data, flags, count);
  414. tty_ldisc_deref(ld);
  415. }
  416. }
  417. static const struct tty_port_operations mgslpc_port_ops = {
  418. .carrier_raised = carrier_raised,
  419. .dtr_rts = dtr_rts
  420. };
  421. static int mgslpc_probe(struct pcmcia_device *link)
  422. {
  423. MGSLPC_INFO *info;
  424. int ret;
  425. if (debug_level >= DEBUG_LEVEL_INFO)
  426. printk("mgslpc_attach\n");
  427. info = kzalloc(sizeof(MGSLPC_INFO), GFP_KERNEL);
  428. if (!info) {
  429. printk("Error can't allocate device instance data\n");
  430. return -ENOMEM;
  431. }
  432. info->magic = MGSLPC_MAGIC;
  433. tty_port_init(&info->port);
  434. info->port.ops = &mgslpc_port_ops;
  435. INIT_WORK(&info->task, bh_handler);
  436. info->max_frame_size = 4096;
  437. info->port.close_delay = 5*HZ/10;
  438. info->port.closing_wait = 30*HZ;
  439. init_waitqueue_head(&info->status_event_wait_q);
  440. init_waitqueue_head(&info->event_wait_q);
  441. spin_lock_init(&info->lock);
  442. spin_lock_init(&info->netlock);
  443. memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
  444. info->idle_mode = HDLC_TXIDLE_FLAGS;
  445. info->imra_value = 0xffff;
  446. info->imrb_value = 0xffff;
  447. info->pim_value = 0xff;
  448. info->p_dev = link;
  449. link->priv = info;
  450. /* Initialize the struct pcmcia_device structure */
  451. ret = mgslpc_config(link);
  452. if (ret != 0)
  453. goto failed;
  454. ret = mgslpc_add_device(info);
  455. if (ret != 0)
  456. goto failed_release;
  457. return 0;
  458. failed_release:
  459. mgslpc_release((u_long)link);
  460. failed:
  461. tty_port_destroy(&info->port);
  462. kfree(info);
  463. return ret;
  464. }
  465. /* Card has been inserted.
  466. */
  467. static int mgslpc_ioprobe(struct pcmcia_device *p_dev, void *priv_data)
  468. {
  469. return pcmcia_request_io(p_dev);
  470. }
  471. static int mgslpc_config(struct pcmcia_device *link)
  472. {
  473. MGSLPC_INFO *info = link->priv;
  474. int ret;
  475. if (debug_level >= DEBUG_LEVEL_INFO)
  476. printk("mgslpc_config(0x%p)\n", link);
  477. link->config_flags |= CONF_ENABLE_IRQ | CONF_AUTO_SET_IO;
  478. ret = pcmcia_loop_config(link, mgslpc_ioprobe, NULL);
  479. if (ret != 0)
  480. goto failed;
  481. link->config_index = 8;
  482. link->config_regs = PRESENT_OPTION;
  483. ret = pcmcia_request_irq(link, mgslpc_isr);
  484. if (ret)
  485. goto failed;
  486. ret = pcmcia_enable_device(link);
  487. if (ret)
  488. goto failed;
  489. info->io_base = link->resource[0]->start;
  490. info->irq_level = link->irq;
  491. return 0;
  492. failed:
  493. mgslpc_release((u_long)link);
  494. return -ENODEV;
  495. }
  496. /* Card has been removed.
  497. * Unregister device and release PCMCIA configuration.
  498. * If device is open, postpone until it is closed.
  499. */
  500. static void mgslpc_release(u_long arg)
  501. {
  502. struct pcmcia_device *link = (struct pcmcia_device *)arg;
  503. if (debug_level >= DEBUG_LEVEL_INFO)
  504. printk("mgslpc_release(0x%p)\n", link);
  505. pcmcia_disable_device(link);
  506. }
  507. static void mgslpc_detach(struct pcmcia_device *link)
  508. {
  509. if (debug_level >= DEBUG_LEVEL_INFO)
  510. printk("mgslpc_detach(0x%p)\n", link);
  511. ((MGSLPC_INFO *)link->priv)->stop = 1;
  512. mgslpc_release((u_long)link);
  513. mgslpc_remove_device((MGSLPC_INFO *)link->priv);
  514. }
  515. static int mgslpc_suspend(struct pcmcia_device *link)
  516. {
  517. MGSLPC_INFO *info = link->priv;
  518. info->stop = 1;
  519. return 0;
  520. }
  521. static int mgslpc_resume(struct pcmcia_device *link)
  522. {
  523. MGSLPC_INFO *info = link->priv;
  524. info->stop = 0;
  525. return 0;
  526. }
  527. static inline bool mgslpc_paranoia_check(MGSLPC_INFO *info,
  528. char *name, const char *routine)
  529. {
  530. #ifdef MGSLPC_PARANOIA_CHECK
  531. static const char *badmagic =
  532. "Warning: bad magic number for mgsl struct (%s) in %s\n";
  533. static const char *badinfo =
  534. "Warning: null mgslpc_info for (%s) in %s\n";
  535. if (!info) {
  536. printk(badinfo, name, routine);
  537. return true;
  538. }
  539. if (info->magic != MGSLPC_MAGIC) {
  540. printk(badmagic, name, routine);
  541. return true;
  542. }
  543. #else
  544. if (!info)
  545. return true;
  546. #endif
  547. return false;
  548. }
  549. #define CMD_RXFIFO BIT7 // release current rx FIFO
  550. #define CMD_RXRESET BIT6 // receiver reset
  551. #define CMD_RXFIFO_READ BIT5
  552. #define CMD_START_TIMER BIT4
  553. #define CMD_TXFIFO BIT3 // release current tx FIFO
  554. #define CMD_TXEOM BIT1 // transmit end message
  555. #define CMD_TXRESET BIT0 // transmit reset
  556. static bool wait_command_complete(MGSLPC_INFO *info, unsigned char channel)
  557. {
  558. int i = 0;
  559. /* wait for command completion */
  560. while (read_reg(info, (unsigned char)(channel+STAR)) & BIT2) {
  561. udelay(1);
  562. if (i++ == 1000)
  563. return false;
  564. }
  565. return true;
  566. }
  567. static void issue_command(MGSLPC_INFO *info, unsigned char channel, unsigned char cmd)
  568. {
  569. wait_command_complete(info, channel);
  570. write_reg(info, (unsigned char) (channel + CMDR), cmd);
  571. }
  572. static void tx_pause(struct tty_struct *tty)
  573. {
  574. MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
  575. unsigned long flags;
  576. if (mgslpc_paranoia_check(info, tty->name, "tx_pause"))
  577. return;
  578. if (debug_level >= DEBUG_LEVEL_INFO)
  579. printk("tx_pause(%s)\n", info->device_name);
  580. spin_lock_irqsave(&info->lock, flags);
  581. if (info->tx_enabled)
  582. tx_stop(info);
  583. spin_unlock_irqrestore(&info->lock, flags);
  584. }
  585. static void tx_release(struct tty_struct *tty)
  586. {
  587. MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
  588. unsigned long flags;
  589. if (mgslpc_paranoia_check(info, tty->name, "tx_release"))
  590. return;
  591. if (debug_level >= DEBUG_LEVEL_INFO)
  592. printk("tx_release(%s)\n", info->device_name);
  593. spin_lock_irqsave(&info->lock, flags);
  594. if (!info->tx_enabled)
  595. tx_start(info, tty);
  596. spin_unlock_irqrestore(&info->lock, flags);
  597. }
  598. /* Return next bottom half action to perform.
  599. * or 0 if nothing to do.
  600. */
  601. static int bh_action(MGSLPC_INFO *info)
  602. {
  603. unsigned long flags;
  604. int rc = 0;
  605. spin_lock_irqsave(&info->lock, flags);
  606. if (info->pending_bh & BH_RECEIVE) {
  607. info->pending_bh &= ~BH_RECEIVE;
  608. rc = BH_RECEIVE;
  609. } else if (info->pending_bh & BH_TRANSMIT) {
  610. info->pending_bh &= ~BH_TRANSMIT;
  611. rc = BH_TRANSMIT;
  612. } else if (info->pending_bh & BH_STATUS) {
  613. info->pending_bh &= ~BH_STATUS;
  614. rc = BH_STATUS;
  615. }
  616. if (!rc) {
  617. /* Mark BH routine as complete */
  618. info->bh_running = false;
  619. info->bh_requested = false;
  620. }
  621. spin_unlock_irqrestore(&info->lock, flags);
  622. return rc;
  623. }
  624. static void bh_handler(struct work_struct *work)
  625. {
  626. MGSLPC_INFO *info = container_of(work, MGSLPC_INFO, task);
  627. struct tty_struct *tty;
  628. int action;
  629. if (debug_level >= DEBUG_LEVEL_BH)
  630. printk("%s(%d):bh_handler(%s) entry\n",
  631. __FILE__,__LINE__,info->device_name);
  632. info->bh_running = true;
  633. tty = tty_port_tty_get(&info->port);
  634. while((action = bh_action(info)) != 0) {
  635. /* Process work item */
  636. if (debug_level >= DEBUG_LEVEL_BH)
  637. printk("%s(%d):bh_handler() work item action=%d\n",
  638. __FILE__,__LINE__,action);
  639. switch (action) {
  640. case BH_RECEIVE:
  641. while(rx_get_frame(info, tty));
  642. break;
  643. case BH_TRANSMIT:
  644. bh_transmit(info, tty);
  645. break;
  646. case BH_STATUS:
  647. bh_status(info);
  648. break;
  649. default:
  650. /* unknown work item ID */
  651. printk("Unknown work item ID=%08X!\n", action);
  652. break;
  653. }
  654. }
  655. tty_kref_put(tty);
  656. if (debug_level >= DEBUG_LEVEL_BH)
  657. printk("%s(%d):bh_handler(%s) exit\n",
  658. __FILE__,__LINE__,info->device_name);
  659. }
  660. static void bh_transmit(MGSLPC_INFO *info, struct tty_struct *tty)
  661. {
  662. if (debug_level >= DEBUG_LEVEL_BH)
  663. printk("bh_transmit() entry on %s\n", info->device_name);
  664. if (tty)
  665. tty_wakeup(tty);
  666. }
  667. static void bh_status(MGSLPC_INFO *info)
  668. {
  669. info->ri_chkcount = 0;
  670. info->dsr_chkcount = 0;
  671. info->dcd_chkcount = 0;
  672. info->cts_chkcount = 0;
  673. }
  674. /* eom: non-zero = end of frame */
  675. static void rx_ready_hdlc(MGSLPC_INFO *info, int eom)
  676. {
  677. unsigned char data[2];
  678. unsigned char fifo_count, read_count, i;
  679. RXBUF *buf = (RXBUF*)(info->rx_buf + (info->rx_put * info->rx_buf_size));
  680. if (debug_level >= DEBUG_LEVEL_ISR)
  681. printk("%s(%d):rx_ready_hdlc(eom=%d)\n", __FILE__, __LINE__, eom);
  682. if (!info->rx_enabled)
  683. return;
  684. if (info->rx_frame_count >= info->rx_buf_count) {
  685. /* no more free buffers */
  686. issue_command(info, CHA, CMD_RXRESET);
  687. info->pending_bh |= BH_RECEIVE;
  688. info->rx_overflow = true;
  689. info->icount.buf_overrun++;
  690. return;
  691. }
  692. if (eom) {
  693. /* end of frame, get FIFO count from RBCL register */
  694. fifo_count = (unsigned char)(read_reg(info, CHA+RBCL) & 0x1f);
  695. if (fifo_count == 0)
  696. fifo_count = 32;
  697. } else
  698. fifo_count = 32;
  699. do {
  700. if (fifo_count == 1) {
  701. read_count = 1;
  702. data[0] = read_reg(info, CHA + RXFIFO);
  703. } else {
  704. read_count = 2;
  705. *((unsigned short *) data) = read_reg16(info, CHA + RXFIFO);
  706. }
  707. fifo_count -= read_count;
  708. if (!fifo_count && eom)
  709. buf->status = data[--read_count];
  710. for (i = 0; i < read_count; i++) {
  711. if (buf->count >= info->max_frame_size) {
  712. /* frame too large, reset receiver and reset current buffer */
  713. issue_command(info, CHA, CMD_RXRESET);
  714. buf->count = 0;
  715. return;
  716. }
  717. *(buf->data + buf->count) = data[i];
  718. buf->count++;
  719. }
  720. } while (fifo_count);
  721. if (eom) {
  722. info->pending_bh |= BH_RECEIVE;
  723. info->rx_frame_count++;
  724. info->rx_put++;
  725. if (info->rx_put >= info->rx_buf_count)
  726. info->rx_put = 0;
  727. }
  728. issue_command(info, CHA, CMD_RXFIFO);
  729. }
  730. static void rx_ready_async(MGSLPC_INFO *info, int tcd)
  731. {
  732. struct tty_port *port = &info->port;
  733. unsigned char data, status, flag;
  734. int fifo_count;
  735. int work = 0;
  736. struct mgsl_icount *icount = &info->icount;
  737. if (tcd) {
  738. /* early termination, get FIFO count from RBCL register */
  739. fifo_count = (unsigned char)(read_reg(info, CHA+RBCL) & 0x1f);
  740. /* Zero fifo count could mean 0 or 32 bytes available.
  741. * If BIT5 of STAR is set then at least 1 byte is available.
  742. */
  743. if (!fifo_count && (read_reg(info,CHA+STAR) & BIT5))
  744. fifo_count = 32;
  745. } else
  746. fifo_count = 32;
  747. tty_buffer_request_room(port, fifo_count);
  748. /* Flush received async data to receive data buffer. */
  749. while (fifo_count) {
  750. data = read_reg(info, CHA + RXFIFO);
  751. status = read_reg(info, CHA + RXFIFO);
  752. fifo_count -= 2;
  753. icount->rx++;
  754. flag = TTY_NORMAL;
  755. // if no frameing/crc error then save data
  756. // BIT7:parity error
  757. // BIT6:framing error
  758. if (status & (BIT7 + BIT6)) {
  759. if (status & BIT7)
  760. icount->parity++;
  761. else
  762. icount->frame++;
  763. /* discard char if tty control flags say so */
  764. if (status & info->ignore_status_mask)
  765. continue;
  766. status &= info->read_status_mask;
  767. if (status & BIT7)
  768. flag = TTY_PARITY;
  769. else if (status & BIT6)
  770. flag = TTY_FRAME;
  771. }
  772. work += tty_insert_flip_char(port, data, flag);
  773. }
  774. issue_command(info, CHA, CMD_RXFIFO);
  775. if (debug_level >= DEBUG_LEVEL_ISR) {
  776. printk("%s(%d):rx_ready_async",
  777. __FILE__,__LINE__);
  778. printk("%s(%d):rx=%d brk=%d parity=%d frame=%d overrun=%d\n",
  779. __FILE__,__LINE__,icount->rx,icount->brk,
  780. icount->parity,icount->frame,icount->overrun);
  781. }
  782. if (work)
  783. tty_flip_buffer_push(port);
  784. }
  785. static void tx_done(MGSLPC_INFO *info, struct tty_struct *tty)
  786. {
  787. if (!info->tx_active)
  788. return;
  789. info->tx_active = false;
  790. info->tx_aborting = false;
  791. if (info->params.mode == MGSL_MODE_ASYNC)
  792. return;
  793. info->tx_count = info->tx_put = info->tx_get = 0;
  794. del_timer(&info->tx_timer);
  795. if (info->drop_rts_on_tx_done) {
  796. get_signals(info);
  797. if (info->serial_signals & SerialSignal_RTS) {
  798. info->serial_signals &= ~SerialSignal_RTS;
  799. set_signals(info);
  800. }
  801. info->drop_rts_on_tx_done = false;
  802. }
  803. #if SYNCLINK_GENERIC_HDLC
  804. if (info->netcount)
  805. hdlcdev_tx_done(info);
  806. else
  807. #endif
  808. {
  809. if (tty && (tty->stopped || tty->hw_stopped)) {
  810. tx_stop(info);
  811. return;
  812. }
  813. info->pending_bh |= BH_TRANSMIT;
  814. }
  815. }
  816. static void tx_ready(MGSLPC_INFO *info, struct tty_struct *tty)
  817. {
  818. unsigned char fifo_count = 32;
  819. int c;
  820. if (debug_level >= DEBUG_LEVEL_ISR)
  821. printk("%s(%d):tx_ready(%s)\n", __FILE__, __LINE__, info->device_name);
  822. if (info->params.mode == MGSL_MODE_HDLC) {
  823. if (!info->tx_active)
  824. return;
  825. } else {
  826. if (tty && (tty->stopped || tty->hw_stopped)) {
  827. tx_stop(info);
  828. return;
  829. }
  830. if (!info->tx_count)
  831. info->tx_active = false;
  832. }
  833. if (!info->tx_count)
  834. return;
  835. while (info->tx_count && fifo_count) {
  836. c = min(2, min_t(int, fifo_count, min(info->tx_count, TXBUFSIZE - info->tx_get)));
  837. if (c == 1) {
  838. write_reg(info, CHA + TXFIFO, *(info->tx_buf + info->tx_get));
  839. } else {
  840. write_reg16(info, CHA + TXFIFO,
  841. *((unsigned short*)(info->tx_buf + info->tx_get)));
  842. }
  843. info->tx_count -= c;
  844. info->tx_get = (info->tx_get + c) & (TXBUFSIZE - 1);
  845. fifo_count -= c;
  846. }
  847. if (info->params.mode == MGSL_MODE_ASYNC) {
  848. if (info->tx_count < WAKEUP_CHARS)
  849. info->pending_bh |= BH_TRANSMIT;
  850. issue_command(info, CHA, CMD_TXFIFO);
  851. } else {
  852. if (info->tx_count)
  853. issue_command(info, CHA, CMD_TXFIFO);
  854. else
  855. issue_command(info, CHA, CMD_TXFIFO + CMD_TXEOM);
  856. }
  857. }
  858. static void cts_change(MGSLPC_INFO *info, struct tty_struct *tty)
  859. {
  860. get_signals(info);
  861. if ((info->cts_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
  862. irq_disable(info, CHB, IRQ_CTS);
  863. info->icount.cts++;
  864. if (info->serial_signals & SerialSignal_CTS)
  865. info->input_signal_events.cts_up++;
  866. else
  867. info->input_signal_events.cts_down++;
  868. wake_up_interruptible(&info->status_event_wait_q);
  869. wake_up_interruptible(&info->event_wait_q);
  870. if (tty && tty_port_cts_enabled(&info->port)) {
  871. if (tty->hw_stopped) {
  872. if (info->serial_signals & SerialSignal_CTS) {
  873. if (debug_level >= DEBUG_LEVEL_ISR)
  874. printk("CTS tx start...");
  875. tty->hw_stopped = 0;
  876. tx_start(info, tty);
  877. info->pending_bh |= BH_TRANSMIT;
  878. return;
  879. }
  880. } else {
  881. if (!(info->serial_signals & SerialSignal_CTS)) {
  882. if (debug_level >= DEBUG_LEVEL_ISR)
  883. printk("CTS tx stop...");
  884. tty->hw_stopped = 1;
  885. tx_stop(info);
  886. }
  887. }
  888. }
  889. info->pending_bh |= BH_STATUS;
  890. }
  891. static void dcd_change(MGSLPC_INFO *info, struct tty_struct *tty)
  892. {
  893. get_signals(info);
  894. if ((info->dcd_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
  895. irq_disable(info, CHB, IRQ_DCD);
  896. info->icount.dcd++;
  897. if (info->serial_signals & SerialSignal_DCD) {
  898. info->input_signal_events.dcd_up++;
  899. }
  900. else
  901. info->input_signal_events.dcd_down++;
  902. #if SYNCLINK_GENERIC_HDLC
  903. if (info->netcount) {
  904. if (info->serial_signals & SerialSignal_DCD)
  905. netif_carrier_on(info->netdev);
  906. else
  907. netif_carrier_off(info->netdev);
  908. }
  909. #endif
  910. wake_up_interruptible(&info->status_event_wait_q);
  911. wake_up_interruptible(&info->event_wait_q);
  912. if (tty_port_check_carrier(&info->port)) {
  913. if (debug_level >= DEBUG_LEVEL_ISR)
  914. printk("%s CD now %s...", info->device_name,
  915. (info->serial_signals & SerialSignal_DCD) ? "on" : "off");
  916. if (info->serial_signals & SerialSignal_DCD)
  917. wake_up_interruptible(&info->port.open_wait);
  918. else {
  919. if (debug_level >= DEBUG_LEVEL_ISR)
  920. printk("doing serial hangup...");
  921. if (tty)
  922. tty_hangup(tty);
  923. }
  924. }
  925. info->pending_bh |= BH_STATUS;
  926. }
  927. static void dsr_change(MGSLPC_INFO *info)
  928. {
  929. get_signals(info);
  930. if ((info->dsr_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
  931. port_irq_disable(info, PVR_DSR);
  932. info->icount.dsr++;
  933. if (info->serial_signals & SerialSignal_DSR)
  934. info->input_signal_events.dsr_up++;
  935. else
  936. info->input_signal_events.dsr_down++;
  937. wake_up_interruptible(&info->status_event_wait_q);
  938. wake_up_interruptible(&info->event_wait_q);
  939. info->pending_bh |= BH_STATUS;
  940. }
  941. static void ri_change(MGSLPC_INFO *info)
  942. {
  943. get_signals(info);
  944. if ((info->ri_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
  945. port_irq_disable(info, PVR_RI);
  946. info->icount.rng++;
  947. if (info->serial_signals & SerialSignal_RI)
  948. info->input_signal_events.ri_up++;
  949. else
  950. info->input_signal_events.ri_down++;
  951. wake_up_interruptible(&info->status_event_wait_q);
  952. wake_up_interruptible(&info->event_wait_q);
  953. info->pending_bh |= BH_STATUS;
  954. }
  955. /* Interrupt service routine entry point.
  956. *
  957. * Arguments:
  958. *
  959. * irq interrupt number that caused interrupt
  960. * dev_id device ID supplied during interrupt registration
  961. */
  962. static irqreturn_t mgslpc_isr(int dummy, void *dev_id)
  963. {
  964. MGSLPC_INFO *info = dev_id;
  965. struct tty_struct *tty;
  966. unsigned short isr;
  967. unsigned char gis, pis;
  968. int count=0;
  969. if (debug_level >= DEBUG_LEVEL_ISR)
  970. printk("mgslpc_isr(%d) entry.\n", info->irq_level);
  971. if (!(info->p_dev->_locked))
  972. return IRQ_HANDLED;
  973. tty = tty_port_tty_get(&info->port);
  974. spin_lock(&info->lock);
  975. while ((gis = read_reg(info, CHA + GIS))) {
  976. if (debug_level >= DEBUG_LEVEL_ISR)
  977. printk("mgslpc_isr %s gis=%04X\n", info->device_name,gis);
  978. if ((gis & 0x70) || count > 1000) {
  979. printk("synclink_cs:hardware failed or ejected\n");
  980. break;
  981. }
  982. count++;
  983. if (gis & (BIT1 | BIT0)) {
  984. isr = read_reg16(info, CHB + ISR);
  985. if (isr & IRQ_DCD)
  986. dcd_change(info, tty);
  987. if (isr & IRQ_CTS)
  988. cts_change(info, tty);
  989. }
  990. if (gis & (BIT3 | BIT2))
  991. {
  992. isr = read_reg16(info, CHA + ISR);
  993. if (isr & IRQ_TIMER) {
  994. info->irq_occurred = true;
  995. irq_disable(info, CHA, IRQ_TIMER);
  996. }
  997. /* receive IRQs */
  998. if (isr & IRQ_EXITHUNT) {
  999. info->icount.exithunt++;
  1000. wake_up_interruptible(&info->event_wait_q);
  1001. }
  1002. if (isr & IRQ_BREAK_ON) {
  1003. info->icount.brk++;
  1004. if (info->port.flags & ASYNC_SAK)
  1005. do_SAK(tty);
  1006. }
  1007. if (isr & IRQ_RXTIME) {
  1008. issue_command(info, CHA, CMD_RXFIFO_READ);
  1009. }
  1010. if (isr & (IRQ_RXEOM | IRQ_RXFIFO)) {
  1011. if (info->params.mode == MGSL_MODE_HDLC)
  1012. rx_ready_hdlc(info, isr & IRQ_RXEOM);
  1013. else
  1014. rx_ready_async(info, isr & IRQ_RXEOM);
  1015. }
  1016. /* transmit IRQs */
  1017. if (isr & IRQ_UNDERRUN) {
  1018. if (info->tx_aborting)
  1019. info->icount.txabort++;
  1020. else
  1021. info->icount.txunder++;
  1022. tx_done(info, tty);
  1023. }
  1024. else if (isr & IRQ_ALLSENT) {
  1025. info->icount.txok++;
  1026. tx_done(info, tty);
  1027. }
  1028. else if (isr & IRQ_TXFIFO)
  1029. tx_ready(info, tty);
  1030. }
  1031. if (gis & BIT7) {
  1032. pis = read_reg(info, CHA + PIS);
  1033. if (pis & BIT1)
  1034. dsr_change(info);
  1035. if (pis & BIT2)
  1036. ri_change(info);
  1037. }
  1038. }
  1039. /* Request bottom half processing if there's something
  1040. * for it to do and the bh is not already running
  1041. */
  1042. if (info->pending_bh && !info->bh_running && !info->bh_requested) {
  1043. if (debug_level >= DEBUG_LEVEL_ISR)
  1044. printk("%s(%d):%s queueing bh task.\n",
  1045. __FILE__,__LINE__,info->device_name);
  1046. schedule_work(&info->task);
  1047. info->bh_requested = true;
  1048. }
  1049. spin_unlock(&info->lock);
  1050. tty_kref_put(tty);
  1051. if (debug_level >= DEBUG_LEVEL_ISR)
  1052. printk("%s(%d):mgslpc_isr(%d)exit.\n",
  1053. __FILE__, __LINE__, info->irq_level);
  1054. return IRQ_HANDLED;
  1055. }
  1056. /* Initialize and start device.
  1057. */
  1058. static int startup(MGSLPC_INFO * info, struct tty_struct *tty)
  1059. {
  1060. int retval = 0;
  1061. if (debug_level >= DEBUG_LEVEL_INFO)
  1062. printk("%s(%d):startup(%s)\n", __FILE__, __LINE__, info->device_name);
  1063. if (tty_port_initialized(&info->port))
  1064. return 0;
  1065. if (!info->tx_buf) {
  1066. /* allocate a page of memory for a transmit buffer */
  1067. info->tx_buf = (unsigned char *)get_zeroed_page(GFP_KERNEL);
  1068. if (!info->tx_buf) {
  1069. printk(KERN_ERR"%s(%d):%s can't allocate transmit buffer\n",
  1070. __FILE__, __LINE__, info->device_name);
  1071. return -ENOMEM;
  1072. }
  1073. }
  1074. info->pending_bh = 0;
  1075. memset(&info->icount, 0, sizeof(info->icount));
  1076. timer_setup(&info->tx_timer, tx_timeout, 0);
  1077. /* Allocate and claim adapter resources */
  1078. retval = claim_resources(info);
  1079. /* perform existence check and diagnostics */
  1080. if (!retval)
  1081. retval = adapter_test(info);
  1082. if (retval) {
  1083. if (capable(CAP_SYS_ADMIN) && tty)
  1084. set_bit(TTY_IO_ERROR, &tty->flags);
  1085. release_resources(info);
  1086. return retval;
  1087. }
  1088. /* program hardware for current parameters */
  1089. mgslpc_change_params(info, tty);
  1090. if (tty)
  1091. clear_bit(TTY_IO_ERROR, &tty->flags);
  1092. tty_port_set_initialized(&info->port, 1);
  1093. return 0;
  1094. }
  1095. /* Called by mgslpc_close() and mgslpc_hangup() to shutdown hardware
  1096. */
  1097. static void shutdown(MGSLPC_INFO * info, struct tty_struct *tty)
  1098. {
  1099. unsigned long flags;
  1100. if (!tty_port_initialized(&info->port))
  1101. return;
  1102. if (debug_level >= DEBUG_LEVEL_INFO)
  1103. printk("%s(%d):mgslpc_shutdown(%s)\n",
  1104. __FILE__, __LINE__, info->device_name);
  1105. /* clear status wait queue because status changes */
  1106. /* can't happen after shutting down the hardware */
  1107. wake_up_interruptible(&info->status_event_wait_q);
  1108. wake_up_interruptible(&info->event_wait_q);
  1109. del_timer_sync(&info->tx_timer);
  1110. if (info->tx_buf) {
  1111. free_page((unsigned long) info->tx_buf);
  1112. info->tx_buf = NULL;
  1113. }
  1114. spin_lock_irqsave(&info->lock, flags);
  1115. rx_stop(info);
  1116. tx_stop(info);
  1117. /* TODO:disable interrupts instead of reset to preserve signal states */
  1118. reset_device(info);
  1119. if (!tty || C_HUPCL(tty)) {
  1120. info->serial_signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
  1121. set_signals(info);
  1122. }
  1123. spin_unlock_irqrestore(&info->lock, flags);
  1124. release_resources(info);
  1125. if (tty)
  1126. set_bit(TTY_IO_ERROR, &tty->flags);
  1127. tty_port_set_initialized(&info->port, 0);
  1128. }
  1129. static void mgslpc_program_hw(MGSLPC_INFO *info, struct tty_struct *tty)
  1130. {
  1131. unsigned long flags;
  1132. spin_lock_irqsave(&info->lock, flags);
  1133. rx_stop(info);
  1134. tx_stop(info);
  1135. info->tx_count = info->tx_put = info->tx_get = 0;
  1136. if (info->params.mode == MGSL_MODE_HDLC || info->netcount)
  1137. hdlc_mode(info);
  1138. else
  1139. async_mode(info);
  1140. set_signals(info);
  1141. info->dcd_chkcount = 0;
  1142. info->cts_chkcount = 0;
  1143. info->ri_chkcount = 0;
  1144. info->dsr_chkcount = 0;
  1145. irq_enable(info, CHB, IRQ_DCD | IRQ_CTS);
  1146. port_irq_enable(info, (unsigned char) PVR_DSR | PVR_RI);
  1147. get_signals(info);
  1148. if (info->netcount || (tty && C_CREAD(tty)))
  1149. rx_start(info);
  1150. spin_unlock_irqrestore(&info->lock, flags);
  1151. }
  1152. /* Reconfigure adapter based on new parameters
  1153. */
  1154. static void mgslpc_change_params(MGSLPC_INFO *info, struct tty_struct *tty)
  1155. {
  1156. unsigned cflag;
  1157. int bits_per_char;
  1158. if (!tty)
  1159. return;
  1160. if (debug_level >= DEBUG_LEVEL_INFO)
  1161. printk("%s(%d):mgslpc_change_params(%s)\n",
  1162. __FILE__, __LINE__, info->device_name);
  1163. cflag = tty->termios.c_cflag;
  1164. /* if B0 rate (hangup) specified then negate RTS and DTR */
  1165. /* otherwise assert RTS and DTR */
  1166. if (cflag & CBAUD)
  1167. info->serial_signals |= SerialSignal_RTS | SerialSignal_DTR;
  1168. else
  1169. info->serial_signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
  1170. /* byte size and parity */
  1171. switch (cflag & CSIZE) {
  1172. case CS5: info->params.data_bits = 5; break;
  1173. case CS6: info->params.data_bits = 6; break;
  1174. case CS7: info->params.data_bits = 7; break;
  1175. case CS8: info->params.data_bits = 8; break;
  1176. default: info->params.data_bits = 7; break;
  1177. }
  1178. if (cflag & CSTOPB)
  1179. info->params.stop_bits = 2;
  1180. else
  1181. info->params.stop_bits = 1;
  1182. info->params.parity = ASYNC_PARITY_NONE;
  1183. if (cflag & PARENB) {
  1184. if (cflag & PARODD)
  1185. info->params.parity = ASYNC_PARITY_ODD;
  1186. else
  1187. info->params.parity = ASYNC_PARITY_EVEN;
  1188. #ifdef CMSPAR
  1189. if (cflag & CMSPAR)
  1190. info->params.parity = ASYNC_PARITY_SPACE;
  1191. #endif
  1192. }
  1193. /* calculate number of jiffies to transmit a full
  1194. * FIFO (32 bytes) at specified data rate
  1195. */
  1196. bits_per_char = info->params.data_bits +
  1197. info->params.stop_bits + 1;
  1198. /* if port data rate is set to 460800 or less then
  1199. * allow tty settings to override, otherwise keep the
  1200. * current data rate.
  1201. */
  1202. if (info->params.data_rate <= 460800) {
  1203. info->params.data_rate = tty_get_baud_rate(tty);
  1204. }
  1205. if (info->params.data_rate) {
  1206. info->timeout = (32*HZ*bits_per_char) /
  1207. info->params.data_rate;
  1208. }
  1209. info->timeout += HZ/50; /* Add .02 seconds of slop */
  1210. tty_port_set_cts_flow(&info->port, cflag & CRTSCTS);
  1211. tty_port_set_check_carrier(&info->port, ~cflag & CLOCAL);
  1212. /* process tty input control flags */
  1213. info->read_status_mask = 0;
  1214. if (I_INPCK(tty))
  1215. info->read_status_mask |= BIT7 | BIT6;
  1216. if (I_IGNPAR(tty))
  1217. info->ignore_status_mask |= BIT7 | BIT6;
  1218. mgslpc_program_hw(info, tty);
  1219. }
  1220. /* Add a character to the transmit buffer
  1221. */
  1222. static int mgslpc_put_char(struct tty_struct *tty, unsigned char ch)
  1223. {
  1224. MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
  1225. unsigned long flags;
  1226. if (debug_level >= DEBUG_LEVEL_INFO) {
  1227. printk("%s(%d):mgslpc_put_char(%d) on %s\n",
  1228. __FILE__, __LINE__, ch, info->device_name);
  1229. }
  1230. if (mgslpc_paranoia_check(info, tty->name, "mgslpc_put_char"))
  1231. return 0;
  1232. if (!info->tx_buf)
  1233. return 0;
  1234. spin_lock_irqsave(&info->lock, flags);
  1235. if (info->params.mode == MGSL_MODE_ASYNC || !info->tx_active) {
  1236. if (info->tx_count < TXBUFSIZE - 1) {
  1237. info->tx_buf[info->tx_put++] = ch;
  1238. info->tx_put &= TXBUFSIZE-1;
  1239. info->tx_count++;
  1240. }
  1241. }
  1242. spin_unlock_irqrestore(&info->lock, flags);
  1243. return 1;
  1244. }
  1245. /* Enable transmitter so remaining characters in the
  1246. * transmit buffer are sent.
  1247. */
  1248. static void mgslpc_flush_chars(struct tty_struct *tty)
  1249. {
  1250. MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
  1251. unsigned long flags;
  1252. if (debug_level >= DEBUG_LEVEL_INFO)
  1253. printk("%s(%d):mgslpc_flush_chars() entry on %s tx_count=%d\n",
  1254. __FILE__, __LINE__, info->device_name, info->tx_count);
  1255. if (mgslpc_paranoia_check(info, tty->name, "mgslpc_flush_chars"))
  1256. return;
  1257. if (info->tx_count <= 0 || tty->stopped ||
  1258. tty->hw_stopped || !info->tx_buf)
  1259. return;
  1260. if (debug_level >= DEBUG_LEVEL_INFO)
  1261. printk("%s(%d):mgslpc_flush_chars() entry on %s starting transmitter\n",
  1262. __FILE__, __LINE__, info->device_name);
  1263. spin_lock_irqsave(&info->lock, flags);
  1264. if (!info->tx_active)
  1265. tx_start(info, tty);
  1266. spin_unlock_irqrestore(&info->lock, flags);
  1267. }
  1268. /* Send a block of data
  1269. *
  1270. * Arguments:
  1271. *
  1272. * tty pointer to tty information structure
  1273. * buf pointer to buffer containing send data
  1274. * count size of send data in bytes
  1275. *
  1276. * Returns: number of characters written
  1277. */
  1278. static int mgslpc_write(struct tty_struct * tty,
  1279. const unsigned char *buf, int count)
  1280. {
  1281. int c, ret = 0;
  1282. MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
  1283. unsigned long flags;
  1284. if (debug_level >= DEBUG_LEVEL_INFO)
  1285. printk("%s(%d):mgslpc_write(%s) count=%d\n",
  1286. __FILE__, __LINE__, info->device_name, count);
  1287. if (mgslpc_paranoia_check(info, tty->name, "mgslpc_write") ||
  1288. !info->tx_buf)
  1289. goto cleanup;
  1290. if (info->params.mode == MGSL_MODE_HDLC) {
  1291. if (count > TXBUFSIZE) {
  1292. ret = -EIO;
  1293. goto cleanup;
  1294. }
  1295. if (info->tx_active)
  1296. goto cleanup;
  1297. else if (info->tx_count)
  1298. goto start;
  1299. }
  1300. for (;;) {
  1301. c = min(count,
  1302. min(TXBUFSIZE - info->tx_count - 1,
  1303. TXBUFSIZE - info->tx_put));
  1304. if (c <= 0)
  1305. break;
  1306. memcpy(info->tx_buf + info->tx_put, buf, c);
  1307. spin_lock_irqsave(&info->lock, flags);
  1308. info->tx_put = (info->tx_put + c) & (TXBUFSIZE-1);
  1309. info->tx_count += c;
  1310. spin_unlock_irqrestore(&info->lock, flags);
  1311. buf += c;
  1312. count -= c;
  1313. ret += c;
  1314. }
  1315. start:
  1316. if (info->tx_count && !tty->stopped && !tty->hw_stopped) {
  1317. spin_lock_irqsave(&info->lock, flags);
  1318. if (!info->tx_active)
  1319. tx_start(info, tty);
  1320. spin_unlock_irqrestore(&info->lock, flags);
  1321. }
  1322. cleanup:
  1323. if (debug_level >= DEBUG_LEVEL_INFO)
  1324. printk("%s(%d):mgslpc_write(%s) returning=%d\n",
  1325. __FILE__, __LINE__, info->device_name, ret);
  1326. return ret;
  1327. }
  1328. /* Return the count of free bytes in transmit buffer
  1329. */
  1330. static int mgslpc_write_room(struct tty_struct *tty)
  1331. {
  1332. MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
  1333. int ret;
  1334. if (mgslpc_paranoia_check(info, tty->name, "mgslpc_write_room"))
  1335. return 0;
  1336. if (info->params.mode == MGSL_MODE_HDLC) {
  1337. /* HDLC (frame oriented) mode */
  1338. if (info->tx_active)
  1339. return 0;
  1340. else
  1341. return HDLC_MAX_FRAME_SIZE;
  1342. } else {
  1343. ret = TXBUFSIZE - info->tx_count - 1;
  1344. if (ret < 0)
  1345. ret = 0;
  1346. }
  1347. if (debug_level >= DEBUG_LEVEL_INFO)
  1348. printk("%s(%d):mgslpc_write_room(%s)=%d\n",
  1349. __FILE__, __LINE__, info->device_name, ret);
  1350. return ret;
  1351. }
  1352. /* Return the count of bytes in transmit buffer
  1353. */
  1354. static int mgslpc_chars_in_buffer(struct tty_struct *tty)
  1355. {
  1356. MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
  1357. int rc;
  1358. if (debug_level >= DEBUG_LEVEL_INFO)
  1359. printk("%s(%d):mgslpc_chars_in_buffer(%s)\n",
  1360. __FILE__, __LINE__, info->device_name);
  1361. if (mgslpc_paranoia_check(info, tty->name, "mgslpc_chars_in_buffer"))
  1362. return 0;
  1363. if (info->params.mode == MGSL_MODE_HDLC)
  1364. rc = info->tx_active ? info->max_frame_size : 0;
  1365. else
  1366. rc = info->tx_count;
  1367. if (debug_level >= DEBUG_LEVEL_INFO)
  1368. printk("%s(%d):mgslpc_chars_in_buffer(%s)=%d\n",
  1369. __FILE__, __LINE__, info->device_name, rc);
  1370. return rc;
  1371. }
  1372. /* Discard all data in the send buffer
  1373. */
  1374. static void mgslpc_flush_buffer(struct tty_struct *tty)
  1375. {
  1376. MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
  1377. unsigned long flags;
  1378. if (debug_level >= DEBUG_LEVEL_INFO)
  1379. printk("%s(%d):mgslpc_flush_buffer(%s) entry\n",
  1380. __FILE__, __LINE__, info->device_name);
  1381. if (mgslpc_paranoia_check(info, tty->name, "mgslpc_flush_buffer"))
  1382. return;
  1383. spin_lock_irqsave(&info->lock, flags);
  1384. info->tx_count = info->tx_put = info->tx_get = 0;
  1385. del_timer(&info->tx_timer);
  1386. spin_unlock_irqrestore(&info->lock, flags);
  1387. wake_up_interruptible(&tty->write_wait);
  1388. tty_wakeup(tty);
  1389. }
  1390. /* Send a high-priority XON/XOFF character
  1391. */
  1392. static void mgslpc_send_xchar(struct tty_struct *tty, char ch)
  1393. {
  1394. MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
  1395. unsigned long flags;
  1396. if (debug_level >= DEBUG_LEVEL_INFO)
  1397. printk("%s(%d):mgslpc_send_xchar(%s,%d)\n",
  1398. __FILE__, __LINE__, info->device_name, ch);
  1399. if (mgslpc_paranoia_check(info, tty->name, "mgslpc_send_xchar"))
  1400. return;
  1401. info->x_char = ch;
  1402. if (ch) {
  1403. spin_lock_irqsave(&info->lock, flags);
  1404. if (!info->tx_enabled)
  1405. tx_start(info, tty);
  1406. spin_unlock_irqrestore(&info->lock, flags);
  1407. }
  1408. }
  1409. /* Signal remote device to throttle send data (our receive data)
  1410. */
  1411. static void mgslpc_throttle(struct tty_struct * tty)
  1412. {
  1413. MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
  1414. unsigned long flags;
  1415. if (debug_level >= DEBUG_LEVEL_INFO)
  1416. printk("%s(%d):mgslpc_throttle(%s) entry\n",
  1417. __FILE__, __LINE__, info->device_name);
  1418. if (mgslpc_paranoia_check(info, tty->name, "mgslpc_throttle"))
  1419. return;
  1420. if (I_IXOFF(tty))
  1421. mgslpc_send_xchar(tty, STOP_CHAR(tty));
  1422. if (C_CRTSCTS(tty)) {
  1423. spin_lock_irqsave(&info->lock, flags);
  1424. info->serial_signals &= ~SerialSignal_RTS;
  1425. set_signals(info);
  1426. spin_unlock_irqrestore(&info->lock, flags);
  1427. }
  1428. }
  1429. /* Signal remote device to stop throttling send data (our receive data)
  1430. */
  1431. static void mgslpc_unthrottle(struct tty_struct * tty)
  1432. {
  1433. MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
  1434. unsigned long flags;
  1435. if (debug_level >= DEBUG_LEVEL_INFO)
  1436. printk("%s(%d):mgslpc_unthrottle(%s) entry\n",
  1437. __FILE__, __LINE__, info->device_name);
  1438. if (mgslpc_paranoia_check(info, tty->name, "mgslpc_unthrottle"))
  1439. return;
  1440. if (I_IXOFF(tty)) {
  1441. if (info->x_char)
  1442. info->x_char = 0;
  1443. else
  1444. mgslpc_send_xchar(tty, START_CHAR(tty));
  1445. }
  1446. if (C_CRTSCTS(tty)) {
  1447. spin_lock_irqsave(&info->lock, flags);
  1448. info->serial_signals |= SerialSignal_RTS;
  1449. set_signals(info);
  1450. spin_unlock_irqrestore(&info->lock, flags);
  1451. }
  1452. }
  1453. /* get the current serial statistics
  1454. */
  1455. static int get_stats(MGSLPC_INFO * info, struct mgsl_icount __user *user_icount)
  1456. {
  1457. int err;
  1458. if (debug_level >= DEBUG_LEVEL_INFO)
  1459. printk("get_params(%s)\n", info->device_name);
  1460. if (!user_icount) {
  1461. memset(&info->icount, 0, sizeof(info->icount));
  1462. } else {
  1463. COPY_TO_USER(err, user_icount, &info->icount, sizeof(struct mgsl_icount));
  1464. if (err)
  1465. return -EFAULT;
  1466. }
  1467. return 0;
  1468. }
  1469. /* get the current serial parameters
  1470. */
  1471. static int get_params(MGSLPC_INFO * info, MGSL_PARAMS __user *user_params)
  1472. {
  1473. int err;
  1474. if (debug_level >= DEBUG_LEVEL_INFO)
  1475. printk("get_params(%s)\n", info->device_name);
  1476. COPY_TO_USER(err,user_params, &info->params, sizeof(MGSL_PARAMS));
  1477. if (err)
  1478. return -EFAULT;
  1479. return 0;
  1480. }
  1481. /* set the serial parameters
  1482. *
  1483. * Arguments:
  1484. *
  1485. * info pointer to device instance data
  1486. * new_params user buffer containing new serial params
  1487. *
  1488. * Returns: 0 if success, otherwise error code
  1489. */
  1490. static int set_params(MGSLPC_INFO * info, MGSL_PARAMS __user *new_params, struct tty_struct *tty)
  1491. {
  1492. unsigned long flags;
  1493. MGSL_PARAMS tmp_params;
  1494. int err;
  1495. if (debug_level >= DEBUG_LEVEL_INFO)
  1496. printk("%s(%d):set_params %s\n", __FILE__,__LINE__,
  1497. info->device_name);
  1498. COPY_FROM_USER(err,&tmp_params, new_params, sizeof(MGSL_PARAMS));
  1499. if (err) {
  1500. if (debug_level >= DEBUG_LEVEL_INFO)
  1501. printk("%s(%d):set_params(%s) user buffer copy failed\n",
  1502. __FILE__, __LINE__, info->device_name);
  1503. return -EFAULT;
  1504. }
  1505. spin_lock_irqsave(&info->lock, flags);
  1506. memcpy(&info->params,&tmp_params,sizeof(MGSL_PARAMS));
  1507. spin_unlock_irqrestore(&info->lock, flags);
  1508. mgslpc_change_params(info, tty);
  1509. return 0;
  1510. }
  1511. static int get_txidle(MGSLPC_INFO * info, int __user *idle_mode)
  1512. {
  1513. int err;
  1514. if (debug_level >= DEBUG_LEVEL_INFO)
  1515. printk("get_txidle(%s)=%d\n", info->device_name, info->idle_mode);
  1516. COPY_TO_USER(err,idle_mode, &info->idle_mode, sizeof(int));
  1517. if (err)
  1518. return -EFAULT;
  1519. return 0;
  1520. }
  1521. static int set_txidle(MGSLPC_INFO * info, int idle_mode)
  1522. {
  1523. unsigned long flags;
  1524. if (debug_level >= DEBUG_LEVEL_INFO)
  1525. printk("set_txidle(%s,%d)\n", info->device_name, idle_mode);
  1526. spin_lock_irqsave(&info->lock, flags);
  1527. info->idle_mode = idle_mode;
  1528. tx_set_idle(info);
  1529. spin_unlock_irqrestore(&info->lock, flags);
  1530. return 0;
  1531. }
  1532. static int get_interface(MGSLPC_INFO * info, int __user *if_mode)
  1533. {
  1534. int err;
  1535. if (debug_level >= DEBUG_LEVEL_INFO)
  1536. printk("get_interface(%s)=%d\n", info->device_name, info->if_mode);
  1537. COPY_TO_USER(err,if_mode, &info->if_mode, sizeof(int));
  1538. if (err)
  1539. return -EFAULT;
  1540. return 0;
  1541. }
  1542. static int set_interface(MGSLPC_INFO * info, int if_mode)
  1543. {
  1544. unsigned long flags;
  1545. unsigned char val;
  1546. if (debug_level >= DEBUG_LEVEL_INFO)
  1547. printk("set_interface(%s,%d)\n", info->device_name, if_mode);
  1548. spin_lock_irqsave(&info->lock, flags);
  1549. info->if_mode = if_mode;
  1550. val = read_reg(info, PVR) & 0x0f;
  1551. switch (info->if_mode)
  1552. {
  1553. case MGSL_INTERFACE_RS232: val |= PVR_RS232; break;
  1554. case MGSL_INTERFACE_V35: val |= PVR_V35; break;
  1555. case MGSL_INTERFACE_RS422: val |= PVR_RS422; break;
  1556. }
  1557. write_reg(info, PVR, val);
  1558. spin_unlock_irqrestore(&info->lock, flags);
  1559. return 0;
  1560. }
  1561. static int set_txenable(MGSLPC_INFO * info, int enable, struct tty_struct *tty)
  1562. {
  1563. unsigned long flags;
  1564. if (debug_level >= DEBUG_LEVEL_INFO)
  1565. printk("set_txenable(%s,%d)\n", info->device_name, enable);
  1566. spin_lock_irqsave(&info->lock, flags);
  1567. if (enable) {
  1568. if (!info->tx_enabled)
  1569. tx_start(info, tty);
  1570. } else {
  1571. if (info->tx_enabled)
  1572. tx_stop(info);
  1573. }
  1574. spin_unlock_irqrestore(&info->lock, flags);
  1575. return 0;
  1576. }
  1577. static int tx_abort(MGSLPC_INFO * info)
  1578. {
  1579. unsigned long flags;
  1580. if (debug_level >= DEBUG_LEVEL_INFO)
  1581. printk("tx_abort(%s)\n", info->device_name);
  1582. spin_lock_irqsave(&info->lock, flags);
  1583. if (info->tx_active && info->tx_count &&
  1584. info->params.mode == MGSL_MODE_HDLC) {
  1585. /* clear data count so FIFO is not filled on next IRQ.
  1586. * This results in underrun and abort transmission.
  1587. */
  1588. info->tx_count = info->tx_put = info->tx_get = 0;
  1589. info->tx_aborting = true;
  1590. }
  1591. spin_unlock_irqrestore(&info->lock, flags);
  1592. return 0;
  1593. }
  1594. static int set_rxenable(MGSLPC_INFO * info, int enable)
  1595. {
  1596. unsigned long flags;
  1597. if (debug_level >= DEBUG_LEVEL_INFO)
  1598. printk("set_rxenable(%s,%d)\n", info->device_name, enable);
  1599. spin_lock_irqsave(&info->lock, flags);
  1600. if (enable) {
  1601. if (!info->rx_enabled)
  1602. rx_start(info);
  1603. } else {
  1604. if (info->rx_enabled)
  1605. rx_stop(info);
  1606. }
  1607. spin_unlock_irqrestore(&info->lock, flags);
  1608. return 0;
  1609. }
  1610. /* wait for specified event to occur
  1611. *
  1612. * Arguments: info pointer to device instance data
  1613. * mask pointer to bitmask of events to wait for
  1614. * Return Value: 0 if successful and bit mask updated with
  1615. * of events triggerred,
  1616. * otherwise error code
  1617. */
  1618. static int wait_events(MGSLPC_INFO * info, int __user *mask_ptr)
  1619. {
  1620. unsigned long flags;
  1621. int s;
  1622. int rc=0;
  1623. struct mgsl_icount cprev, cnow;
  1624. int events;
  1625. int mask;
  1626. struct _input_signal_events oldsigs, newsigs;
  1627. DECLARE_WAITQUEUE(wait, current);
  1628. COPY_FROM_USER(rc,&mask, mask_ptr, sizeof(int));
  1629. if (rc)
  1630. return -EFAULT;
  1631. if (debug_level >= DEBUG_LEVEL_INFO)
  1632. printk("wait_events(%s,%d)\n", info->device_name, mask);
  1633. spin_lock_irqsave(&info->lock, flags);
  1634. /* return immediately if state matches requested events */
  1635. get_signals(info);
  1636. s = info->serial_signals;
  1637. events = mask &
  1638. ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
  1639. ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
  1640. ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
  1641. ((s & SerialSignal_RI) ? MgslEvent_RiActive :MgslEvent_RiInactive) );
  1642. if (events) {
  1643. spin_unlock_irqrestore(&info->lock, flags);
  1644. goto exit;
  1645. }
  1646. /* save current irq counts */
  1647. cprev = info->icount;
  1648. oldsigs = info->input_signal_events;
  1649. if ((info->params.mode == MGSL_MODE_HDLC) &&
  1650. (mask & MgslEvent_ExitHuntMode))
  1651. irq_enable(info, CHA, IRQ_EXITHUNT);
  1652. set_current_state(TASK_INTERRUPTIBLE);
  1653. add_wait_queue(&info->event_wait_q, &wait);
  1654. spin_unlock_irqrestore(&info->lock, flags);
  1655. for(;;) {
  1656. schedule();
  1657. if (signal_pending(current)) {
  1658. rc = -ERESTARTSYS;
  1659. break;
  1660. }
  1661. /* get current irq counts */
  1662. spin_lock_irqsave(&info->lock, flags);
  1663. cnow = info->icount;
  1664. newsigs = info->input_signal_events;
  1665. set_current_state(TASK_INTERRUPTIBLE);
  1666. spin_unlock_irqrestore(&info->lock, flags);
  1667. /* if no change, wait aborted for some reason */
  1668. if (newsigs.dsr_up == oldsigs.dsr_up &&
  1669. newsigs.dsr_down == oldsigs.dsr_down &&
  1670. newsigs.dcd_up == oldsigs.dcd_up &&
  1671. newsigs.dcd_down == oldsigs.dcd_down &&
  1672. newsigs.cts_up == oldsigs.cts_up &&
  1673. newsigs.cts_down == oldsigs.cts_down &&
  1674. newsigs.ri_up == oldsigs.ri_up &&
  1675. newsigs.ri_down == oldsigs.ri_down &&
  1676. cnow.exithunt == cprev.exithunt &&
  1677. cnow.rxidle == cprev.rxidle) {
  1678. rc = -EIO;
  1679. break;
  1680. }
  1681. events = mask &
  1682. ( (newsigs.dsr_up != oldsigs.dsr_up ? MgslEvent_DsrActive:0) +
  1683. (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
  1684. (newsigs.dcd_up != oldsigs.dcd_up ? MgslEvent_DcdActive:0) +
  1685. (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
  1686. (newsigs.cts_up != oldsigs.cts_up ? MgslEvent_CtsActive:0) +
  1687. (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
  1688. (newsigs.ri_up != oldsigs.ri_up ? MgslEvent_RiActive:0) +
  1689. (newsigs.ri_down != oldsigs.ri_down ? MgslEvent_RiInactive:0) +
  1690. (cnow.exithunt != cprev.exithunt ? MgslEvent_ExitHuntMode:0) +
  1691. (cnow.rxidle != cprev.rxidle ? MgslEvent_IdleReceived:0) );
  1692. if (events)
  1693. break;
  1694. cprev = cnow;
  1695. oldsigs = newsigs;
  1696. }
  1697. remove_wait_queue(&info->event_wait_q, &wait);
  1698. set_current_state(TASK_RUNNING);
  1699. if (mask & MgslEvent_ExitHuntMode) {
  1700. spin_lock_irqsave(&info->lock, flags);
  1701. if (!waitqueue_active(&info->event_wait_q))
  1702. irq_disable(info, CHA, IRQ_EXITHUNT);
  1703. spin_unlock_irqrestore(&info->lock, flags);
  1704. }
  1705. exit:
  1706. if (rc == 0)
  1707. PUT_USER(rc, events, mask_ptr);
  1708. return rc;
  1709. }
  1710. static int modem_input_wait(MGSLPC_INFO *info,int arg)
  1711. {
  1712. unsigned long flags;
  1713. int rc;
  1714. struct mgsl_icount cprev, cnow;
  1715. DECLARE_WAITQUEUE(wait, current);
  1716. /* save current irq counts */
  1717. spin_lock_irqsave(&info->lock, flags);
  1718. cprev = info->icount;
  1719. add_wait_queue(&info->status_event_wait_q, &wait);
  1720. set_current_state(TASK_INTERRUPTIBLE);
  1721. spin_unlock_irqrestore(&info->lock, flags);
  1722. for(;;) {
  1723. schedule();
  1724. if (signal_pending(current)) {
  1725. rc = -ERESTARTSYS;
  1726. break;
  1727. }
  1728. /* get new irq counts */
  1729. spin_lock_irqsave(&info->lock, flags);
  1730. cnow = info->icount;
  1731. set_current_state(TASK_INTERRUPTIBLE);
  1732. spin_unlock_irqrestore(&info->lock, flags);
  1733. /* if no change, wait aborted for some reason */
  1734. if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
  1735. cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
  1736. rc = -EIO;
  1737. break;
  1738. }
  1739. /* check for change in caller specified modem input */
  1740. if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
  1741. (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
  1742. (arg & TIOCM_CD && cnow.dcd != cprev.dcd) ||
  1743. (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
  1744. rc = 0;
  1745. break;
  1746. }
  1747. cprev = cnow;
  1748. }
  1749. remove_wait_queue(&info->status_event_wait_q, &wait);
  1750. set_current_state(TASK_RUNNING);
  1751. return rc;
  1752. }
  1753. /* return the state of the serial control and status signals
  1754. */
  1755. static int tiocmget(struct tty_struct *tty)
  1756. {
  1757. MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
  1758. unsigned int result;
  1759. unsigned long flags;
  1760. spin_lock_irqsave(&info->lock, flags);
  1761. get_signals(info);
  1762. spin_unlock_irqrestore(&info->lock, flags);
  1763. result = ((info->serial_signals & SerialSignal_RTS) ? TIOCM_RTS:0) +
  1764. ((info->serial_signals & SerialSignal_DTR) ? TIOCM_DTR:0) +
  1765. ((info->serial_signals & SerialSignal_DCD) ? TIOCM_CAR:0) +
  1766. ((info->serial_signals & SerialSignal_RI) ? TIOCM_RNG:0) +
  1767. ((info->serial_signals & SerialSignal_DSR) ? TIOCM_DSR:0) +
  1768. ((info->serial_signals & SerialSignal_CTS) ? TIOCM_CTS:0);
  1769. if (debug_level >= DEBUG_LEVEL_INFO)
  1770. printk("%s(%d):%s tiocmget() value=%08X\n",
  1771. __FILE__, __LINE__, info->device_name, result);
  1772. return result;
  1773. }
  1774. /* set modem control signals (DTR/RTS)
  1775. */
  1776. static int tiocmset(struct tty_struct *tty,
  1777. unsigned int set, unsigned int clear)
  1778. {
  1779. MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
  1780. unsigned long flags;
  1781. if (debug_level >= DEBUG_LEVEL_INFO)
  1782. printk("%s(%d):%s tiocmset(%x,%x)\n",
  1783. __FILE__, __LINE__, info->device_name, set, clear);
  1784. if (set & TIOCM_RTS)
  1785. info->serial_signals |= SerialSignal_RTS;
  1786. if (set & TIOCM_DTR)
  1787. info->serial_signals |= SerialSignal_DTR;
  1788. if (clear & TIOCM_RTS)
  1789. info->serial_signals &= ~SerialSignal_RTS;
  1790. if (clear & TIOCM_DTR)
  1791. info->serial_signals &= ~SerialSignal_DTR;
  1792. spin_lock_irqsave(&info->lock, flags);
  1793. set_signals(info);
  1794. spin_unlock_irqrestore(&info->lock, flags);
  1795. return 0;
  1796. }
  1797. /* Set or clear transmit break condition
  1798. *
  1799. * Arguments: tty pointer to tty instance data
  1800. * break_state -1=set break condition, 0=clear
  1801. */
  1802. static int mgslpc_break(struct tty_struct *tty, int break_state)
  1803. {
  1804. MGSLPC_INFO * info = (MGSLPC_INFO *)tty->driver_data;
  1805. unsigned long flags;
  1806. if (debug_level >= DEBUG_LEVEL_INFO)
  1807. printk("%s(%d):mgslpc_break(%s,%d)\n",
  1808. __FILE__, __LINE__, info->device_name, break_state);
  1809. if (mgslpc_paranoia_check(info, tty->name, "mgslpc_break"))
  1810. return -EINVAL;
  1811. spin_lock_irqsave(&info->lock, flags);
  1812. if (break_state == -1)
  1813. set_reg_bits(info, CHA+DAFO, BIT6);
  1814. else
  1815. clear_reg_bits(info, CHA+DAFO, BIT6);
  1816. spin_unlock_irqrestore(&info->lock, flags);
  1817. return 0;
  1818. }
  1819. static int mgslpc_get_icount(struct tty_struct *tty,
  1820. struct serial_icounter_struct *icount)
  1821. {
  1822. MGSLPC_INFO * info = (MGSLPC_INFO *)tty->driver_data;
  1823. struct mgsl_icount cnow; /* kernel counter temps */
  1824. unsigned long flags;
  1825. spin_lock_irqsave(&info->lock, flags);
  1826. cnow = info->icount;
  1827. spin_unlock_irqrestore(&info->lock, flags);
  1828. icount->cts = cnow.cts;
  1829. icount->dsr = cnow.dsr;
  1830. icount->rng = cnow.rng;
  1831. icount->dcd = cnow.dcd;
  1832. icount->rx = cnow.rx;
  1833. icount->tx = cnow.tx;
  1834. icount->frame = cnow.frame;
  1835. icount->overrun = cnow.overrun;
  1836. icount->parity = cnow.parity;
  1837. icount->brk = cnow.brk;
  1838. icount->buf_overrun = cnow.buf_overrun;
  1839. return 0;
  1840. }
  1841. /* Service an IOCTL request
  1842. *
  1843. * Arguments:
  1844. *
  1845. * tty pointer to tty instance data
  1846. * cmd IOCTL command code
  1847. * arg command argument/context
  1848. *
  1849. * Return Value: 0 if success, otherwise error code
  1850. */
  1851. static int mgslpc_ioctl(struct tty_struct *tty,
  1852. unsigned int cmd, unsigned long arg)
  1853. {
  1854. MGSLPC_INFO * info = (MGSLPC_INFO *)tty->driver_data;
  1855. void __user *argp = (void __user *)arg;
  1856. if (debug_level >= DEBUG_LEVEL_INFO)
  1857. printk("%s(%d):mgslpc_ioctl %s cmd=%08X\n", __FILE__, __LINE__,
  1858. info->device_name, cmd);
  1859. if (mgslpc_paranoia_check(info, tty->name, "mgslpc_ioctl"))
  1860. return -ENODEV;
  1861. if (cmd != TIOCMIWAIT) {
  1862. if (tty_io_error(tty))
  1863. return -EIO;
  1864. }
  1865. switch (cmd) {
  1866. case MGSL_IOCGPARAMS:
  1867. return get_params(info, argp);
  1868. case MGSL_IOCSPARAMS:
  1869. return set_params(info, argp, tty);
  1870. case MGSL_IOCGTXIDLE:
  1871. return get_txidle(info, argp);
  1872. case MGSL_IOCSTXIDLE:
  1873. return set_txidle(info, (int)arg);
  1874. case MGSL_IOCGIF:
  1875. return get_interface(info, argp);
  1876. case MGSL_IOCSIF:
  1877. return set_interface(info,(int)arg);
  1878. case MGSL_IOCTXENABLE:
  1879. return set_txenable(info,(int)arg, tty);
  1880. case MGSL_IOCRXENABLE:
  1881. return set_rxenable(info,(int)arg);
  1882. case MGSL_IOCTXABORT:
  1883. return tx_abort(info);
  1884. case MGSL_IOCGSTATS:
  1885. return get_stats(info, argp);
  1886. case MGSL_IOCWAITEVENT:
  1887. return wait_events(info, argp);
  1888. case TIOCMIWAIT:
  1889. return modem_input_wait(info,(int)arg);
  1890. default:
  1891. return -ENOIOCTLCMD;
  1892. }
  1893. return 0;
  1894. }
  1895. /* Set new termios settings
  1896. *
  1897. * Arguments:
  1898. *
  1899. * tty pointer to tty structure
  1900. * termios pointer to buffer to hold returned old termios
  1901. */
  1902. static void mgslpc_set_termios(struct tty_struct *tty, struct ktermios *old_termios)
  1903. {
  1904. MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
  1905. unsigned long flags;
  1906. if (debug_level >= DEBUG_LEVEL_INFO)
  1907. printk("%s(%d):mgslpc_set_termios %s\n", __FILE__, __LINE__,
  1908. tty->driver->name);
  1909. /* just return if nothing has changed */
  1910. if ((tty->termios.c_cflag == old_termios->c_cflag)
  1911. && (RELEVANT_IFLAG(tty->termios.c_iflag)
  1912. == RELEVANT_IFLAG(old_termios->c_iflag)))
  1913. return;
  1914. mgslpc_change_params(info, tty);
  1915. /* Handle transition to B0 status */
  1916. if ((old_termios->c_cflag & CBAUD) && !C_BAUD(tty)) {
  1917. info->serial_signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
  1918. spin_lock_irqsave(&info->lock, flags);
  1919. set_signals(info);
  1920. spin_unlock_irqrestore(&info->lock, flags);
  1921. }
  1922. /* Handle transition away from B0 status */
  1923. if (!(old_termios->c_cflag & CBAUD) && C_BAUD(tty)) {
  1924. info->serial_signals |= SerialSignal_DTR;
  1925. if (!C_CRTSCTS(tty) || !tty_throttled(tty))
  1926. info->serial_signals |= SerialSignal_RTS;
  1927. spin_lock_irqsave(&info->lock, flags);
  1928. set_signals(info);
  1929. spin_unlock_irqrestore(&info->lock, flags);
  1930. }
  1931. /* Handle turning off CRTSCTS */
  1932. if (old_termios->c_cflag & CRTSCTS && !C_CRTSCTS(tty)) {
  1933. tty->hw_stopped = 0;
  1934. tx_release(tty);
  1935. }
  1936. }
  1937. static void mgslpc_close(struct tty_struct *tty, struct file * filp)
  1938. {
  1939. MGSLPC_INFO * info = (MGSLPC_INFO *)tty->driver_data;
  1940. struct tty_port *port = &info->port;
  1941. if (mgslpc_paranoia_check(info, tty->name, "mgslpc_close"))
  1942. return;
  1943. if (debug_level >= DEBUG_LEVEL_INFO)
  1944. printk("%s(%d):mgslpc_close(%s) entry, count=%d\n",
  1945. __FILE__, __LINE__, info->device_name, port->count);
  1946. if (tty_port_close_start(port, tty, filp) == 0)
  1947. goto cleanup;
  1948. if (tty_port_initialized(port))
  1949. mgslpc_wait_until_sent(tty, info->timeout);
  1950. mgslpc_flush_buffer(tty);
  1951. tty_ldisc_flush(tty);
  1952. shutdown(info, tty);
  1953. tty_port_close_end(port, tty);
  1954. tty_port_tty_set(port, NULL);
  1955. cleanup:
  1956. if (debug_level >= DEBUG_LEVEL_INFO)
  1957. printk("%s(%d):mgslpc_close(%s) exit, count=%d\n", __FILE__, __LINE__,
  1958. tty->driver->name, port->count);
  1959. }
  1960. /* Wait until the transmitter is empty.
  1961. */
  1962. static void mgslpc_wait_until_sent(struct tty_struct *tty, int timeout)
  1963. {
  1964. MGSLPC_INFO * info = (MGSLPC_INFO *)tty->driver_data;
  1965. unsigned long orig_jiffies, char_time;
  1966. if (!info)
  1967. return;
  1968. if (debug_level >= DEBUG_LEVEL_INFO)
  1969. printk("%s(%d):mgslpc_wait_until_sent(%s) entry\n",
  1970. __FILE__, __LINE__, info->device_name);
  1971. if (mgslpc_paranoia_check(info, tty->name, "mgslpc_wait_until_sent"))
  1972. return;
  1973. if (!tty_port_initialized(&info->port))
  1974. goto exit;
  1975. orig_jiffies = jiffies;
  1976. /* Set check interval to 1/5 of estimated time to
  1977. * send a character, and make it at least 1. The check
  1978. * interval should also be less than the timeout.
  1979. * Note: use tight timings here to satisfy the NIST-PCTS.
  1980. */
  1981. if (info->params.data_rate) {
  1982. char_time = info->timeout/(32 * 5);
  1983. if (!char_time)
  1984. char_time++;
  1985. } else
  1986. char_time = 1;
  1987. if (timeout)
  1988. char_time = min_t(unsigned long, char_time, timeout);
  1989. if (info->params.mode == MGSL_MODE_HDLC) {
  1990. while (info->tx_active) {
  1991. msleep_interruptible(jiffies_to_msecs(char_time));
  1992. if (signal_pending(current))
  1993. break;
  1994. if (timeout && time_after(jiffies, orig_jiffies + timeout))
  1995. break;
  1996. }
  1997. } else {
  1998. while ((info->tx_count || info->tx_active) &&
  1999. info->tx_enabled) {
  2000. msleep_interruptible(jiffies_to_msecs(char_time));
  2001. if (signal_pending(current))
  2002. break;
  2003. if (timeout && time_after(jiffies, orig_jiffies + timeout))
  2004. break;
  2005. }
  2006. }
  2007. exit:
  2008. if (debug_level >= DEBUG_LEVEL_INFO)
  2009. printk("%s(%d):mgslpc_wait_until_sent(%s) exit\n",
  2010. __FILE__, __LINE__, info->device_name);
  2011. }
  2012. /* Called by tty_hangup() when a hangup is signaled.
  2013. * This is the same as closing all open files for the port.
  2014. */
  2015. static void mgslpc_hangup(struct tty_struct *tty)
  2016. {
  2017. MGSLPC_INFO * info = (MGSLPC_INFO *)tty->driver_data;
  2018. if (debug_level >= DEBUG_LEVEL_INFO)
  2019. printk("%s(%d):mgslpc_hangup(%s)\n",
  2020. __FILE__, __LINE__, info->device_name);
  2021. if (mgslpc_paranoia_check(info, tty->name, "mgslpc_hangup"))
  2022. return;
  2023. mgslpc_flush_buffer(tty);
  2024. shutdown(info, tty);
  2025. tty_port_hangup(&info->port);
  2026. }
  2027. static int carrier_raised(struct tty_port *port)
  2028. {
  2029. MGSLPC_INFO *info = container_of(port, MGSLPC_INFO, port);
  2030. unsigned long flags;
  2031. spin_lock_irqsave(&info->lock, flags);
  2032. get_signals(info);
  2033. spin_unlock_irqrestore(&info->lock, flags);
  2034. if (info->serial_signals & SerialSignal_DCD)
  2035. return 1;
  2036. return 0;
  2037. }
  2038. static void dtr_rts(struct tty_port *port, int onoff)
  2039. {
  2040. MGSLPC_INFO *info = container_of(port, MGSLPC_INFO, port);
  2041. unsigned long flags;
  2042. spin_lock_irqsave(&info->lock, flags);
  2043. if (onoff)
  2044. info->serial_signals |= SerialSignal_RTS | SerialSignal_DTR;
  2045. else
  2046. info->serial_signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
  2047. set_signals(info);
  2048. spin_unlock_irqrestore(&info->lock, flags);
  2049. }
  2050. static int mgslpc_open(struct tty_struct *tty, struct file * filp)
  2051. {
  2052. MGSLPC_INFO *info;
  2053. struct tty_port *port;
  2054. int retval, line;
  2055. unsigned long flags;
  2056. /* verify range of specified line number */
  2057. line = tty->index;
  2058. if (line >= mgslpc_device_count) {
  2059. printk("%s(%d):mgslpc_open with invalid line #%d.\n",
  2060. __FILE__, __LINE__, line);
  2061. return -ENODEV;
  2062. }
  2063. /* find the info structure for the specified line */
  2064. info = mgslpc_device_list;
  2065. while(info && info->line != line)
  2066. info = info->next_device;
  2067. if (mgslpc_paranoia_check(info, tty->name, "mgslpc_open"))
  2068. return -ENODEV;
  2069. port = &info->port;
  2070. tty->driver_data = info;
  2071. tty_port_tty_set(port, tty);
  2072. if (debug_level >= DEBUG_LEVEL_INFO)
  2073. printk("%s(%d):mgslpc_open(%s), old ref count = %d\n",
  2074. __FILE__, __LINE__, tty->driver->name, port->count);
  2075. port->low_latency = (port->flags & ASYNC_LOW_LATENCY) ? 1 : 0;
  2076. spin_lock_irqsave(&info->netlock, flags);
  2077. if (info->netcount) {
  2078. retval = -EBUSY;
  2079. spin_unlock_irqrestore(&info->netlock, flags);
  2080. goto cleanup;
  2081. }
  2082. spin_lock(&port->lock);
  2083. port->count++;
  2084. spin_unlock(&port->lock);
  2085. spin_unlock_irqrestore(&info->netlock, flags);
  2086. if (port->count == 1) {
  2087. /* 1st open on this device, init hardware */
  2088. retval = startup(info, tty);
  2089. if (retval < 0)
  2090. goto cleanup;
  2091. }
  2092. retval = tty_port_block_til_ready(&info->port, tty, filp);
  2093. if (retval) {
  2094. if (debug_level >= DEBUG_LEVEL_INFO)
  2095. printk("%s(%d):block_til_ready(%s) returned %d\n",
  2096. __FILE__, __LINE__, info->device_name, retval);
  2097. goto cleanup;
  2098. }
  2099. if (debug_level >= DEBUG_LEVEL_INFO)
  2100. printk("%s(%d):mgslpc_open(%s) success\n",
  2101. __FILE__, __LINE__, info->device_name);
  2102. retval = 0;
  2103. cleanup:
  2104. return retval;
  2105. }
  2106. /*
  2107. * /proc fs routines....
  2108. */
  2109. static inline void line_info(struct seq_file *m, MGSLPC_INFO *info)
  2110. {
  2111. char stat_buf[30];
  2112. unsigned long flags;
  2113. seq_printf(m, "%s:io:%04X irq:%d",
  2114. info->device_name, info->io_base, info->irq_level);
  2115. /* output current serial signal states */
  2116. spin_lock_irqsave(&info->lock, flags);
  2117. get_signals(info);
  2118. spin_unlock_irqrestore(&info->lock, flags);
  2119. stat_buf[0] = 0;
  2120. stat_buf[1] = 0;
  2121. if (info->serial_signals & SerialSignal_RTS)
  2122. strcat(stat_buf, "|RTS");
  2123. if (info->serial_signals & SerialSignal_CTS)
  2124. strcat(stat_buf, "|CTS");
  2125. if (info->serial_signals & SerialSignal_DTR)
  2126. strcat(stat_buf, "|DTR");
  2127. if (info->serial_signals & SerialSignal_DSR)
  2128. strcat(stat_buf, "|DSR");
  2129. if (info->serial_signals & SerialSignal_DCD)
  2130. strcat(stat_buf, "|CD");
  2131. if (info->serial_signals & SerialSignal_RI)
  2132. strcat(stat_buf, "|RI");
  2133. if (info->params.mode == MGSL_MODE_HDLC) {
  2134. seq_printf(m, " HDLC txok:%d rxok:%d",
  2135. info->icount.txok, info->icount.rxok);
  2136. if (info->icount.txunder)
  2137. seq_printf(m, " txunder:%d", info->icount.txunder);
  2138. if (info->icount.txabort)
  2139. seq_printf(m, " txabort:%d", info->icount.txabort);
  2140. if (info->icount.rxshort)
  2141. seq_printf(m, " rxshort:%d", info->icount.rxshort);
  2142. if (info->icount.rxlong)
  2143. seq_printf(m, " rxlong:%d", info->icount.rxlong);
  2144. if (info->icount.rxover)
  2145. seq_printf(m, " rxover:%d", info->icount.rxover);
  2146. if (info->icount.rxcrc)
  2147. seq_printf(m, " rxcrc:%d", info->icount.rxcrc);
  2148. } else {
  2149. seq_printf(m, " ASYNC tx:%d rx:%d",
  2150. info->icount.tx, info->icount.rx);
  2151. if (info->icount.frame)
  2152. seq_printf(m, " fe:%d", info->icount.frame);
  2153. if (info->icount.parity)
  2154. seq_printf(m, " pe:%d", info->icount.parity);
  2155. if (info->icount.brk)
  2156. seq_printf(m, " brk:%d", info->icount.brk);
  2157. if (info->icount.overrun)
  2158. seq_printf(m, " oe:%d", info->icount.overrun);
  2159. }
  2160. /* Append serial signal status to end */
  2161. seq_printf(m, " %s\n", stat_buf+1);
  2162. seq_printf(m, "txactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
  2163. info->tx_active,info->bh_requested,info->bh_running,
  2164. info->pending_bh);
  2165. }
  2166. /* Called to print information about devices
  2167. */
  2168. static int mgslpc_proc_show(struct seq_file *m, void *v)
  2169. {
  2170. MGSLPC_INFO *info;
  2171. seq_printf(m, "synclink driver:%s\n", driver_version);
  2172. info = mgslpc_device_list;
  2173. while (info) {
  2174. line_info(m, info);
  2175. info = info->next_device;
  2176. }
  2177. return 0;
  2178. }
  2179. static int rx_alloc_buffers(MGSLPC_INFO *info)
  2180. {
  2181. /* each buffer has header and data */
  2182. info->rx_buf_size = sizeof(RXBUF) + info->max_frame_size;
  2183. /* calculate total allocation size for 8 buffers */
  2184. info->rx_buf_total_size = info->rx_buf_size * 8;
  2185. /* limit total allocated memory */
  2186. if (info->rx_buf_total_size > 0x10000)
  2187. info->rx_buf_total_size = 0x10000;
  2188. /* calculate number of buffers */
  2189. info->rx_buf_count = info->rx_buf_total_size / info->rx_buf_size;
  2190. info->rx_buf = kmalloc(info->rx_buf_total_size, GFP_KERNEL);
  2191. if (info->rx_buf == NULL)
  2192. return -ENOMEM;
  2193. /* unused flag buffer to satisfy receive_buf calling interface */
  2194. info->flag_buf = kzalloc(info->max_frame_size, GFP_KERNEL);
  2195. if (!info->flag_buf) {
  2196. kfree(info->rx_buf);
  2197. info->rx_buf = NULL;
  2198. return -ENOMEM;
  2199. }
  2200. rx_reset_buffers(info);
  2201. return 0;
  2202. }
  2203. static void rx_free_buffers(MGSLPC_INFO *info)
  2204. {
  2205. kfree(info->rx_buf);
  2206. info->rx_buf = NULL;
  2207. kfree(info->flag_buf);
  2208. info->flag_buf = NULL;
  2209. }
  2210. static int claim_resources(MGSLPC_INFO *info)
  2211. {
  2212. if (rx_alloc_buffers(info) < 0) {
  2213. printk("Can't allocate rx buffer %s\n", info->device_name);
  2214. release_resources(info);
  2215. return -ENODEV;
  2216. }
  2217. return 0;
  2218. }
  2219. static void release_resources(MGSLPC_INFO *info)
  2220. {
  2221. if (debug_level >= DEBUG_LEVEL_INFO)
  2222. printk("release_resources(%s)\n", info->device_name);
  2223. rx_free_buffers(info);
  2224. }
  2225. /* Add the specified device instance data structure to the
  2226. * global linked list of devices and increment the device count.
  2227. *
  2228. * Arguments: info pointer to device instance data
  2229. */
  2230. static int mgslpc_add_device(MGSLPC_INFO *info)
  2231. {
  2232. MGSLPC_INFO *current_dev = NULL;
  2233. struct device *tty_dev;
  2234. int ret;
  2235. info->next_device = NULL;
  2236. info->line = mgslpc_device_count;
  2237. sprintf(info->device_name,"ttySLP%d",info->line);
  2238. if (info->line < MAX_DEVICE_COUNT) {
  2239. if (maxframe[info->line])
  2240. info->max_frame_size = maxframe[info->line];
  2241. }
  2242. mgslpc_device_count++;
  2243. if (!mgslpc_device_list)
  2244. mgslpc_device_list = info;
  2245. else {
  2246. current_dev = mgslpc_device_list;
  2247. while (current_dev->next_device)
  2248. current_dev = current_dev->next_device;
  2249. current_dev->next_device = info;
  2250. }
  2251. if (info->max_frame_size < 4096)
  2252. info->max_frame_size = 4096;
  2253. else if (info->max_frame_size > 65535)
  2254. info->max_frame_size = 65535;
  2255. printk("SyncLink PC Card %s:IO=%04X IRQ=%d\n",
  2256. info->device_name, info->io_base, info->irq_level);
  2257. #if SYNCLINK_GENERIC_HDLC
  2258. ret = hdlcdev_init(info);
  2259. if (ret != 0)
  2260. goto failed;
  2261. #endif
  2262. tty_dev = tty_port_register_device(&info->port, serial_driver, info->line,
  2263. &info->p_dev->dev);
  2264. if (IS_ERR(tty_dev)) {
  2265. ret = PTR_ERR(tty_dev);
  2266. #if SYNCLINK_GENERIC_HDLC
  2267. hdlcdev_exit(info);
  2268. #endif
  2269. goto failed;
  2270. }
  2271. return 0;
  2272. failed:
  2273. if (current_dev)
  2274. current_dev->next_device = NULL;
  2275. else
  2276. mgslpc_device_list = NULL;
  2277. mgslpc_device_count--;
  2278. return ret;
  2279. }
  2280. static void mgslpc_remove_device(MGSLPC_INFO *remove_info)
  2281. {
  2282. MGSLPC_INFO *info = mgslpc_device_list;
  2283. MGSLPC_INFO *last = NULL;
  2284. while(info) {
  2285. if (info == remove_info) {
  2286. if (last)
  2287. last->next_device = info->next_device;
  2288. else
  2289. mgslpc_device_list = info->next_device;
  2290. tty_unregister_device(serial_driver, info->line);
  2291. #if SYNCLINK_GENERIC_HDLC
  2292. hdlcdev_exit(info);
  2293. #endif
  2294. release_resources(info);
  2295. tty_port_destroy(&info->port);
  2296. kfree(info);
  2297. mgslpc_device_count--;
  2298. return;
  2299. }
  2300. last = info;
  2301. info = info->next_device;
  2302. }
  2303. }
  2304. static const struct pcmcia_device_id mgslpc_ids[] = {
  2305. PCMCIA_DEVICE_MANF_CARD(0x02c5, 0x0050),
  2306. PCMCIA_DEVICE_NULL
  2307. };
  2308. MODULE_DEVICE_TABLE(pcmcia, mgslpc_ids);
  2309. static struct pcmcia_driver mgslpc_driver = {
  2310. .owner = THIS_MODULE,
  2311. .name = "synclink_cs",
  2312. .probe = mgslpc_probe,
  2313. .remove = mgslpc_detach,
  2314. .id_table = mgslpc_ids,
  2315. .suspend = mgslpc_suspend,
  2316. .resume = mgslpc_resume,
  2317. };
  2318. static const struct tty_operations mgslpc_ops = {
  2319. .open = mgslpc_open,
  2320. .close = mgslpc_close,
  2321. .write = mgslpc_write,
  2322. .put_char = mgslpc_put_char,
  2323. .flush_chars = mgslpc_flush_chars,
  2324. .write_room = mgslpc_write_room,
  2325. .chars_in_buffer = mgslpc_chars_in_buffer,
  2326. .flush_buffer = mgslpc_flush_buffer,
  2327. .ioctl = mgslpc_ioctl,
  2328. .throttle = mgslpc_throttle,
  2329. .unthrottle = mgslpc_unthrottle,
  2330. .send_xchar = mgslpc_send_xchar,
  2331. .break_ctl = mgslpc_break,
  2332. .wait_until_sent = mgslpc_wait_until_sent,
  2333. .set_termios = mgslpc_set_termios,
  2334. .stop = tx_pause,
  2335. .start = tx_release,
  2336. .hangup = mgslpc_hangup,
  2337. .tiocmget = tiocmget,
  2338. .tiocmset = tiocmset,
  2339. .get_icount = mgslpc_get_icount,
  2340. .proc_show = mgslpc_proc_show,
  2341. };
  2342. static int __init synclink_cs_init(void)
  2343. {
  2344. int rc;
  2345. if (break_on_load) {
  2346. mgslpc_get_text_ptr();
  2347. BREAKPOINT();
  2348. }
  2349. serial_driver = tty_alloc_driver(MAX_DEVICE_COUNT,
  2350. TTY_DRIVER_REAL_RAW |
  2351. TTY_DRIVER_DYNAMIC_DEV);
  2352. if (IS_ERR(serial_driver)) {
  2353. rc = PTR_ERR(serial_driver);
  2354. goto err;
  2355. }
  2356. /* Initialize the tty_driver structure */
  2357. serial_driver->driver_name = "synclink_cs";
  2358. serial_driver->name = "ttySLP";
  2359. serial_driver->major = ttymajor;
  2360. serial_driver->minor_start = 64;
  2361. serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
  2362. serial_driver->subtype = SERIAL_TYPE_NORMAL;
  2363. serial_driver->init_termios = tty_std_termios;
  2364. serial_driver->init_termios.c_cflag =
  2365. B9600 | CS8 | CREAD | HUPCL | CLOCAL;
  2366. tty_set_operations(serial_driver, &mgslpc_ops);
  2367. rc = tty_register_driver(serial_driver);
  2368. if (rc < 0) {
  2369. printk(KERN_ERR "%s(%d):Couldn't register serial driver\n",
  2370. __FILE__, __LINE__);
  2371. goto err_put_tty;
  2372. }
  2373. rc = pcmcia_register_driver(&mgslpc_driver);
  2374. if (rc < 0)
  2375. goto err_unreg_tty;
  2376. printk(KERN_INFO "%s %s, tty major#%d\n", driver_name, driver_version,
  2377. serial_driver->major);
  2378. return 0;
  2379. err_unreg_tty:
  2380. tty_unregister_driver(serial_driver);
  2381. err_put_tty:
  2382. put_tty_driver(serial_driver);
  2383. err:
  2384. return rc;
  2385. }
  2386. static void __exit synclink_cs_exit(void)
  2387. {
  2388. pcmcia_unregister_driver(&mgslpc_driver);
  2389. tty_unregister_driver(serial_driver);
  2390. put_tty_driver(serial_driver);
  2391. }
  2392. module_init(synclink_cs_init);
  2393. module_exit(synclink_cs_exit);
  2394. static void mgslpc_set_rate(MGSLPC_INFO *info, unsigned char channel, unsigned int rate)
  2395. {
  2396. unsigned int M, N;
  2397. unsigned char val;
  2398. /* note:standard BRG mode is broken in V3.2 chip
  2399. * so enhanced mode is always used
  2400. */
  2401. if (rate) {
  2402. N = 3686400 / rate;
  2403. if (!N)
  2404. N = 1;
  2405. N >>= 1;
  2406. for (M = 1; N > 64 && M < 16; M++)
  2407. N >>= 1;
  2408. N--;
  2409. /* BGR[5..0] = N
  2410. * BGR[9..6] = M
  2411. * BGR[7..0] contained in BGR register
  2412. * BGR[9..8] contained in CCR2[7..6]
  2413. * divisor = (N+1)*2^M
  2414. *
  2415. * Note: M *must* not be zero (causes asymetric duty cycle)
  2416. */
  2417. write_reg(info, (unsigned char) (channel + BGR),
  2418. (unsigned char) ((M << 6) + N));
  2419. val = read_reg(info, (unsigned char) (channel + CCR2)) & 0x3f;
  2420. val |= ((M << 4) & 0xc0);
  2421. write_reg(info, (unsigned char) (channel + CCR2), val);
  2422. }
  2423. }
  2424. /* Enabled the AUX clock output at the specified frequency.
  2425. */
  2426. static void enable_auxclk(MGSLPC_INFO *info)
  2427. {
  2428. unsigned char val;
  2429. /* MODE
  2430. *
  2431. * 07..06 MDS[1..0] 10 = transparent HDLC mode
  2432. * 05 ADM Address Mode, 0 = no addr recognition
  2433. * 04 TMD Timer Mode, 0 = external
  2434. * 03 RAC Receiver Active, 0 = inactive
  2435. * 02 RTS 0=RTS active during xmit, 1=RTS always active
  2436. * 01 TRS Timer Resolution, 1=512
  2437. * 00 TLP Test Loop, 0 = no loop
  2438. *
  2439. * 1000 0010
  2440. */
  2441. val = 0x82;
  2442. /* channel B RTS is used to enable AUXCLK driver on SP505 */
  2443. if (info->params.mode == MGSL_MODE_HDLC && info->params.clock_speed)
  2444. val |= BIT2;
  2445. write_reg(info, CHB + MODE, val);
  2446. /* CCR0
  2447. *
  2448. * 07 PU Power Up, 1=active, 0=power down
  2449. * 06 MCE Master Clock Enable, 1=enabled
  2450. * 05 Reserved, 0
  2451. * 04..02 SC[2..0] Encoding
  2452. * 01..00 SM[1..0] Serial Mode, 00=HDLC
  2453. *
  2454. * 11000000
  2455. */
  2456. write_reg(info, CHB + CCR0, 0xc0);
  2457. /* CCR1
  2458. *
  2459. * 07 SFLG Shared Flag, 0 = disable shared flags
  2460. * 06 GALP Go Active On Loop, 0 = not used
  2461. * 05 GLP Go On Loop, 0 = not used
  2462. * 04 ODS Output Driver Select, 1=TxD is push-pull output
  2463. * 03 ITF Interframe Time Fill, 0=mark, 1=flag
  2464. * 02..00 CM[2..0] Clock Mode
  2465. *
  2466. * 0001 0111
  2467. */
  2468. write_reg(info, CHB + CCR1, 0x17);
  2469. /* CCR2 (Channel B)
  2470. *
  2471. * 07..06 BGR[9..8] Baud rate bits 9..8
  2472. * 05 BDF Baud rate divisor factor, 0=1, 1=BGR value
  2473. * 04 SSEL Clock source select, 1=submode b
  2474. * 03 TOE 0=TxCLK is input, 1=TxCLK is output
  2475. * 02 RWX Read/Write Exchange 0=disabled
  2476. * 01 C32, CRC select, 0=CRC-16, 1=CRC-32
  2477. * 00 DIV, data inversion 0=disabled, 1=enabled
  2478. *
  2479. * 0011 1000
  2480. */
  2481. if (info->params.mode == MGSL_MODE_HDLC && info->params.clock_speed)
  2482. write_reg(info, CHB + CCR2, 0x38);
  2483. else
  2484. write_reg(info, CHB + CCR2, 0x30);
  2485. /* CCR4
  2486. *
  2487. * 07 MCK4 Master Clock Divide by 4, 1=enabled
  2488. * 06 EBRG Enhanced Baud Rate Generator Mode, 1=enabled
  2489. * 05 TST1 Test Pin, 0=normal operation
  2490. * 04 ICD Ivert Carrier Detect, 1=enabled (active low)
  2491. * 03..02 Reserved, must be 0
  2492. * 01..00 RFT[1..0] RxFIFO Threshold 00=32 bytes
  2493. *
  2494. * 0101 0000
  2495. */
  2496. write_reg(info, CHB + CCR4, 0x50);
  2497. /* if auxclk not enabled, set internal BRG so
  2498. * CTS transitions can be detected (requires TxC)
  2499. */
  2500. if (info->params.mode == MGSL_MODE_HDLC && info->params.clock_speed)
  2501. mgslpc_set_rate(info, CHB, info->params.clock_speed);
  2502. else
  2503. mgslpc_set_rate(info, CHB, 921600);
  2504. }
  2505. static void loopback_enable(MGSLPC_INFO *info)
  2506. {
  2507. unsigned char val;
  2508. /* CCR1:02..00 CM[2..0] Clock Mode = 111 (clock mode 7) */
  2509. val = read_reg(info, CHA + CCR1) | (BIT2 | BIT1 | BIT0);
  2510. write_reg(info, CHA + CCR1, val);
  2511. /* CCR2:04 SSEL Clock source select, 1=submode b */
  2512. val = read_reg(info, CHA + CCR2) | (BIT4 | BIT5);
  2513. write_reg(info, CHA + CCR2, val);
  2514. /* set LinkSpeed if available, otherwise default to 2Mbps */
  2515. if (info->params.clock_speed)
  2516. mgslpc_set_rate(info, CHA, info->params.clock_speed);
  2517. else
  2518. mgslpc_set_rate(info, CHA, 1843200);
  2519. /* MODE:00 TLP Test Loop, 1=loopback enabled */
  2520. val = read_reg(info, CHA + MODE) | BIT0;
  2521. write_reg(info, CHA + MODE, val);
  2522. }
  2523. static void hdlc_mode(MGSLPC_INFO *info)
  2524. {
  2525. unsigned char val;
  2526. unsigned char clkmode, clksubmode;
  2527. /* disable all interrupts */
  2528. irq_disable(info, CHA, 0xffff);
  2529. irq_disable(info, CHB, 0xffff);
  2530. port_irq_disable(info, 0xff);
  2531. /* assume clock mode 0a, rcv=RxC xmt=TxC */
  2532. clkmode = clksubmode = 0;
  2533. if (info->params.flags & HDLC_FLAG_RXC_DPLL
  2534. && info->params.flags & HDLC_FLAG_TXC_DPLL) {
  2535. /* clock mode 7a, rcv = DPLL, xmt = DPLL */
  2536. clkmode = 7;
  2537. } else if (info->params.flags & HDLC_FLAG_RXC_BRG
  2538. && info->params.flags & HDLC_FLAG_TXC_BRG) {
  2539. /* clock mode 7b, rcv = BRG, xmt = BRG */
  2540. clkmode = 7;
  2541. clksubmode = 1;
  2542. } else if (info->params.flags & HDLC_FLAG_RXC_DPLL) {
  2543. if (info->params.flags & HDLC_FLAG_TXC_BRG) {
  2544. /* clock mode 6b, rcv = DPLL, xmt = BRG/16 */
  2545. clkmode = 6;
  2546. clksubmode = 1;
  2547. } else {
  2548. /* clock mode 6a, rcv = DPLL, xmt = TxC */
  2549. clkmode = 6;
  2550. }
  2551. } else if (info->params.flags & HDLC_FLAG_TXC_BRG) {
  2552. /* clock mode 0b, rcv = RxC, xmt = BRG */
  2553. clksubmode = 1;
  2554. }
  2555. /* MODE
  2556. *
  2557. * 07..06 MDS[1..0] 10 = transparent HDLC mode
  2558. * 05 ADM Address Mode, 0 = no addr recognition
  2559. * 04 TMD Timer Mode, 0 = external
  2560. * 03 RAC Receiver Active, 0 = inactive
  2561. * 02 RTS 0=RTS active during xmit, 1=RTS always active
  2562. * 01 TRS Timer Resolution, 1=512
  2563. * 00 TLP Test Loop, 0 = no loop
  2564. *
  2565. * 1000 0010
  2566. */
  2567. val = 0x82;
  2568. if (info->params.loopback)
  2569. val |= BIT0;
  2570. /* preserve RTS state */
  2571. if (info->serial_signals & SerialSignal_RTS)
  2572. val |= BIT2;
  2573. write_reg(info, CHA + MODE, val);
  2574. /* CCR0
  2575. *
  2576. * 07 PU Power Up, 1=active, 0=power down
  2577. * 06 MCE Master Clock Enable, 1=enabled
  2578. * 05 Reserved, 0
  2579. * 04..02 SC[2..0] Encoding
  2580. * 01..00 SM[1..0] Serial Mode, 00=HDLC
  2581. *
  2582. * 11000000
  2583. */
  2584. val = 0xc0;
  2585. switch (info->params.encoding)
  2586. {
  2587. case HDLC_ENCODING_NRZI:
  2588. val |= BIT3;
  2589. break;
  2590. case HDLC_ENCODING_BIPHASE_SPACE:
  2591. val |= BIT4;
  2592. break; // FM0
  2593. case HDLC_ENCODING_BIPHASE_MARK:
  2594. val |= BIT4 | BIT2;
  2595. break; // FM1
  2596. case HDLC_ENCODING_BIPHASE_LEVEL:
  2597. val |= BIT4 | BIT3;
  2598. break; // Manchester
  2599. }
  2600. write_reg(info, CHA + CCR0, val);
  2601. /* CCR1
  2602. *
  2603. * 07 SFLG Shared Flag, 0 = disable shared flags
  2604. * 06 GALP Go Active On Loop, 0 = not used
  2605. * 05 GLP Go On Loop, 0 = not used
  2606. * 04 ODS Output Driver Select, 1=TxD is push-pull output
  2607. * 03 ITF Interframe Time Fill, 0=mark, 1=flag
  2608. * 02..00 CM[2..0] Clock Mode
  2609. *
  2610. * 0001 0000
  2611. */
  2612. val = 0x10 + clkmode;
  2613. write_reg(info, CHA + CCR1, val);
  2614. /* CCR2
  2615. *
  2616. * 07..06 BGR[9..8] Baud rate bits 9..8
  2617. * 05 BDF Baud rate divisor factor, 0=1, 1=BGR value
  2618. * 04 SSEL Clock source select, 1=submode b
  2619. * 03 TOE 0=TxCLK is input, 0=TxCLK is input
  2620. * 02 RWX Read/Write Exchange 0=disabled
  2621. * 01 C32, CRC select, 0=CRC-16, 1=CRC-32
  2622. * 00 DIV, data inversion 0=disabled, 1=enabled
  2623. *
  2624. * 0000 0000
  2625. */
  2626. val = 0x00;
  2627. if (clkmode == 2 || clkmode == 3 || clkmode == 6
  2628. || clkmode == 7 || (clkmode == 0 && clksubmode == 1))
  2629. val |= BIT5;
  2630. if (clksubmode)
  2631. val |= BIT4;
  2632. if (info->params.crc_type == HDLC_CRC_32_CCITT)
  2633. val |= BIT1;
  2634. if (info->params.encoding == HDLC_ENCODING_NRZB)
  2635. val |= BIT0;
  2636. write_reg(info, CHA + CCR2, val);
  2637. /* CCR3
  2638. *
  2639. * 07..06 PRE[1..0] Preamble count 00=1, 01=2, 10=4, 11=8
  2640. * 05 EPT Enable preamble transmission, 1=enabled
  2641. * 04 RADD Receive address pushed to FIFO, 0=disabled
  2642. * 03 CRL CRC Reset Level, 0=FFFF
  2643. * 02 RCRC Rx CRC 0=On 1=Off
  2644. * 01 TCRC Tx CRC 0=On 1=Off
  2645. * 00 PSD DPLL Phase Shift Disable
  2646. *
  2647. * 0000 0000
  2648. */
  2649. val = 0x00;
  2650. if (info->params.crc_type == HDLC_CRC_NONE)
  2651. val |= BIT2 | BIT1;
  2652. if (info->params.preamble != HDLC_PREAMBLE_PATTERN_NONE)
  2653. val |= BIT5;
  2654. switch (info->params.preamble_length)
  2655. {
  2656. case HDLC_PREAMBLE_LENGTH_16BITS:
  2657. val |= BIT6;
  2658. break;
  2659. case HDLC_PREAMBLE_LENGTH_32BITS:
  2660. val |= BIT6;
  2661. break;
  2662. case HDLC_PREAMBLE_LENGTH_64BITS:
  2663. val |= BIT7 | BIT6;
  2664. break;
  2665. }
  2666. write_reg(info, CHA + CCR3, val);
  2667. /* PRE - Preamble pattern */
  2668. val = 0;
  2669. switch (info->params.preamble)
  2670. {
  2671. case HDLC_PREAMBLE_PATTERN_FLAGS: val = 0x7e; break;
  2672. case HDLC_PREAMBLE_PATTERN_10: val = 0xaa; break;
  2673. case HDLC_PREAMBLE_PATTERN_01: val = 0x55; break;
  2674. case HDLC_PREAMBLE_PATTERN_ONES: val = 0xff; break;
  2675. }
  2676. write_reg(info, CHA + PRE, val);
  2677. /* CCR4
  2678. *
  2679. * 07 MCK4 Master Clock Divide by 4, 1=enabled
  2680. * 06 EBRG Enhanced Baud Rate Generator Mode, 1=enabled
  2681. * 05 TST1 Test Pin, 0=normal operation
  2682. * 04 ICD Ivert Carrier Detect, 1=enabled (active low)
  2683. * 03..02 Reserved, must be 0
  2684. * 01..00 RFT[1..0] RxFIFO Threshold 00=32 bytes
  2685. *
  2686. * 0101 0000
  2687. */
  2688. val = 0x50;
  2689. write_reg(info, CHA + CCR4, val);
  2690. if (info->params.flags & HDLC_FLAG_RXC_DPLL)
  2691. mgslpc_set_rate(info, CHA, info->params.clock_speed * 16);
  2692. else
  2693. mgslpc_set_rate(info, CHA, info->params.clock_speed);
  2694. /* RLCR Receive length check register
  2695. *
  2696. * 7 1=enable receive length check
  2697. * 6..0 Max frame length = (RL + 1) * 32
  2698. */
  2699. write_reg(info, CHA + RLCR, 0);
  2700. /* XBCH Transmit Byte Count High
  2701. *
  2702. * 07 DMA mode, 0 = interrupt driven
  2703. * 06 NRM, 0=ABM (ignored)
  2704. * 05 CAS Carrier Auto Start
  2705. * 04 XC Transmit Continuously (ignored)
  2706. * 03..00 XBC[10..8] Transmit byte count bits 10..8
  2707. *
  2708. * 0000 0000
  2709. */
  2710. val = 0x00;
  2711. if (info->params.flags & HDLC_FLAG_AUTO_DCD)
  2712. val |= BIT5;
  2713. write_reg(info, CHA + XBCH, val);
  2714. enable_auxclk(info);
  2715. if (info->params.loopback || info->testing_irq)
  2716. loopback_enable(info);
  2717. if (info->params.flags & HDLC_FLAG_AUTO_CTS)
  2718. {
  2719. irq_enable(info, CHB, IRQ_CTS);
  2720. /* PVR[3] 1=AUTO CTS active */
  2721. set_reg_bits(info, CHA + PVR, BIT3);
  2722. } else
  2723. clear_reg_bits(info, CHA + PVR, BIT3);
  2724. irq_enable(info, CHA,
  2725. IRQ_RXEOM | IRQ_RXFIFO | IRQ_ALLSENT |
  2726. IRQ_UNDERRUN | IRQ_TXFIFO);
  2727. issue_command(info, CHA, CMD_TXRESET + CMD_RXRESET);
  2728. wait_command_complete(info, CHA);
  2729. read_reg16(info, CHA + ISR); /* clear pending IRQs */
  2730. /* Master clock mode enabled above to allow reset commands
  2731. * to complete even if no data clocks are present.
  2732. *
  2733. * Disable master clock mode for normal communications because
  2734. * V3.2 of the ESCC2 has a bug that prevents the transmit all sent
  2735. * IRQ when in master clock mode.
  2736. *
  2737. * Leave master clock mode enabled for IRQ test because the
  2738. * timer IRQ used by the test can only happen in master clock mode.
  2739. */
  2740. if (!info->testing_irq)
  2741. clear_reg_bits(info, CHA + CCR0, BIT6);
  2742. tx_set_idle(info);
  2743. tx_stop(info);
  2744. rx_stop(info);
  2745. }
  2746. static void rx_stop(MGSLPC_INFO *info)
  2747. {
  2748. if (debug_level >= DEBUG_LEVEL_ISR)
  2749. printk("%s(%d):rx_stop(%s)\n",
  2750. __FILE__, __LINE__, info->device_name);
  2751. /* MODE:03 RAC Receiver Active, 0=inactive */
  2752. clear_reg_bits(info, CHA + MODE, BIT3);
  2753. info->rx_enabled = false;
  2754. info->rx_overflow = false;
  2755. }
  2756. static void rx_start(MGSLPC_INFO *info)
  2757. {
  2758. if (debug_level >= DEBUG_LEVEL_ISR)
  2759. printk("%s(%d):rx_start(%s)\n",
  2760. __FILE__, __LINE__, info->device_name);
  2761. rx_reset_buffers(info);
  2762. info->rx_enabled = false;
  2763. info->rx_overflow = false;
  2764. /* MODE:03 RAC Receiver Active, 1=active */
  2765. set_reg_bits(info, CHA + MODE, BIT3);
  2766. info->rx_enabled = true;
  2767. }
  2768. static void tx_start(MGSLPC_INFO *info, struct tty_struct *tty)
  2769. {
  2770. if (debug_level >= DEBUG_LEVEL_ISR)
  2771. printk("%s(%d):tx_start(%s)\n",
  2772. __FILE__, __LINE__, info->device_name);
  2773. if (info->tx_count) {
  2774. /* If auto RTS enabled and RTS is inactive, then assert */
  2775. /* RTS and set a flag indicating that the driver should */
  2776. /* negate RTS when the transmission completes. */
  2777. info->drop_rts_on_tx_done = false;
  2778. if (info->params.flags & HDLC_FLAG_AUTO_RTS) {
  2779. get_signals(info);
  2780. if (!(info->serial_signals & SerialSignal_RTS)) {
  2781. info->serial_signals |= SerialSignal_RTS;
  2782. set_signals(info);
  2783. info->drop_rts_on_tx_done = true;
  2784. }
  2785. }
  2786. if (info->params.mode == MGSL_MODE_ASYNC) {
  2787. if (!info->tx_active) {
  2788. info->tx_active = true;
  2789. tx_ready(info, tty);
  2790. }
  2791. } else {
  2792. info->tx_active = true;
  2793. tx_ready(info, tty);
  2794. mod_timer(&info->tx_timer, jiffies +
  2795. msecs_to_jiffies(5000));
  2796. }
  2797. }
  2798. if (!info->tx_enabled)
  2799. info->tx_enabled = true;
  2800. }
  2801. static void tx_stop(MGSLPC_INFO *info)
  2802. {
  2803. if (debug_level >= DEBUG_LEVEL_ISR)
  2804. printk("%s(%d):tx_stop(%s)\n",
  2805. __FILE__, __LINE__, info->device_name);
  2806. del_timer(&info->tx_timer);
  2807. info->tx_enabled = false;
  2808. info->tx_active = false;
  2809. }
  2810. /* Reset the adapter to a known state and prepare it for further use.
  2811. */
  2812. static void reset_device(MGSLPC_INFO *info)
  2813. {
  2814. /* power up both channels (set BIT7) */
  2815. write_reg(info, CHA + CCR0, 0x80);
  2816. write_reg(info, CHB + CCR0, 0x80);
  2817. write_reg(info, CHA + MODE, 0);
  2818. write_reg(info, CHB + MODE, 0);
  2819. /* disable all interrupts */
  2820. irq_disable(info, CHA, 0xffff);
  2821. irq_disable(info, CHB, 0xffff);
  2822. port_irq_disable(info, 0xff);
  2823. /* PCR Port Configuration Register
  2824. *
  2825. * 07..04 DEC[3..0] Serial I/F select outputs
  2826. * 03 output, 1=AUTO CTS control enabled
  2827. * 02 RI Ring Indicator input 0=active
  2828. * 01 DSR input 0=active
  2829. * 00 DTR output 0=active
  2830. *
  2831. * 0000 0110
  2832. */
  2833. write_reg(info, PCR, 0x06);
  2834. /* PVR Port Value Register
  2835. *
  2836. * 07..04 DEC[3..0] Serial I/F select (0000=disabled)
  2837. * 03 AUTO CTS output 1=enabled
  2838. * 02 RI Ring Indicator input
  2839. * 01 DSR input
  2840. * 00 DTR output (1=inactive)
  2841. *
  2842. * 0000 0001
  2843. */
  2844. // write_reg(info, PVR, PVR_DTR);
  2845. /* IPC Interrupt Port Configuration
  2846. *
  2847. * 07 VIS 1=Masked interrupts visible
  2848. * 06..05 Reserved, 0
  2849. * 04..03 SLA Slave address, 00 ignored
  2850. * 02 CASM Cascading Mode, 1=daisy chain
  2851. * 01..00 IC[1..0] Interrupt Config, 01=push-pull output, active low
  2852. *
  2853. * 0000 0101
  2854. */
  2855. write_reg(info, IPC, 0x05);
  2856. }
  2857. static void async_mode(MGSLPC_INFO *info)
  2858. {
  2859. unsigned char val;
  2860. /* disable all interrupts */
  2861. irq_disable(info, CHA, 0xffff);
  2862. irq_disable(info, CHB, 0xffff);
  2863. port_irq_disable(info, 0xff);
  2864. /* MODE
  2865. *
  2866. * 07 Reserved, 0
  2867. * 06 FRTS RTS State, 0=active
  2868. * 05 FCTS Flow Control on CTS
  2869. * 04 FLON Flow Control Enable
  2870. * 03 RAC Receiver Active, 0 = inactive
  2871. * 02 RTS 0=Auto RTS, 1=manual RTS
  2872. * 01 TRS Timer Resolution, 1=512
  2873. * 00 TLP Test Loop, 0 = no loop
  2874. *
  2875. * 0000 0110
  2876. */
  2877. val = 0x06;
  2878. if (info->params.loopback)
  2879. val |= BIT0;
  2880. /* preserve RTS state */
  2881. if (!(info->serial_signals & SerialSignal_RTS))
  2882. val |= BIT6;
  2883. write_reg(info, CHA + MODE, val);
  2884. /* CCR0
  2885. *
  2886. * 07 PU Power Up, 1=active, 0=power down
  2887. * 06 MCE Master Clock Enable, 1=enabled
  2888. * 05 Reserved, 0
  2889. * 04..02 SC[2..0] Encoding, 000=NRZ
  2890. * 01..00 SM[1..0] Serial Mode, 11=Async
  2891. *
  2892. * 1000 0011
  2893. */
  2894. write_reg(info, CHA + CCR0, 0x83);
  2895. /* CCR1
  2896. *
  2897. * 07..05 Reserved, 0
  2898. * 04 ODS Output Driver Select, 1=TxD is push-pull output
  2899. * 03 BCR Bit Clock Rate, 1=16x
  2900. * 02..00 CM[2..0] Clock Mode, 111=BRG
  2901. *
  2902. * 0001 1111
  2903. */
  2904. write_reg(info, CHA + CCR1, 0x1f);
  2905. /* CCR2 (channel A)
  2906. *
  2907. * 07..06 BGR[9..8] Baud rate bits 9..8
  2908. * 05 BDF Baud rate divisor factor, 0=1, 1=BGR value
  2909. * 04 SSEL Clock source select, 1=submode b
  2910. * 03 TOE 0=TxCLK is input, 0=TxCLK is input
  2911. * 02 RWX Read/Write Exchange 0=disabled
  2912. * 01 Reserved, 0
  2913. * 00 DIV, data inversion 0=disabled, 1=enabled
  2914. *
  2915. * 0001 0000
  2916. */
  2917. write_reg(info, CHA + CCR2, 0x10);
  2918. /* CCR3
  2919. *
  2920. * 07..01 Reserved, 0
  2921. * 00 PSD DPLL Phase Shift Disable
  2922. *
  2923. * 0000 0000
  2924. */
  2925. write_reg(info, CHA + CCR3, 0);
  2926. /* CCR4
  2927. *
  2928. * 07 MCK4 Master Clock Divide by 4, 1=enabled
  2929. * 06 EBRG Enhanced Baud Rate Generator Mode, 1=enabled
  2930. * 05 TST1 Test Pin, 0=normal operation
  2931. * 04 ICD Ivert Carrier Detect, 1=enabled (active low)
  2932. * 03..00 Reserved, must be 0
  2933. *
  2934. * 0101 0000
  2935. */
  2936. write_reg(info, CHA + CCR4, 0x50);
  2937. mgslpc_set_rate(info, CHA, info->params.data_rate * 16);
  2938. /* DAFO Data Format
  2939. *
  2940. * 07 Reserved, 0
  2941. * 06 XBRK transmit break, 0=normal operation
  2942. * 05 Stop bits (0=1, 1=2)
  2943. * 04..03 PAR[1..0] Parity (01=odd, 10=even)
  2944. * 02 PAREN Parity Enable
  2945. * 01..00 CHL[1..0] Character Length (00=8, 01=7)
  2946. *
  2947. */
  2948. val = 0x00;
  2949. if (info->params.data_bits != 8)
  2950. val |= BIT0; /* 7 bits */
  2951. if (info->params.stop_bits != 1)
  2952. val |= BIT5;
  2953. if (info->params.parity != ASYNC_PARITY_NONE)
  2954. {
  2955. val |= BIT2; /* Parity enable */
  2956. if (info->params.parity == ASYNC_PARITY_ODD)
  2957. val |= BIT3;
  2958. else
  2959. val |= BIT4;
  2960. }
  2961. write_reg(info, CHA + DAFO, val);
  2962. /* RFC Rx FIFO Control
  2963. *
  2964. * 07 Reserved, 0
  2965. * 06 DPS, 1=parity bit not stored in data byte
  2966. * 05 DXS, 0=all data stored in FIFO (including XON/XOFF)
  2967. * 04 RFDF Rx FIFO Data Format, 1=status byte stored in FIFO
  2968. * 03..02 RFTH[1..0], rx threshold, 11=16 status + 16 data byte
  2969. * 01 Reserved, 0
  2970. * 00 TCDE Terminate Char Detect Enable, 0=disabled
  2971. *
  2972. * 0101 1100
  2973. */
  2974. write_reg(info, CHA + RFC, 0x5c);
  2975. /* RLCR Receive length check register
  2976. *
  2977. * Max frame length = (RL + 1) * 32
  2978. */
  2979. write_reg(info, CHA + RLCR, 0);
  2980. /* XBCH Transmit Byte Count High
  2981. *
  2982. * 07 DMA mode, 0 = interrupt driven
  2983. * 06 NRM, 0=ABM (ignored)
  2984. * 05 CAS Carrier Auto Start
  2985. * 04 XC Transmit Continuously (ignored)
  2986. * 03..00 XBC[10..8] Transmit byte count bits 10..8
  2987. *
  2988. * 0000 0000
  2989. */
  2990. val = 0x00;
  2991. if (info->params.flags & HDLC_FLAG_AUTO_DCD)
  2992. val |= BIT5;
  2993. write_reg(info, CHA + XBCH, val);
  2994. if (info->params.flags & HDLC_FLAG_AUTO_CTS)
  2995. irq_enable(info, CHA, IRQ_CTS);
  2996. /* MODE:03 RAC Receiver Active, 1=active */
  2997. set_reg_bits(info, CHA + MODE, BIT3);
  2998. enable_auxclk(info);
  2999. if (info->params.flags & HDLC_FLAG_AUTO_CTS) {
  3000. irq_enable(info, CHB, IRQ_CTS);
  3001. /* PVR[3] 1=AUTO CTS active */
  3002. set_reg_bits(info, CHA + PVR, BIT3);
  3003. } else
  3004. clear_reg_bits(info, CHA + PVR, BIT3);
  3005. irq_enable(info, CHA,
  3006. IRQ_RXEOM | IRQ_RXFIFO | IRQ_BREAK_ON | IRQ_RXTIME |
  3007. IRQ_ALLSENT | IRQ_TXFIFO);
  3008. issue_command(info, CHA, CMD_TXRESET + CMD_RXRESET);
  3009. wait_command_complete(info, CHA);
  3010. read_reg16(info, CHA + ISR); /* clear pending IRQs */
  3011. }
  3012. /* Set the HDLC idle mode for the transmitter.
  3013. */
  3014. static void tx_set_idle(MGSLPC_INFO *info)
  3015. {
  3016. /* Note: ESCC2 only supports flags and one idle modes */
  3017. if (info->idle_mode == HDLC_TXIDLE_FLAGS)
  3018. set_reg_bits(info, CHA + CCR1, BIT3);
  3019. else
  3020. clear_reg_bits(info, CHA + CCR1, BIT3);
  3021. }
  3022. /* get state of the V24 status (input) signals.
  3023. */
  3024. static void get_signals(MGSLPC_INFO *info)
  3025. {
  3026. unsigned char status = 0;
  3027. /* preserve RTS and DTR */
  3028. info->serial_signals &= SerialSignal_RTS | SerialSignal_DTR;
  3029. if (read_reg(info, CHB + VSTR) & BIT7)
  3030. info->serial_signals |= SerialSignal_DCD;
  3031. if (read_reg(info, CHB + STAR) & BIT1)
  3032. info->serial_signals |= SerialSignal_CTS;
  3033. status = read_reg(info, CHA + PVR);
  3034. if (!(status & PVR_RI))
  3035. info->serial_signals |= SerialSignal_RI;
  3036. if (!(status & PVR_DSR))
  3037. info->serial_signals |= SerialSignal_DSR;
  3038. }
  3039. /* Set the state of RTS and DTR based on contents of
  3040. * serial_signals member of device extension.
  3041. */
  3042. static void set_signals(MGSLPC_INFO *info)
  3043. {
  3044. unsigned char val;
  3045. val = read_reg(info, CHA + MODE);
  3046. if (info->params.mode == MGSL_MODE_ASYNC) {
  3047. if (info->serial_signals & SerialSignal_RTS)
  3048. val &= ~BIT6;
  3049. else
  3050. val |= BIT6;
  3051. } else {
  3052. if (info->serial_signals & SerialSignal_RTS)
  3053. val |= BIT2;
  3054. else
  3055. val &= ~BIT2;
  3056. }
  3057. write_reg(info, CHA + MODE, val);
  3058. if (info->serial_signals & SerialSignal_DTR)
  3059. clear_reg_bits(info, CHA + PVR, PVR_DTR);
  3060. else
  3061. set_reg_bits(info, CHA + PVR, PVR_DTR);
  3062. }
  3063. static void rx_reset_buffers(MGSLPC_INFO *info)
  3064. {
  3065. RXBUF *buf;
  3066. int i;
  3067. info->rx_put = 0;
  3068. info->rx_get = 0;
  3069. info->rx_frame_count = 0;
  3070. for (i=0 ; i < info->rx_buf_count ; i++) {
  3071. buf = (RXBUF*)(info->rx_buf + (i * info->rx_buf_size));
  3072. buf->status = buf->count = 0;
  3073. }
  3074. }
  3075. /* Attempt to return a received HDLC frame
  3076. * Only frames received without errors are returned.
  3077. *
  3078. * Returns true if frame returned, otherwise false
  3079. */
  3080. static bool rx_get_frame(MGSLPC_INFO *info, struct tty_struct *tty)
  3081. {
  3082. unsigned short status;
  3083. RXBUF *buf;
  3084. unsigned int framesize = 0;
  3085. unsigned long flags;
  3086. bool return_frame = false;
  3087. if (info->rx_frame_count == 0)
  3088. return false;
  3089. buf = (RXBUF*)(info->rx_buf + (info->rx_get * info->rx_buf_size));
  3090. status = buf->status;
  3091. /* 07 VFR 1=valid frame
  3092. * 06 RDO 1=data overrun
  3093. * 05 CRC 1=OK, 0=error
  3094. * 04 RAB 1=frame aborted
  3095. */
  3096. if ((status & 0xf0) != 0xA0) {
  3097. if (!(status & BIT7) || (status & BIT4))
  3098. info->icount.rxabort++;
  3099. else if (status & BIT6)
  3100. info->icount.rxover++;
  3101. else if (!(status & BIT5)) {
  3102. info->icount.rxcrc++;
  3103. if (info->params.crc_type & HDLC_CRC_RETURN_EX)
  3104. return_frame = true;
  3105. }
  3106. framesize = 0;
  3107. #if SYNCLINK_GENERIC_HDLC
  3108. {
  3109. info->netdev->stats.rx_errors++;
  3110. info->netdev->stats.rx_frame_errors++;
  3111. }
  3112. #endif
  3113. } else
  3114. return_frame = true;
  3115. if (return_frame)
  3116. framesize = buf->count;
  3117. if (debug_level >= DEBUG_LEVEL_BH)
  3118. printk("%s(%d):rx_get_frame(%s) status=%04X size=%d\n",
  3119. __FILE__, __LINE__, info->device_name, status, framesize);
  3120. if (debug_level >= DEBUG_LEVEL_DATA)
  3121. trace_block(info, buf->data, framesize, 0);
  3122. if (framesize) {
  3123. if ((info->params.crc_type & HDLC_CRC_RETURN_EX &&
  3124. framesize+1 > info->max_frame_size) ||
  3125. framesize > info->max_frame_size)
  3126. info->icount.rxlong++;
  3127. else {
  3128. if (status & BIT5)
  3129. info->icount.rxok++;
  3130. if (info->params.crc_type & HDLC_CRC_RETURN_EX) {
  3131. *(buf->data + framesize) = status & BIT5 ? RX_OK:RX_CRC_ERROR;
  3132. ++framesize;
  3133. }
  3134. #if SYNCLINK_GENERIC_HDLC
  3135. if (info->netcount)
  3136. hdlcdev_rx(info, buf->data, framesize);
  3137. else
  3138. #endif
  3139. ldisc_receive_buf(tty, buf->data, info->flag_buf, framesize);
  3140. }
  3141. }
  3142. spin_lock_irqsave(&info->lock, flags);
  3143. buf->status = buf->count = 0;
  3144. info->rx_frame_count--;
  3145. info->rx_get++;
  3146. if (info->rx_get >= info->rx_buf_count)
  3147. info->rx_get = 0;
  3148. spin_unlock_irqrestore(&info->lock, flags);
  3149. return true;
  3150. }
  3151. static bool register_test(MGSLPC_INFO *info)
  3152. {
  3153. static unsigned char patterns[] =
  3154. { 0x00, 0xff, 0xaa, 0x55, 0x69, 0x96, 0x0f };
  3155. static unsigned int count = ARRAY_SIZE(patterns);
  3156. unsigned int i;
  3157. bool rc = true;
  3158. unsigned long flags;
  3159. spin_lock_irqsave(&info->lock, flags);
  3160. reset_device(info);
  3161. for (i = 0; i < count; i++) {
  3162. write_reg(info, XAD1, patterns[i]);
  3163. write_reg(info, XAD2, patterns[(i + 1) % count]);
  3164. if ((read_reg(info, XAD1) != patterns[i]) ||
  3165. (read_reg(info, XAD2) != patterns[(i + 1) % count])) {
  3166. rc = false;
  3167. break;
  3168. }
  3169. }
  3170. spin_unlock_irqrestore(&info->lock, flags);
  3171. return rc;
  3172. }
  3173. static bool irq_test(MGSLPC_INFO *info)
  3174. {
  3175. unsigned long end_time;
  3176. unsigned long flags;
  3177. spin_lock_irqsave(&info->lock, flags);
  3178. reset_device(info);
  3179. info->testing_irq = true;
  3180. hdlc_mode(info);
  3181. info->irq_occurred = false;
  3182. /* init hdlc mode */
  3183. irq_enable(info, CHA, IRQ_TIMER);
  3184. write_reg(info, CHA + TIMR, 0); /* 512 cycles */
  3185. issue_command(info, CHA, CMD_START_TIMER);
  3186. spin_unlock_irqrestore(&info->lock, flags);
  3187. end_time=100;
  3188. while(end_time-- && !info->irq_occurred) {
  3189. msleep_interruptible(10);
  3190. }
  3191. info->testing_irq = false;
  3192. spin_lock_irqsave(&info->lock, flags);
  3193. reset_device(info);
  3194. spin_unlock_irqrestore(&info->lock, flags);
  3195. return info->irq_occurred;
  3196. }
  3197. static int adapter_test(MGSLPC_INFO *info)
  3198. {
  3199. if (!register_test(info)) {
  3200. info->init_error = DiagStatus_AddressFailure;
  3201. printk("%s(%d):Register test failure for device %s Addr=%04X\n",
  3202. __FILE__, __LINE__, info->device_name, (unsigned short)(info->io_base));
  3203. return -ENODEV;
  3204. }
  3205. if (!irq_test(info)) {
  3206. info->init_error = DiagStatus_IrqFailure;
  3207. printk("%s(%d):Interrupt test failure for device %s IRQ=%d\n",
  3208. __FILE__, __LINE__, info->device_name, (unsigned short)(info->irq_level));
  3209. return -ENODEV;
  3210. }
  3211. if (debug_level >= DEBUG_LEVEL_INFO)
  3212. printk("%s(%d):device %s passed diagnostics\n",
  3213. __FILE__, __LINE__, info->device_name);
  3214. return 0;
  3215. }
  3216. static void trace_block(MGSLPC_INFO *info,const char* data, int count, int xmit)
  3217. {
  3218. int i;
  3219. int linecount;
  3220. if (xmit)
  3221. printk("%s tx data:\n", info->device_name);
  3222. else
  3223. printk("%s rx data:\n", info->device_name);
  3224. while(count) {
  3225. if (count > 16)
  3226. linecount = 16;
  3227. else
  3228. linecount = count;
  3229. for(i=0;i<linecount;i++)
  3230. printk("%02X ", (unsigned char)data[i]);
  3231. for(;i<17;i++)
  3232. printk(" ");
  3233. for(i=0;i<linecount;i++) {
  3234. if (data[i]>=040 && data[i]<=0176)
  3235. printk("%c", data[i]);
  3236. else
  3237. printk(".");
  3238. }
  3239. printk("\n");
  3240. data += linecount;
  3241. count -= linecount;
  3242. }
  3243. }
  3244. /* HDLC frame time out
  3245. * update stats and do tx completion processing
  3246. */
  3247. static void tx_timeout(struct timer_list *t)
  3248. {
  3249. MGSLPC_INFO *info = from_timer(info, t, tx_timer);
  3250. unsigned long flags;
  3251. if (debug_level >= DEBUG_LEVEL_INFO)
  3252. printk("%s(%d):tx_timeout(%s)\n",
  3253. __FILE__, __LINE__, info->device_name);
  3254. if (info->tx_active &&
  3255. info->params.mode == MGSL_MODE_HDLC) {
  3256. info->icount.txtimeout++;
  3257. }
  3258. spin_lock_irqsave(&info->lock, flags);
  3259. info->tx_active = false;
  3260. info->tx_count = info->tx_put = info->tx_get = 0;
  3261. spin_unlock_irqrestore(&info->lock, flags);
  3262. #if SYNCLINK_GENERIC_HDLC
  3263. if (info->netcount)
  3264. hdlcdev_tx_done(info);
  3265. else
  3266. #endif
  3267. {
  3268. struct tty_struct *tty = tty_port_tty_get(&info->port);
  3269. bh_transmit(info, tty);
  3270. tty_kref_put(tty);
  3271. }
  3272. }
  3273. #if SYNCLINK_GENERIC_HDLC
  3274. /**
  3275. * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
  3276. * set encoding and frame check sequence (FCS) options
  3277. *
  3278. * dev pointer to network device structure
  3279. * encoding serial encoding setting
  3280. * parity FCS setting
  3281. *
  3282. * returns 0 if success, otherwise error code
  3283. */
  3284. static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
  3285. unsigned short parity)
  3286. {
  3287. MGSLPC_INFO *info = dev_to_port(dev);
  3288. struct tty_struct *tty;
  3289. unsigned char new_encoding;
  3290. unsigned short new_crctype;
  3291. /* return error if TTY interface open */
  3292. if (info->port.count)
  3293. return -EBUSY;
  3294. switch (encoding)
  3295. {
  3296. case ENCODING_NRZ: new_encoding = HDLC_ENCODING_NRZ; break;
  3297. case ENCODING_NRZI: new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
  3298. case ENCODING_FM_MARK: new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
  3299. case ENCODING_FM_SPACE: new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
  3300. case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
  3301. default: return -EINVAL;
  3302. }
  3303. switch (parity)
  3304. {
  3305. case PARITY_NONE: new_crctype = HDLC_CRC_NONE; break;
  3306. case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
  3307. case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
  3308. default: return -EINVAL;
  3309. }
  3310. info->params.encoding = new_encoding;
  3311. info->params.crc_type = new_crctype;
  3312. /* if network interface up, reprogram hardware */
  3313. if (info->netcount) {
  3314. tty = tty_port_tty_get(&info->port);
  3315. mgslpc_program_hw(info, tty);
  3316. tty_kref_put(tty);
  3317. }
  3318. return 0;
  3319. }
  3320. /**
  3321. * called by generic HDLC layer to send frame
  3322. *
  3323. * skb socket buffer containing HDLC frame
  3324. * dev pointer to network device structure
  3325. */
  3326. static netdev_tx_t hdlcdev_xmit(struct sk_buff *skb,
  3327. struct net_device *dev)
  3328. {
  3329. MGSLPC_INFO *info = dev_to_port(dev);
  3330. unsigned long flags;
  3331. if (debug_level >= DEBUG_LEVEL_INFO)
  3332. printk(KERN_INFO "%s:hdlc_xmit(%s)\n", __FILE__, dev->name);
  3333. /* stop sending until this frame completes */
  3334. netif_stop_queue(dev);
  3335. /* copy data to device buffers */
  3336. skb_copy_from_linear_data(skb, info->tx_buf, skb->len);
  3337. info->tx_get = 0;
  3338. info->tx_put = info->tx_count = skb->len;
  3339. /* update network statistics */
  3340. dev->stats.tx_packets++;
  3341. dev->stats.tx_bytes += skb->len;
  3342. /* done with socket buffer, so free it */
  3343. dev_kfree_skb(skb);
  3344. /* save start time for transmit timeout detection */
  3345. netif_trans_update(dev);
  3346. /* start hardware transmitter if necessary */
  3347. spin_lock_irqsave(&info->lock, flags);
  3348. if (!info->tx_active) {
  3349. struct tty_struct *tty = tty_port_tty_get(&info->port);
  3350. tx_start(info, tty);
  3351. tty_kref_put(tty);
  3352. }
  3353. spin_unlock_irqrestore(&info->lock, flags);
  3354. return NETDEV_TX_OK;
  3355. }
  3356. /**
  3357. * called by network layer when interface enabled
  3358. * claim resources and initialize hardware
  3359. *
  3360. * dev pointer to network device structure
  3361. *
  3362. * returns 0 if success, otherwise error code
  3363. */
  3364. static int hdlcdev_open(struct net_device *dev)
  3365. {
  3366. MGSLPC_INFO *info = dev_to_port(dev);
  3367. struct tty_struct *tty;
  3368. int rc;
  3369. unsigned long flags;
  3370. if (debug_level >= DEBUG_LEVEL_INFO)
  3371. printk("%s:hdlcdev_open(%s)\n", __FILE__, dev->name);
  3372. /* generic HDLC layer open processing */
  3373. rc = hdlc_open(dev);
  3374. if (rc != 0)
  3375. return rc;
  3376. /* arbitrate between network and tty opens */
  3377. spin_lock_irqsave(&info->netlock, flags);
  3378. if (info->port.count != 0 || info->netcount != 0) {
  3379. printk(KERN_WARNING "%s: hdlc_open returning busy\n", dev->name);
  3380. spin_unlock_irqrestore(&info->netlock, flags);
  3381. return -EBUSY;
  3382. }
  3383. info->netcount=1;
  3384. spin_unlock_irqrestore(&info->netlock, flags);
  3385. tty = tty_port_tty_get(&info->port);
  3386. /* claim resources and init adapter */
  3387. rc = startup(info, tty);
  3388. if (rc != 0) {
  3389. tty_kref_put(tty);
  3390. spin_lock_irqsave(&info->netlock, flags);
  3391. info->netcount=0;
  3392. spin_unlock_irqrestore(&info->netlock, flags);
  3393. return rc;
  3394. }
  3395. /* assert RTS and DTR, apply hardware settings */
  3396. info->serial_signals |= SerialSignal_RTS | SerialSignal_DTR;
  3397. mgslpc_program_hw(info, tty);
  3398. tty_kref_put(tty);
  3399. /* enable network layer transmit */
  3400. netif_trans_update(dev);
  3401. netif_start_queue(dev);
  3402. /* inform generic HDLC layer of current DCD status */
  3403. spin_lock_irqsave(&info->lock, flags);
  3404. get_signals(info);
  3405. spin_unlock_irqrestore(&info->lock, flags);
  3406. if (info->serial_signals & SerialSignal_DCD)
  3407. netif_carrier_on(dev);
  3408. else
  3409. netif_carrier_off(dev);
  3410. return 0;
  3411. }
  3412. /**
  3413. * called by network layer when interface is disabled
  3414. * shutdown hardware and release resources
  3415. *
  3416. * dev pointer to network device structure
  3417. *
  3418. * returns 0 if success, otherwise error code
  3419. */
  3420. static int hdlcdev_close(struct net_device *dev)
  3421. {
  3422. MGSLPC_INFO *info = dev_to_port(dev);
  3423. struct tty_struct *tty = tty_port_tty_get(&info->port);
  3424. unsigned long flags;
  3425. if (debug_level >= DEBUG_LEVEL_INFO)
  3426. printk("%s:hdlcdev_close(%s)\n", __FILE__, dev->name);
  3427. netif_stop_queue(dev);
  3428. /* shutdown adapter and release resources */
  3429. shutdown(info, tty);
  3430. tty_kref_put(tty);
  3431. hdlc_close(dev);
  3432. spin_lock_irqsave(&info->netlock, flags);
  3433. info->netcount=0;
  3434. spin_unlock_irqrestore(&info->netlock, flags);
  3435. return 0;
  3436. }
  3437. /**
  3438. * called by network layer to process IOCTL call to network device
  3439. *
  3440. * dev pointer to network device structure
  3441. * ifr pointer to network interface request structure
  3442. * cmd IOCTL command code
  3443. *
  3444. * returns 0 if success, otherwise error code
  3445. */
  3446. static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
  3447. {
  3448. const size_t size = sizeof(sync_serial_settings);
  3449. sync_serial_settings new_line;
  3450. sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
  3451. MGSLPC_INFO *info = dev_to_port(dev);
  3452. unsigned int flags;
  3453. if (debug_level >= DEBUG_LEVEL_INFO)
  3454. printk("%s:hdlcdev_ioctl(%s)\n", __FILE__, dev->name);
  3455. /* return error if TTY interface open */
  3456. if (info->port.count)
  3457. return -EBUSY;
  3458. if (cmd != SIOCWANDEV)
  3459. return hdlc_ioctl(dev, ifr, cmd);
  3460. memset(&new_line, 0, size);
  3461. switch(ifr->ifr_settings.type) {
  3462. case IF_GET_IFACE: /* return current sync_serial_settings */
  3463. ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
  3464. if (ifr->ifr_settings.size < size) {
  3465. ifr->ifr_settings.size = size; /* data size wanted */
  3466. return -ENOBUFS;
  3467. }
  3468. flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
  3469. HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
  3470. HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
  3471. HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
  3472. switch (flags){
  3473. case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
  3474. case (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_INT; break;
  3475. case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_TXINT; break;
  3476. case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
  3477. default: new_line.clock_type = CLOCK_DEFAULT;
  3478. }
  3479. new_line.clock_rate = info->params.clock_speed;
  3480. new_line.loopback = info->params.loopback ? 1:0;
  3481. if (copy_to_user(line, &new_line, size))
  3482. return -EFAULT;
  3483. return 0;
  3484. case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */
  3485. if(!capable(CAP_NET_ADMIN))
  3486. return -EPERM;
  3487. if (copy_from_user(&new_line, line, size))
  3488. return -EFAULT;
  3489. switch (new_line.clock_type)
  3490. {
  3491. case CLOCK_EXT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
  3492. case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
  3493. case CLOCK_INT: flags = HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG; break;
  3494. case CLOCK_TXINT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG; break;
  3495. case CLOCK_DEFAULT: flags = info->params.flags &
  3496. (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
  3497. HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
  3498. HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
  3499. HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); break;
  3500. default: return -EINVAL;
  3501. }
  3502. if (new_line.loopback != 0 && new_line.loopback != 1)
  3503. return -EINVAL;
  3504. info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
  3505. HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
  3506. HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
  3507. HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
  3508. info->params.flags |= flags;
  3509. info->params.loopback = new_line.loopback;
  3510. if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
  3511. info->params.clock_speed = new_line.clock_rate;
  3512. else
  3513. info->params.clock_speed = 0;
  3514. /* if network interface up, reprogram hardware */
  3515. if (info->netcount) {
  3516. struct tty_struct *tty = tty_port_tty_get(&info->port);
  3517. mgslpc_program_hw(info, tty);
  3518. tty_kref_put(tty);
  3519. }
  3520. return 0;
  3521. default:
  3522. return hdlc_ioctl(dev, ifr, cmd);
  3523. }
  3524. }
  3525. /**
  3526. * called by network layer when transmit timeout is detected
  3527. *
  3528. * dev pointer to network device structure
  3529. */
  3530. static void hdlcdev_tx_timeout(struct net_device *dev, unsigned int txqueue)
  3531. {
  3532. MGSLPC_INFO *info = dev_to_port(dev);
  3533. unsigned long flags;
  3534. if (debug_level >= DEBUG_LEVEL_INFO)
  3535. printk("hdlcdev_tx_timeout(%s)\n", dev->name);
  3536. dev->stats.tx_errors++;
  3537. dev->stats.tx_aborted_errors++;
  3538. spin_lock_irqsave(&info->lock, flags);
  3539. tx_stop(info);
  3540. spin_unlock_irqrestore(&info->lock, flags);
  3541. netif_wake_queue(dev);
  3542. }
  3543. /**
  3544. * called by device driver when transmit completes
  3545. * reenable network layer transmit if stopped
  3546. *
  3547. * info pointer to device instance information
  3548. */
  3549. static void hdlcdev_tx_done(MGSLPC_INFO *info)
  3550. {
  3551. if (netif_queue_stopped(info->netdev))
  3552. netif_wake_queue(info->netdev);
  3553. }
  3554. /**
  3555. * called by device driver when frame received
  3556. * pass frame to network layer
  3557. *
  3558. * info pointer to device instance information
  3559. * buf pointer to buffer contianing frame data
  3560. * size count of data bytes in buf
  3561. */
  3562. static void hdlcdev_rx(MGSLPC_INFO *info, char *buf, int size)
  3563. {
  3564. struct sk_buff *skb = dev_alloc_skb(size);
  3565. struct net_device *dev = info->netdev;
  3566. if (debug_level >= DEBUG_LEVEL_INFO)
  3567. printk("hdlcdev_rx(%s)\n", dev->name);
  3568. if (skb == NULL) {
  3569. printk(KERN_NOTICE "%s: can't alloc skb, dropping packet\n", dev->name);
  3570. dev->stats.rx_dropped++;
  3571. return;
  3572. }
  3573. skb_put_data(skb, buf, size);
  3574. skb->protocol = hdlc_type_trans(skb, dev);
  3575. dev->stats.rx_packets++;
  3576. dev->stats.rx_bytes += size;
  3577. netif_rx(skb);
  3578. }
  3579. static const struct net_device_ops hdlcdev_ops = {
  3580. .ndo_open = hdlcdev_open,
  3581. .ndo_stop = hdlcdev_close,
  3582. .ndo_start_xmit = hdlc_start_xmit,
  3583. .ndo_do_ioctl = hdlcdev_ioctl,
  3584. .ndo_tx_timeout = hdlcdev_tx_timeout,
  3585. };
  3586. /**
  3587. * called by device driver when adding device instance
  3588. * do generic HDLC initialization
  3589. *
  3590. * info pointer to device instance information
  3591. *
  3592. * returns 0 if success, otherwise error code
  3593. */
  3594. static int hdlcdev_init(MGSLPC_INFO *info)
  3595. {
  3596. int rc;
  3597. struct net_device *dev;
  3598. hdlc_device *hdlc;
  3599. /* allocate and initialize network and HDLC layer objects */
  3600. dev = alloc_hdlcdev(info);
  3601. if (dev == NULL) {
  3602. printk(KERN_ERR "%s:hdlc device allocation failure\n", __FILE__);
  3603. return -ENOMEM;
  3604. }
  3605. /* for network layer reporting purposes only */
  3606. dev->base_addr = info->io_base;
  3607. dev->irq = info->irq_level;
  3608. /* network layer callbacks and settings */
  3609. dev->netdev_ops = &hdlcdev_ops;
  3610. dev->watchdog_timeo = 10 * HZ;
  3611. dev->tx_queue_len = 50;
  3612. /* generic HDLC layer callbacks and settings */
  3613. hdlc = dev_to_hdlc(dev);
  3614. hdlc->attach = hdlcdev_attach;
  3615. hdlc->xmit = hdlcdev_xmit;
  3616. /* register objects with HDLC layer */
  3617. rc = register_hdlc_device(dev);
  3618. if (rc) {
  3619. printk(KERN_WARNING "%s:unable to register hdlc device\n", __FILE__);
  3620. free_netdev(dev);
  3621. return rc;
  3622. }
  3623. info->netdev = dev;
  3624. return 0;
  3625. }
  3626. /**
  3627. * called by device driver when removing device instance
  3628. * do generic HDLC cleanup
  3629. *
  3630. * info pointer to device instance information
  3631. */
  3632. static void hdlcdev_exit(MGSLPC_INFO *info)
  3633. {
  3634. unregister_hdlc_device(info->netdev);
  3635. free_netdev(info->netdev);
  3636. info->netdev = NULL;
  3637. }
  3638. #endif /* CONFIG_HDLC */