cm4040_cs.c 15 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685
  1. /*
  2. * A driver for the Omnikey PCMCIA smartcard reader CardMan 4040
  3. *
  4. * (c) 2000-2004 Omnikey AG (http://www.omnikey.com/)
  5. *
  6. * (C) 2005-2006 Harald Welte <laforge@gnumonks.org>
  7. * - add support for poll()
  8. * - driver cleanup
  9. * - add waitqueues
  10. * - adhere to linux kernel coding style and policies
  11. * - support 2.6.13 "new style" pcmcia interface
  12. * - add class interface for udev device creation
  13. *
  14. * The device basically is a USB CCID compliant device that has been
  15. * attached to an I/O-Mapped FIFO.
  16. *
  17. * All rights reserved, Dual BSD/GPL Licensed.
  18. */
  19. #include <linux/kernel.h>
  20. #include <linux/module.h>
  21. #include <linux/slab.h>
  22. #include <linux/init.h>
  23. #include <linux/fs.h>
  24. #include <linux/delay.h>
  25. #include <linux/poll.h>
  26. #include <linux/mutex.h>
  27. #include <linux/wait.h>
  28. #include <linux/uaccess.h>
  29. #include <asm/io.h>
  30. #include <pcmcia/cistpl.h>
  31. #include <pcmcia/cisreg.h>
  32. #include <pcmcia/ciscode.h>
  33. #include <pcmcia/ds.h>
  34. #include "cm4040_cs.h"
  35. #define reader_to_dev(x) (&x->p_dev->dev)
  36. /* n (debug level) is ignored */
  37. /* additional debug output may be enabled by re-compiling with
  38. * CM4040_DEBUG set */
  39. /* #define CM4040_DEBUG */
  40. #define DEBUGP(n, rdr, x, args...) do { \
  41. dev_dbg(reader_to_dev(rdr), "%s:" x, \
  42. __func__ , ## args); \
  43. } while (0)
  44. static DEFINE_MUTEX(cm4040_mutex);
  45. #define CCID_DRIVER_BULK_DEFAULT_TIMEOUT (150*HZ)
  46. #define CCID_DRIVER_ASYNC_POWERUP_TIMEOUT (35*HZ)
  47. #define CCID_DRIVER_MINIMUM_TIMEOUT (3*HZ)
  48. #define READ_WRITE_BUFFER_SIZE 512
  49. #define POLL_LOOP_COUNT 1000
  50. /* how often to poll for fifo status change */
  51. #define POLL_PERIOD msecs_to_jiffies(10)
  52. static void reader_release(struct pcmcia_device *link);
  53. static int major;
  54. static struct class *cmx_class;
  55. #define BS_READABLE 0x01
  56. #define BS_WRITABLE 0x02
  57. struct reader_dev {
  58. struct pcmcia_device *p_dev;
  59. wait_queue_head_t devq;
  60. wait_queue_head_t poll_wait;
  61. wait_queue_head_t read_wait;
  62. wait_queue_head_t write_wait;
  63. unsigned long buffer_status;
  64. unsigned long timeout;
  65. unsigned char s_buf[READ_WRITE_BUFFER_SIZE];
  66. unsigned char r_buf[READ_WRITE_BUFFER_SIZE];
  67. struct timer_list poll_timer;
  68. };
  69. static struct pcmcia_device *dev_table[CM_MAX_DEV];
  70. #ifndef CM4040_DEBUG
  71. #define xoutb outb
  72. #define xinb inb
  73. #else
  74. static inline void xoutb(unsigned char val, unsigned short port)
  75. {
  76. pr_debug("outb(val=%.2x,port=%.4x)\n", val, port);
  77. outb(val, port);
  78. }
  79. static inline unsigned char xinb(unsigned short port)
  80. {
  81. unsigned char val;
  82. val = inb(port);
  83. pr_debug("%.2x=inb(%.4x)\n", val, port);
  84. return val;
  85. }
  86. #endif
  87. /* poll the device fifo status register. not to be confused with
  88. * the poll syscall. */
  89. static void cm4040_do_poll(struct timer_list *t)
  90. {
  91. struct reader_dev *dev = from_timer(dev, t, poll_timer);
  92. unsigned int obs = xinb(dev->p_dev->resource[0]->start
  93. + REG_OFFSET_BUFFER_STATUS);
  94. if ((obs & BSR_BULK_IN_FULL)) {
  95. set_bit(BS_READABLE, &dev->buffer_status);
  96. DEBUGP(4, dev, "waking up read_wait\n");
  97. wake_up_interruptible(&dev->read_wait);
  98. } else
  99. clear_bit(BS_READABLE, &dev->buffer_status);
  100. if (!(obs & BSR_BULK_OUT_FULL)) {
  101. set_bit(BS_WRITABLE, &dev->buffer_status);
  102. DEBUGP(4, dev, "waking up write_wait\n");
  103. wake_up_interruptible(&dev->write_wait);
  104. } else
  105. clear_bit(BS_WRITABLE, &dev->buffer_status);
  106. if (dev->buffer_status)
  107. wake_up_interruptible(&dev->poll_wait);
  108. mod_timer(&dev->poll_timer, jiffies + POLL_PERIOD);
  109. }
  110. static void cm4040_stop_poll(struct reader_dev *dev)
  111. {
  112. del_timer_sync(&dev->poll_timer);
  113. }
  114. static int wait_for_bulk_out_ready(struct reader_dev *dev)
  115. {
  116. int i, rc;
  117. int iobase = dev->p_dev->resource[0]->start;
  118. for (i = 0; i < POLL_LOOP_COUNT; i++) {
  119. if ((xinb(iobase + REG_OFFSET_BUFFER_STATUS)
  120. & BSR_BULK_OUT_FULL) == 0) {
  121. DEBUGP(4, dev, "BulkOut empty (i=%d)\n", i);
  122. return 1;
  123. }
  124. }
  125. DEBUGP(4, dev, "wait_event_interruptible_timeout(timeout=%ld\n",
  126. dev->timeout);
  127. rc = wait_event_interruptible_timeout(dev->write_wait,
  128. test_and_clear_bit(BS_WRITABLE,
  129. &dev->buffer_status),
  130. dev->timeout);
  131. if (rc > 0)
  132. DEBUGP(4, dev, "woke up: BulkOut empty\n");
  133. else if (rc == 0)
  134. DEBUGP(4, dev, "woke up: BulkOut full, returning 0 :(\n");
  135. else if (rc < 0)
  136. DEBUGP(4, dev, "woke up: signal arrived\n");
  137. return rc;
  138. }
  139. /* Write to Sync Control Register */
  140. static int write_sync_reg(unsigned char val, struct reader_dev *dev)
  141. {
  142. int iobase = dev->p_dev->resource[0]->start;
  143. int rc;
  144. rc = wait_for_bulk_out_ready(dev);
  145. if (rc <= 0)
  146. return rc;
  147. xoutb(val, iobase + REG_OFFSET_SYNC_CONTROL);
  148. rc = wait_for_bulk_out_ready(dev);
  149. if (rc <= 0)
  150. return rc;
  151. return 1;
  152. }
  153. static int wait_for_bulk_in_ready(struct reader_dev *dev)
  154. {
  155. int i, rc;
  156. int iobase = dev->p_dev->resource[0]->start;
  157. for (i = 0; i < POLL_LOOP_COUNT; i++) {
  158. if ((xinb(iobase + REG_OFFSET_BUFFER_STATUS)
  159. & BSR_BULK_IN_FULL) == BSR_BULK_IN_FULL) {
  160. DEBUGP(3, dev, "BulkIn full (i=%d)\n", i);
  161. return 1;
  162. }
  163. }
  164. DEBUGP(4, dev, "wait_event_interruptible_timeout(timeout=%ld\n",
  165. dev->timeout);
  166. rc = wait_event_interruptible_timeout(dev->read_wait,
  167. test_and_clear_bit(BS_READABLE,
  168. &dev->buffer_status),
  169. dev->timeout);
  170. if (rc > 0)
  171. DEBUGP(4, dev, "woke up: BulkIn full\n");
  172. else if (rc == 0)
  173. DEBUGP(4, dev, "woke up: BulkIn not full, returning 0 :(\n");
  174. else if (rc < 0)
  175. DEBUGP(4, dev, "woke up: signal arrived\n");
  176. return rc;
  177. }
  178. static ssize_t cm4040_read(struct file *filp, char __user *buf,
  179. size_t count, loff_t *ppos)
  180. {
  181. struct reader_dev *dev = filp->private_data;
  182. int iobase = dev->p_dev->resource[0]->start;
  183. size_t bytes_to_read;
  184. unsigned long i;
  185. size_t min_bytes_to_read;
  186. int rc;
  187. unsigned char uc;
  188. DEBUGP(2, dev, "-> cm4040_read(%s,%d)\n", current->comm, current->pid);
  189. if (count == 0)
  190. return 0;
  191. if (count < 10)
  192. return -EFAULT;
  193. if (filp->f_flags & O_NONBLOCK) {
  194. DEBUGP(4, dev, "filep->f_flags O_NONBLOCK set\n");
  195. DEBUGP(2, dev, "<- cm4040_read (failure)\n");
  196. return -EAGAIN;
  197. }
  198. if (!pcmcia_dev_present(dev->p_dev))
  199. return -ENODEV;
  200. for (i = 0; i < 5; i++) {
  201. rc = wait_for_bulk_in_ready(dev);
  202. if (rc <= 0) {
  203. DEBUGP(5, dev, "wait_for_bulk_in_ready rc=%.2x\n", rc);
  204. DEBUGP(2, dev, "<- cm4040_read (failed)\n");
  205. if (rc == -ERESTARTSYS)
  206. return rc;
  207. return -EIO;
  208. }
  209. dev->r_buf[i] = xinb(iobase + REG_OFFSET_BULK_IN);
  210. #ifdef CM4040_DEBUG
  211. pr_debug("%lu:%2x ", i, dev->r_buf[i]);
  212. }
  213. pr_debug("\n");
  214. #else
  215. }
  216. #endif
  217. bytes_to_read = 5 + le32_to_cpu(*(__le32 *)&dev->r_buf[1]);
  218. DEBUGP(6, dev, "BytesToRead=%zu\n", bytes_to_read);
  219. min_bytes_to_read = min(count, bytes_to_read + 5);
  220. min_bytes_to_read = min_t(size_t, min_bytes_to_read, READ_WRITE_BUFFER_SIZE);
  221. DEBUGP(6, dev, "Min=%zu\n", min_bytes_to_read);
  222. for (i = 0; i < (min_bytes_to_read-5); i++) {
  223. rc = wait_for_bulk_in_ready(dev);
  224. if (rc <= 0) {
  225. DEBUGP(5, dev, "wait_for_bulk_in_ready rc=%.2x\n", rc);
  226. DEBUGP(2, dev, "<- cm4040_read (failed)\n");
  227. if (rc == -ERESTARTSYS)
  228. return rc;
  229. return -EIO;
  230. }
  231. dev->r_buf[i+5] = xinb(iobase + REG_OFFSET_BULK_IN);
  232. #ifdef CM4040_DEBUG
  233. pr_debug("%lu:%2x ", i, dev->r_buf[i]);
  234. }
  235. pr_debug("\n");
  236. #else
  237. }
  238. #endif
  239. *ppos = min_bytes_to_read;
  240. if (copy_to_user(buf, dev->r_buf, min_bytes_to_read))
  241. return -EFAULT;
  242. rc = wait_for_bulk_in_ready(dev);
  243. if (rc <= 0) {
  244. DEBUGP(5, dev, "wait_for_bulk_in_ready rc=%.2x\n", rc);
  245. DEBUGP(2, dev, "<- cm4040_read (failed)\n");
  246. if (rc == -ERESTARTSYS)
  247. return rc;
  248. return -EIO;
  249. }
  250. rc = write_sync_reg(SCR_READER_TO_HOST_DONE, dev);
  251. if (rc <= 0) {
  252. DEBUGP(5, dev, "write_sync_reg c=%.2x\n", rc);
  253. DEBUGP(2, dev, "<- cm4040_read (failed)\n");
  254. if (rc == -ERESTARTSYS)
  255. return rc;
  256. else
  257. return -EIO;
  258. }
  259. uc = xinb(iobase + REG_OFFSET_BULK_IN);
  260. DEBUGP(2, dev, "<- cm4040_read (successfully)\n");
  261. return min_bytes_to_read;
  262. }
  263. static ssize_t cm4040_write(struct file *filp, const char __user *buf,
  264. size_t count, loff_t *ppos)
  265. {
  266. struct reader_dev *dev = filp->private_data;
  267. int iobase = dev->p_dev->resource[0]->start;
  268. ssize_t rc;
  269. int i;
  270. unsigned int bytes_to_write;
  271. DEBUGP(2, dev, "-> cm4040_write(%s,%d)\n", current->comm, current->pid);
  272. if (count == 0) {
  273. DEBUGP(2, dev, "<- cm4040_write empty read (successfully)\n");
  274. return 0;
  275. }
  276. if ((count < 5) || (count > READ_WRITE_BUFFER_SIZE)) {
  277. DEBUGP(2, dev, "<- cm4040_write buffersize=%zd < 5\n", count);
  278. return -EIO;
  279. }
  280. if (filp->f_flags & O_NONBLOCK) {
  281. DEBUGP(4, dev, "filep->f_flags O_NONBLOCK set\n");
  282. DEBUGP(4, dev, "<- cm4040_write (failure)\n");
  283. return -EAGAIN;
  284. }
  285. if (!pcmcia_dev_present(dev->p_dev))
  286. return -ENODEV;
  287. bytes_to_write = count;
  288. if (copy_from_user(dev->s_buf, buf, bytes_to_write))
  289. return -EFAULT;
  290. switch (dev->s_buf[0]) {
  291. case CMD_PC_TO_RDR_XFRBLOCK:
  292. case CMD_PC_TO_RDR_SECURE:
  293. case CMD_PC_TO_RDR_TEST_SECURE:
  294. case CMD_PC_TO_RDR_OK_SECURE:
  295. dev->timeout = CCID_DRIVER_BULK_DEFAULT_TIMEOUT;
  296. break;
  297. case CMD_PC_TO_RDR_ICCPOWERON:
  298. dev->timeout = CCID_DRIVER_ASYNC_POWERUP_TIMEOUT;
  299. break;
  300. case CMD_PC_TO_RDR_GETSLOTSTATUS:
  301. case CMD_PC_TO_RDR_ICCPOWEROFF:
  302. case CMD_PC_TO_RDR_GETPARAMETERS:
  303. case CMD_PC_TO_RDR_RESETPARAMETERS:
  304. case CMD_PC_TO_RDR_SETPARAMETERS:
  305. case CMD_PC_TO_RDR_ESCAPE:
  306. case CMD_PC_TO_RDR_ICCCLOCK:
  307. default:
  308. dev->timeout = CCID_DRIVER_MINIMUM_TIMEOUT;
  309. break;
  310. }
  311. rc = write_sync_reg(SCR_HOST_TO_READER_START, dev);
  312. if (rc <= 0) {
  313. DEBUGP(5, dev, "write_sync_reg c=%.2zx\n", rc);
  314. DEBUGP(2, dev, "<- cm4040_write (failed)\n");
  315. if (rc == -ERESTARTSYS)
  316. return rc;
  317. else
  318. return -EIO;
  319. }
  320. DEBUGP(4, dev, "start \n");
  321. for (i = 0; i < bytes_to_write; i++) {
  322. rc = wait_for_bulk_out_ready(dev);
  323. if (rc <= 0) {
  324. DEBUGP(5, dev, "wait_for_bulk_out_ready rc=%.2zx\n",
  325. rc);
  326. DEBUGP(2, dev, "<- cm4040_write (failed)\n");
  327. if (rc == -ERESTARTSYS)
  328. return rc;
  329. else
  330. return -EIO;
  331. }
  332. xoutb(dev->s_buf[i],iobase + REG_OFFSET_BULK_OUT);
  333. }
  334. DEBUGP(4, dev, "end\n");
  335. rc = write_sync_reg(SCR_HOST_TO_READER_DONE, dev);
  336. if (rc <= 0) {
  337. DEBUGP(5, dev, "write_sync_reg c=%.2zx\n", rc);
  338. DEBUGP(2, dev, "<- cm4040_write (failed)\n");
  339. if (rc == -ERESTARTSYS)
  340. return rc;
  341. else
  342. return -EIO;
  343. }
  344. DEBUGP(2, dev, "<- cm4040_write (successfully)\n");
  345. return count;
  346. }
  347. static __poll_t cm4040_poll(struct file *filp, poll_table *wait)
  348. {
  349. struct reader_dev *dev = filp->private_data;
  350. __poll_t mask = 0;
  351. poll_wait(filp, &dev->poll_wait, wait);
  352. if (test_and_clear_bit(BS_READABLE, &dev->buffer_status))
  353. mask |= EPOLLIN | EPOLLRDNORM;
  354. if (test_and_clear_bit(BS_WRITABLE, &dev->buffer_status))
  355. mask |= EPOLLOUT | EPOLLWRNORM;
  356. DEBUGP(2, dev, "<- cm4040_poll(%u)\n", mask);
  357. return mask;
  358. }
  359. static int cm4040_open(struct inode *inode, struct file *filp)
  360. {
  361. struct reader_dev *dev;
  362. struct pcmcia_device *link;
  363. int minor = iminor(inode);
  364. int ret;
  365. if (minor >= CM_MAX_DEV)
  366. return -ENODEV;
  367. mutex_lock(&cm4040_mutex);
  368. link = dev_table[minor];
  369. if (link == NULL || !pcmcia_dev_present(link)) {
  370. ret = -ENODEV;
  371. goto out;
  372. }
  373. if (link->open) {
  374. ret = -EBUSY;
  375. goto out;
  376. }
  377. dev = link->priv;
  378. filp->private_data = dev;
  379. if (filp->f_flags & O_NONBLOCK) {
  380. DEBUGP(4, dev, "filep->f_flags O_NONBLOCK set\n");
  381. ret = -EAGAIN;
  382. goto out;
  383. }
  384. link->open = 1;
  385. mod_timer(&dev->poll_timer, jiffies + POLL_PERIOD);
  386. DEBUGP(2, dev, "<- cm4040_open (successfully)\n");
  387. ret = nonseekable_open(inode, filp);
  388. out:
  389. mutex_unlock(&cm4040_mutex);
  390. return ret;
  391. }
  392. static int cm4040_close(struct inode *inode, struct file *filp)
  393. {
  394. struct reader_dev *dev = filp->private_data;
  395. struct pcmcia_device *link;
  396. int minor = iminor(inode);
  397. DEBUGP(2, dev, "-> cm4040_close(maj/min=%d.%d)\n", imajor(inode),
  398. iminor(inode));
  399. if (minor >= CM_MAX_DEV)
  400. return -ENODEV;
  401. link = dev_table[minor];
  402. if (link == NULL)
  403. return -ENODEV;
  404. cm4040_stop_poll(dev);
  405. link->open = 0;
  406. wake_up(&dev->devq);
  407. DEBUGP(2, dev, "<- cm4040_close\n");
  408. return 0;
  409. }
  410. static void cm4040_reader_release(struct pcmcia_device *link)
  411. {
  412. struct reader_dev *dev = link->priv;
  413. DEBUGP(3, dev, "-> cm4040_reader_release\n");
  414. while (link->open) {
  415. DEBUGP(3, dev, MODULE_NAME ": delaying release "
  416. "until process has terminated\n");
  417. wait_event(dev->devq, (link->open == 0));
  418. }
  419. DEBUGP(3, dev, "<- cm4040_reader_release\n");
  420. return;
  421. }
  422. static int cm4040_config_check(struct pcmcia_device *p_dev, void *priv_data)
  423. {
  424. return pcmcia_request_io(p_dev);
  425. }
  426. static int reader_config(struct pcmcia_device *link, int devno)
  427. {
  428. struct reader_dev *dev;
  429. int fail_rc;
  430. link->config_flags |= CONF_AUTO_SET_IO;
  431. if (pcmcia_loop_config(link, cm4040_config_check, NULL))
  432. goto cs_release;
  433. fail_rc = pcmcia_enable_device(link);
  434. if (fail_rc != 0) {
  435. dev_info(&link->dev, "pcmcia_enable_device failed 0x%x\n",
  436. fail_rc);
  437. goto cs_release;
  438. }
  439. dev = link->priv;
  440. DEBUGP(2, dev, "device " DEVICE_NAME "%d at %pR\n", devno,
  441. link->resource[0]);
  442. DEBUGP(2, dev, "<- reader_config (succ)\n");
  443. return 0;
  444. cs_release:
  445. reader_release(link);
  446. return -ENODEV;
  447. }
  448. static void reader_release(struct pcmcia_device *link)
  449. {
  450. cm4040_reader_release(link);
  451. pcmcia_disable_device(link);
  452. }
  453. static int reader_probe(struct pcmcia_device *link)
  454. {
  455. struct reader_dev *dev;
  456. int i, ret;
  457. for (i = 0; i < CM_MAX_DEV; i++) {
  458. if (dev_table[i] == NULL)
  459. break;
  460. }
  461. if (i == CM_MAX_DEV)
  462. return -ENODEV;
  463. dev = kzalloc(sizeof(struct reader_dev), GFP_KERNEL);
  464. if (dev == NULL)
  465. return -ENOMEM;
  466. dev->timeout = CCID_DRIVER_MINIMUM_TIMEOUT;
  467. dev->buffer_status = 0;
  468. link->priv = dev;
  469. dev->p_dev = link;
  470. dev_table[i] = link;
  471. init_waitqueue_head(&dev->devq);
  472. init_waitqueue_head(&dev->poll_wait);
  473. init_waitqueue_head(&dev->read_wait);
  474. init_waitqueue_head(&dev->write_wait);
  475. timer_setup(&dev->poll_timer, cm4040_do_poll, 0);
  476. ret = reader_config(link, i);
  477. if (ret) {
  478. dev_table[i] = NULL;
  479. kfree(dev);
  480. return ret;
  481. }
  482. device_create(cmx_class, NULL, MKDEV(major, i), NULL, "cmx%d", i);
  483. return 0;
  484. }
  485. static void reader_detach(struct pcmcia_device *link)
  486. {
  487. struct reader_dev *dev = link->priv;
  488. int devno;
  489. /* find device */
  490. for (devno = 0; devno < CM_MAX_DEV; devno++) {
  491. if (dev_table[devno] == link)
  492. break;
  493. }
  494. if (devno == CM_MAX_DEV)
  495. return;
  496. reader_release(link);
  497. dev_table[devno] = NULL;
  498. kfree(dev);
  499. device_destroy(cmx_class, MKDEV(major, devno));
  500. return;
  501. }
  502. static const struct file_operations reader_fops = {
  503. .owner = THIS_MODULE,
  504. .read = cm4040_read,
  505. .write = cm4040_write,
  506. .open = cm4040_open,
  507. .release = cm4040_close,
  508. .poll = cm4040_poll,
  509. .llseek = no_llseek,
  510. };
  511. static const struct pcmcia_device_id cm4040_ids[] = {
  512. PCMCIA_DEVICE_MANF_CARD(0x0223, 0x0200),
  513. PCMCIA_DEVICE_PROD_ID12("OMNIKEY", "CardMan 4040",
  514. 0xE32CDD8C, 0x8F23318B),
  515. PCMCIA_DEVICE_NULL,
  516. };
  517. MODULE_DEVICE_TABLE(pcmcia, cm4040_ids);
  518. static struct pcmcia_driver reader_driver = {
  519. .owner = THIS_MODULE,
  520. .name = "cm4040_cs",
  521. .probe = reader_probe,
  522. .remove = reader_detach,
  523. .id_table = cm4040_ids,
  524. };
  525. static int __init cm4040_init(void)
  526. {
  527. int rc;
  528. cmx_class = class_create(THIS_MODULE, "cardman_4040");
  529. if (IS_ERR(cmx_class))
  530. return PTR_ERR(cmx_class);
  531. major = register_chrdev(0, DEVICE_NAME, &reader_fops);
  532. if (major < 0) {
  533. printk(KERN_WARNING MODULE_NAME
  534. ": could not get major number\n");
  535. class_destroy(cmx_class);
  536. return major;
  537. }
  538. rc = pcmcia_register_driver(&reader_driver);
  539. if (rc < 0) {
  540. unregister_chrdev(major, DEVICE_NAME);
  541. class_destroy(cmx_class);
  542. return rc;
  543. }
  544. return 0;
  545. }
  546. static void __exit cm4040_exit(void)
  547. {
  548. pcmcia_unregister_driver(&reader_driver);
  549. unregister_chrdev(major, DEVICE_NAME);
  550. class_destroy(cmx_class);
  551. }
  552. module_init(cm4040_init);
  553. module_exit(cm4040_exit);
  554. MODULE_LICENSE("Dual BSD/GPL");