pc8736x_gpio.c 8.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /* linux/drivers/char/pc8736x_gpio.c
  3. National Semiconductor PC8736x GPIO driver. Allows a user space
  4. process to play with the GPIO pins.
  5. Copyright (c) 2005,2006 Jim Cromie <jim.cromie@gmail.com>
  6. adapted from linux/drivers/char/scx200_gpio.c
  7. Copyright (c) 2001,2002 Christer Weinigel <wingel@nano-system.com>,
  8. */
  9. #include <linux/fs.h>
  10. #include <linux/module.h>
  11. #include <linux/errno.h>
  12. #include <linux/kernel.h>
  13. #include <linux/init.h>
  14. #include <linux/cdev.h>
  15. #include <linux/io.h>
  16. #include <linux/ioport.h>
  17. #include <linux/mutex.h>
  18. #include <linux/nsc_gpio.h>
  19. #include <linux/platform_device.h>
  20. #include <linux/uaccess.h>
  21. #define DEVNAME "pc8736x_gpio"
  22. MODULE_AUTHOR("Jim Cromie <jim.cromie@gmail.com>");
  23. MODULE_DESCRIPTION("NatSemi/Winbond PC-8736x GPIO Pin Driver");
  24. MODULE_LICENSE("GPL");
  25. static int major; /* default to dynamic major */
  26. module_param(major, int, 0);
  27. MODULE_PARM_DESC(major, "Major device number");
  28. static DEFINE_MUTEX(pc8736x_gpio_config_lock);
  29. static unsigned pc8736x_gpio_base;
  30. static u8 pc8736x_gpio_shadow[4];
  31. #define SIO_BASE1 0x2E /* 1st command-reg to check */
  32. #define SIO_BASE2 0x4E /* alt command-reg to check */
  33. #define SIO_SID 0x20 /* SuperI/O ID Register */
  34. #define SIO_SID_PC87365 0xe5 /* Expected value in ID Register for PC87365 */
  35. #define SIO_SID_PC87366 0xe9 /* Expected value in ID Register for PC87366 */
  36. #define SIO_CF1 0x21 /* chip config, bit0 is chip enable */
  37. #define PC8736X_GPIO_RANGE 16 /* ioaddr range */
  38. #define PC8736X_GPIO_CT 32 /* minors matching 4 8 bit ports */
  39. #define SIO_UNIT_SEL 0x7 /* unit select reg */
  40. #define SIO_UNIT_ACT 0x30 /* unit enable */
  41. #define SIO_GPIO_UNIT 0x7 /* unit number of GPIO */
  42. #define SIO_VLM_UNIT 0x0D
  43. #define SIO_TMS_UNIT 0x0E
  44. /* config-space addrs to read/write each unit's runtime addr */
  45. #define SIO_BASE_HADDR 0x60
  46. #define SIO_BASE_LADDR 0x61
  47. /* GPIO config-space pin-control addresses */
  48. #define SIO_GPIO_PIN_SELECT 0xF0
  49. #define SIO_GPIO_PIN_CONFIG 0xF1
  50. #define SIO_GPIO_PIN_EVENT 0xF2
  51. static unsigned char superio_cmd = 0;
  52. static unsigned char selected_device = 0xFF; /* bogus start val */
  53. /* GPIO port runtime access, functionality */
  54. static int port_offset[] = { 0, 4, 8, 10 }; /* non-uniform offsets ! */
  55. /* static int event_capable[] = { 1, 1, 0, 0 }; ports 2,3 are hobbled */
  56. #define PORT_OUT 0
  57. #define PORT_IN 1
  58. #define PORT_EVT_EN 2
  59. #define PORT_EVT_STST 3
  60. static struct platform_device *pdev; /* use in dev_*() */
  61. static inline void superio_outb(int addr, int val)
  62. {
  63. outb_p(addr, superio_cmd);
  64. outb_p(val, superio_cmd + 1);
  65. }
  66. static inline int superio_inb(int addr)
  67. {
  68. outb_p(addr, superio_cmd);
  69. return inb_p(superio_cmd + 1);
  70. }
  71. static int pc8736x_superio_present(void)
  72. {
  73. int id;
  74. /* try the 2 possible values, read a hardware reg to verify */
  75. superio_cmd = SIO_BASE1;
  76. id = superio_inb(SIO_SID);
  77. if (id == SIO_SID_PC87365 || id == SIO_SID_PC87366)
  78. return superio_cmd;
  79. superio_cmd = SIO_BASE2;
  80. id = superio_inb(SIO_SID);
  81. if (id == SIO_SID_PC87365 || id == SIO_SID_PC87366)
  82. return superio_cmd;
  83. return 0;
  84. }
  85. static void device_select(unsigned devldn)
  86. {
  87. superio_outb(SIO_UNIT_SEL, devldn);
  88. selected_device = devldn;
  89. }
  90. static void select_pin(unsigned iminor)
  91. {
  92. /* select GPIO port/pin from device minor number */
  93. device_select(SIO_GPIO_UNIT);
  94. superio_outb(SIO_GPIO_PIN_SELECT,
  95. ((iminor << 1) & 0xF0) | (iminor & 0x7));
  96. }
  97. static inline u32 pc8736x_gpio_configure_fn(unsigned index, u32 mask, u32 bits,
  98. u32 func_slct)
  99. {
  100. u32 config, new_config;
  101. mutex_lock(&pc8736x_gpio_config_lock);
  102. device_select(SIO_GPIO_UNIT);
  103. select_pin(index);
  104. /* read current config value */
  105. config = superio_inb(func_slct);
  106. /* set new config */
  107. new_config = (config & mask) | bits;
  108. superio_outb(func_slct, new_config);
  109. mutex_unlock(&pc8736x_gpio_config_lock);
  110. return config;
  111. }
  112. static u32 pc8736x_gpio_configure(unsigned index, u32 mask, u32 bits)
  113. {
  114. return pc8736x_gpio_configure_fn(index, mask, bits,
  115. SIO_GPIO_PIN_CONFIG);
  116. }
  117. static int pc8736x_gpio_get(unsigned minor)
  118. {
  119. int port, bit, val;
  120. port = minor >> 3;
  121. bit = minor & 7;
  122. val = inb_p(pc8736x_gpio_base + port_offset[port] + PORT_IN);
  123. val >>= bit;
  124. val &= 1;
  125. dev_dbg(&pdev->dev, "_gpio_get(%d from %x bit %d) == val %d\n",
  126. minor, pc8736x_gpio_base + port_offset[port] + PORT_IN, bit,
  127. val);
  128. return val;
  129. }
  130. static void pc8736x_gpio_set(unsigned minor, int val)
  131. {
  132. int port, bit, curval;
  133. minor &= 0x1f;
  134. port = minor >> 3;
  135. bit = minor & 7;
  136. curval = inb_p(pc8736x_gpio_base + port_offset[port] + PORT_OUT);
  137. dev_dbg(&pdev->dev, "addr:%x cur:%x bit-pos:%d cur-bit:%x + new:%d -> bit-new:%d\n",
  138. pc8736x_gpio_base + port_offset[port] + PORT_OUT,
  139. curval, bit, (curval & ~(1 << bit)), val, (val << bit));
  140. val = (curval & ~(1 << bit)) | (val << bit);
  141. dev_dbg(&pdev->dev, "gpio_set(minor:%d port:%d bit:%d)"
  142. " %2x -> %2x\n", minor, port, bit, curval, val);
  143. outb_p(val, pc8736x_gpio_base + port_offset[port] + PORT_OUT);
  144. curval = inb_p(pc8736x_gpio_base + port_offset[port] + PORT_OUT);
  145. val = inb_p(pc8736x_gpio_base + port_offset[port] + PORT_IN);
  146. dev_dbg(&pdev->dev, "wrote %x, read: %x\n", curval, val);
  147. pc8736x_gpio_shadow[port] = val;
  148. }
  149. static int pc8736x_gpio_current(unsigned minor)
  150. {
  151. int port, bit;
  152. minor &= 0x1f;
  153. port = minor >> 3;
  154. bit = minor & 7;
  155. return ((pc8736x_gpio_shadow[port] >> bit) & 0x01);
  156. }
  157. static void pc8736x_gpio_change(unsigned index)
  158. {
  159. pc8736x_gpio_set(index, !pc8736x_gpio_current(index));
  160. }
  161. static struct nsc_gpio_ops pc8736x_gpio_ops = {
  162. .owner = THIS_MODULE,
  163. .gpio_config = pc8736x_gpio_configure,
  164. .gpio_dump = nsc_gpio_dump,
  165. .gpio_get = pc8736x_gpio_get,
  166. .gpio_set = pc8736x_gpio_set,
  167. .gpio_change = pc8736x_gpio_change,
  168. .gpio_current = pc8736x_gpio_current
  169. };
  170. static int pc8736x_gpio_open(struct inode *inode, struct file *file)
  171. {
  172. unsigned m = iminor(inode);
  173. file->private_data = &pc8736x_gpio_ops;
  174. dev_dbg(&pdev->dev, "open %d\n", m);
  175. if (m >= PC8736X_GPIO_CT)
  176. return -EINVAL;
  177. return nonseekable_open(inode, file);
  178. }
  179. static const struct file_operations pc8736x_gpio_fileops = {
  180. .owner = THIS_MODULE,
  181. .open = pc8736x_gpio_open,
  182. .write = nsc_gpio_write,
  183. .read = nsc_gpio_read,
  184. .llseek = no_llseek,
  185. };
  186. static void __init pc8736x_init_shadow(void)
  187. {
  188. int port;
  189. /* read the current values driven on the GPIO signals */
  190. for (port = 0; port < 4; ++port)
  191. pc8736x_gpio_shadow[port]
  192. = inb_p(pc8736x_gpio_base + port_offset[port]
  193. + PORT_OUT);
  194. }
  195. static struct cdev pc8736x_gpio_cdev;
  196. static int __init pc8736x_gpio_init(void)
  197. {
  198. int rc;
  199. dev_t devid;
  200. pdev = platform_device_alloc(DEVNAME, 0);
  201. if (!pdev)
  202. return -ENOMEM;
  203. rc = platform_device_add(pdev);
  204. if (rc) {
  205. rc = -ENODEV;
  206. goto undo_platform_dev_alloc;
  207. }
  208. dev_info(&pdev->dev, "NatSemi pc8736x GPIO Driver Initializing\n");
  209. if (!pc8736x_superio_present()) {
  210. rc = -ENODEV;
  211. dev_err(&pdev->dev, "no device found\n");
  212. goto undo_platform_dev_add;
  213. }
  214. pc8736x_gpio_ops.dev = &pdev->dev;
  215. /* Verify that chip and it's GPIO unit are both enabled.
  216. My BIOS does this, so I take minimum action here
  217. */
  218. rc = superio_inb(SIO_CF1);
  219. if (!(rc & 0x01)) {
  220. rc = -ENODEV;
  221. dev_err(&pdev->dev, "device not enabled\n");
  222. goto undo_platform_dev_add;
  223. }
  224. device_select(SIO_GPIO_UNIT);
  225. if (!superio_inb(SIO_UNIT_ACT)) {
  226. rc = -ENODEV;
  227. dev_err(&pdev->dev, "GPIO unit not enabled\n");
  228. goto undo_platform_dev_add;
  229. }
  230. /* read the GPIO unit base addr that chip responds to */
  231. pc8736x_gpio_base = (superio_inb(SIO_BASE_HADDR) << 8
  232. | superio_inb(SIO_BASE_LADDR));
  233. if (!request_region(pc8736x_gpio_base, PC8736X_GPIO_RANGE, DEVNAME)) {
  234. rc = -ENODEV;
  235. dev_err(&pdev->dev, "GPIO ioport %x busy\n",
  236. pc8736x_gpio_base);
  237. goto undo_platform_dev_add;
  238. }
  239. dev_info(&pdev->dev, "GPIO ioport %x reserved\n", pc8736x_gpio_base);
  240. if (major) {
  241. devid = MKDEV(major, 0);
  242. rc = register_chrdev_region(devid, PC8736X_GPIO_CT, DEVNAME);
  243. } else {
  244. rc = alloc_chrdev_region(&devid, 0, PC8736X_GPIO_CT, DEVNAME);
  245. major = MAJOR(devid);
  246. }
  247. if (rc < 0) {
  248. dev_err(&pdev->dev, "register-chrdev failed: %d\n", rc);
  249. goto undo_request_region;
  250. }
  251. if (!major) {
  252. major = rc;
  253. dev_dbg(&pdev->dev, "got dynamic major %d\n", major);
  254. }
  255. pc8736x_init_shadow();
  256. /* ignore minor errs, and succeed */
  257. cdev_init(&pc8736x_gpio_cdev, &pc8736x_gpio_fileops);
  258. cdev_add(&pc8736x_gpio_cdev, devid, PC8736X_GPIO_CT);
  259. return 0;
  260. undo_request_region:
  261. release_region(pc8736x_gpio_base, PC8736X_GPIO_RANGE);
  262. undo_platform_dev_add:
  263. platform_device_del(pdev);
  264. undo_platform_dev_alloc:
  265. platform_device_put(pdev);
  266. return rc;
  267. }
  268. static void __exit pc8736x_gpio_cleanup(void)
  269. {
  270. dev_dbg(&pdev->dev, "cleanup\n");
  271. cdev_del(&pc8736x_gpio_cdev);
  272. unregister_chrdev_region(MKDEV(major,0), PC8736X_GPIO_CT);
  273. release_region(pc8736x_gpio_base, PC8736X_GPIO_RANGE);
  274. platform_device_unregister(pdev);
  275. }
  276. module_init(pc8736x_gpio_init);
  277. module_exit(pc8736x_gpio_cleanup);