xsysace.c 33 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Xilinx SystemACE device driver
  4. *
  5. * Copyright 2007 Secret Lab Technologies Ltd.
  6. */
  7. /*
  8. * The SystemACE chip is designed to configure FPGAs by loading an FPGA
  9. * bitstream from a file on a CF card and squirting it into FPGAs connected
  10. * to the SystemACE JTAG chain. It also has the advantage of providing an
  11. * MPU interface which can be used to control the FPGA configuration process
  12. * and to use the attached CF card for general purpose storage.
  13. *
  14. * This driver is a block device driver for the SystemACE.
  15. *
  16. * Initialization:
  17. * The driver registers itself as a platform_device driver at module
  18. * load time. The platform bus will take care of calling the
  19. * ace_probe() method for all SystemACE instances in the system. Any
  20. * number of SystemACE instances are supported. ace_probe() calls
  21. * ace_setup() which initialized all data structures, reads the CF
  22. * id structure and registers the device.
  23. *
  24. * Processing:
  25. * Just about all of the heavy lifting in this driver is performed by
  26. * a Finite State Machine (FSM). The driver needs to wait on a number
  27. * of events; some raised by interrupts, some which need to be polled
  28. * for. Describing all of the behaviour in a FSM seems to be the
  29. * easiest way to keep the complexity low and make it easy to
  30. * understand what the driver is doing. If the block ops or the
  31. * request function need to interact with the hardware, then they
  32. * simply need to flag the request and kick of FSM processing.
  33. *
  34. * The FSM itself is atomic-safe code which can be run from any
  35. * context. The general process flow is:
  36. * 1. obtain the ace->lock spinlock.
  37. * 2. loop on ace_fsm_dostate() until the ace->fsm_continue flag is
  38. * cleared.
  39. * 3. release the lock.
  40. *
  41. * Individual states do not sleep in any way. If a condition needs to
  42. * be waited for then the state much clear the fsm_continue flag and
  43. * either schedule the FSM to be run again at a later time, or expect
  44. * an interrupt to call the FSM when the desired condition is met.
  45. *
  46. * In normal operation, the FSM is processed at interrupt context
  47. * either when the driver's tasklet is scheduled, or when an irq is
  48. * raised by the hardware. The tasklet can be scheduled at any time.
  49. * The request method in particular schedules the tasklet when a new
  50. * request has been indicated by the block layer. Once started, the
  51. * FSM proceeds as far as it can processing the request until it
  52. * needs on a hardware event. At this point, it must yield execution.
  53. *
  54. * A state has two options when yielding execution:
  55. * 1. ace_fsm_yield()
  56. * - Call if need to poll for event.
  57. * - clears the fsm_continue flag to exit the processing loop
  58. * - reschedules the tasklet to run again as soon as possible
  59. * 2. ace_fsm_yieldirq()
  60. * - Call if an irq is expected from the HW
  61. * - clears the fsm_continue flag to exit the processing loop
  62. * - does not reschedule the tasklet so the FSM will not be processed
  63. * again until an irq is received.
  64. * After calling a yield function, the state must return control back
  65. * to the FSM main loop.
  66. *
  67. * Additionally, the driver maintains a kernel timer which can process
  68. * the FSM. If the FSM gets stalled, typically due to a missed
  69. * interrupt, then the kernel timer will expire and the driver can
  70. * continue where it left off.
  71. *
  72. * To Do:
  73. * - Add FPGA configuration control interface.
  74. * - Request major number from lanana
  75. */
  76. #undef DEBUG
  77. #include <linux/module.h>
  78. #include <linux/ctype.h>
  79. #include <linux/init.h>
  80. #include <linux/interrupt.h>
  81. #include <linux/errno.h>
  82. #include <linux/kernel.h>
  83. #include <linux/delay.h>
  84. #include <linux/slab.h>
  85. #include <linux/blk-mq.h>
  86. #include <linux/mutex.h>
  87. #include <linux/ata.h>
  88. #include <linux/hdreg.h>
  89. #include <linux/platform_device.h>
  90. #if defined(CONFIG_OF)
  91. #include <linux/of_address.h>
  92. #include <linux/of_device.h>
  93. #include <linux/of_platform.h>
  94. #endif
  95. MODULE_AUTHOR("Grant Likely <grant.likely@secretlab.ca>");
  96. MODULE_DESCRIPTION("Xilinx SystemACE device driver");
  97. MODULE_LICENSE("GPL");
  98. /* SystemACE register definitions */
  99. #define ACE_BUSMODE (0x00)
  100. #define ACE_STATUS (0x04)
  101. #define ACE_STATUS_CFGLOCK (0x00000001)
  102. #define ACE_STATUS_MPULOCK (0x00000002)
  103. #define ACE_STATUS_CFGERROR (0x00000004) /* config controller error */
  104. #define ACE_STATUS_CFCERROR (0x00000008) /* CF controller error */
  105. #define ACE_STATUS_CFDETECT (0x00000010)
  106. #define ACE_STATUS_DATABUFRDY (0x00000020)
  107. #define ACE_STATUS_DATABUFMODE (0x00000040)
  108. #define ACE_STATUS_CFGDONE (0x00000080)
  109. #define ACE_STATUS_RDYFORCFCMD (0x00000100)
  110. #define ACE_STATUS_CFGMODEPIN (0x00000200)
  111. #define ACE_STATUS_CFGADDR_MASK (0x0000e000)
  112. #define ACE_STATUS_CFBSY (0x00020000)
  113. #define ACE_STATUS_CFRDY (0x00040000)
  114. #define ACE_STATUS_CFDWF (0x00080000)
  115. #define ACE_STATUS_CFDSC (0x00100000)
  116. #define ACE_STATUS_CFDRQ (0x00200000)
  117. #define ACE_STATUS_CFCORR (0x00400000)
  118. #define ACE_STATUS_CFERR (0x00800000)
  119. #define ACE_ERROR (0x08)
  120. #define ACE_CFGLBA (0x0c)
  121. #define ACE_MPULBA (0x10)
  122. #define ACE_SECCNTCMD (0x14)
  123. #define ACE_SECCNTCMD_RESET (0x0100)
  124. #define ACE_SECCNTCMD_IDENTIFY (0x0200)
  125. #define ACE_SECCNTCMD_READ_DATA (0x0300)
  126. #define ACE_SECCNTCMD_WRITE_DATA (0x0400)
  127. #define ACE_SECCNTCMD_ABORT (0x0600)
  128. #define ACE_VERSION (0x16)
  129. #define ACE_VERSION_REVISION_MASK (0x00FF)
  130. #define ACE_VERSION_MINOR_MASK (0x0F00)
  131. #define ACE_VERSION_MAJOR_MASK (0xF000)
  132. #define ACE_CTRL (0x18)
  133. #define ACE_CTRL_FORCELOCKREQ (0x0001)
  134. #define ACE_CTRL_LOCKREQ (0x0002)
  135. #define ACE_CTRL_FORCECFGADDR (0x0004)
  136. #define ACE_CTRL_FORCECFGMODE (0x0008)
  137. #define ACE_CTRL_CFGMODE (0x0010)
  138. #define ACE_CTRL_CFGSTART (0x0020)
  139. #define ACE_CTRL_CFGSEL (0x0040)
  140. #define ACE_CTRL_CFGRESET (0x0080)
  141. #define ACE_CTRL_DATABUFRDYIRQ (0x0100)
  142. #define ACE_CTRL_ERRORIRQ (0x0200)
  143. #define ACE_CTRL_CFGDONEIRQ (0x0400)
  144. #define ACE_CTRL_RESETIRQ (0x0800)
  145. #define ACE_CTRL_CFGPROG (0x1000)
  146. #define ACE_CTRL_CFGADDR_MASK (0xe000)
  147. #define ACE_FATSTAT (0x1c)
  148. #define ACE_NUM_MINORS 16
  149. #define ACE_SECTOR_SIZE (512)
  150. #define ACE_FIFO_SIZE (32)
  151. #define ACE_BUF_PER_SECTOR (ACE_SECTOR_SIZE / ACE_FIFO_SIZE)
  152. #define ACE_BUS_WIDTH_8 0
  153. #define ACE_BUS_WIDTH_16 1
  154. struct ace_reg_ops;
  155. struct ace_device {
  156. /* driver state data */
  157. int id;
  158. int media_change;
  159. int users;
  160. struct list_head list;
  161. /* finite state machine data */
  162. struct tasklet_struct fsm_tasklet;
  163. uint fsm_task; /* Current activity (ACE_TASK_*) */
  164. uint fsm_state; /* Current state (ACE_FSM_STATE_*) */
  165. uint fsm_continue_flag; /* cleared to exit FSM mainloop */
  166. uint fsm_iter_num;
  167. struct timer_list stall_timer;
  168. /* Transfer state/result, use for both id and block request */
  169. struct request *req; /* request being processed */
  170. void *data_ptr; /* pointer to I/O buffer */
  171. int data_count; /* number of buffers remaining */
  172. int data_result; /* Result of transfer; 0 := success */
  173. int id_req_count; /* count of id requests */
  174. int id_result;
  175. struct completion id_completion; /* used when id req finishes */
  176. int in_irq;
  177. /* Details of hardware device */
  178. resource_size_t physaddr;
  179. void __iomem *baseaddr;
  180. int irq;
  181. int bus_width; /* 0 := 8 bit; 1 := 16 bit */
  182. struct ace_reg_ops *reg_ops;
  183. int lock_count;
  184. /* Block device data structures */
  185. spinlock_t lock;
  186. struct device *dev;
  187. struct request_queue *queue;
  188. struct gendisk *gd;
  189. struct blk_mq_tag_set tag_set;
  190. struct list_head rq_list;
  191. /* Inserted CF card parameters */
  192. u16 cf_id[ATA_ID_WORDS];
  193. };
  194. static DEFINE_MUTEX(xsysace_mutex);
  195. static int ace_major;
  196. /* ---------------------------------------------------------------------
  197. * Low level register access
  198. */
  199. struct ace_reg_ops {
  200. u16(*in) (struct ace_device * ace, int reg);
  201. void (*out) (struct ace_device * ace, int reg, u16 val);
  202. void (*datain) (struct ace_device * ace);
  203. void (*dataout) (struct ace_device * ace);
  204. };
  205. /* 8 Bit bus width */
  206. static u16 ace_in_8(struct ace_device *ace, int reg)
  207. {
  208. void __iomem *r = ace->baseaddr + reg;
  209. return in_8(r) | (in_8(r + 1) << 8);
  210. }
  211. static void ace_out_8(struct ace_device *ace, int reg, u16 val)
  212. {
  213. void __iomem *r = ace->baseaddr + reg;
  214. out_8(r, val);
  215. out_8(r + 1, val >> 8);
  216. }
  217. static void ace_datain_8(struct ace_device *ace)
  218. {
  219. void __iomem *r = ace->baseaddr + 0x40;
  220. u8 *dst = ace->data_ptr;
  221. int i = ACE_FIFO_SIZE;
  222. while (i--)
  223. *dst++ = in_8(r++);
  224. ace->data_ptr = dst;
  225. }
  226. static void ace_dataout_8(struct ace_device *ace)
  227. {
  228. void __iomem *r = ace->baseaddr + 0x40;
  229. u8 *src = ace->data_ptr;
  230. int i = ACE_FIFO_SIZE;
  231. while (i--)
  232. out_8(r++, *src++);
  233. ace->data_ptr = src;
  234. }
  235. static struct ace_reg_ops ace_reg_8_ops = {
  236. .in = ace_in_8,
  237. .out = ace_out_8,
  238. .datain = ace_datain_8,
  239. .dataout = ace_dataout_8,
  240. };
  241. /* 16 bit big endian bus attachment */
  242. static u16 ace_in_be16(struct ace_device *ace, int reg)
  243. {
  244. return in_be16(ace->baseaddr + reg);
  245. }
  246. static void ace_out_be16(struct ace_device *ace, int reg, u16 val)
  247. {
  248. out_be16(ace->baseaddr + reg, val);
  249. }
  250. static void ace_datain_be16(struct ace_device *ace)
  251. {
  252. int i = ACE_FIFO_SIZE / 2;
  253. u16 *dst = ace->data_ptr;
  254. while (i--)
  255. *dst++ = in_le16(ace->baseaddr + 0x40);
  256. ace->data_ptr = dst;
  257. }
  258. static void ace_dataout_be16(struct ace_device *ace)
  259. {
  260. int i = ACE_FIFO_SIZE / 2;
  261. u16 *src = ace->data_ptr;
  262. while (i--)
  263. out_le16(ace->baseaddr + 0x40, *src++);
  264. ace->data_ptr = src;
  265. }
  266. /* 16 bit little endian bus attachment */
  267. static u16 ace_in_le16(struct ace_device *ace, int reg)
  268. {
  269. return in_le16(ace->baseaddr + reg);
  270. }
  271. static void ace_out_le16(struct ace_device *ace, int reg, u16 val)
  272. {
  273. out_le16(ace->baseaddr + reg, val);
  274. }
  275. static void ace_datain_le16(struct ace_device *ace)
  276. {
  277. int i = ACE_FIFO_SIZE / 2;
  278. u16 *dst = ace->data_ptr;
  279. while (i--)
  280. *dst++ = in_be16(ace->baseaddr + 0x40);
  281. ace->data_ptr = dst;
  282. }
  283. static void ace_dataout_le16(struct ace_device *ace)
  284. {
  285. int i = ACE_FIFO_SIZE / 2;
  286. u16 *src = ace->data_ptr;
  287. while (i--)
  288. out_be16(ace->baseaddr + 0x40, *src++);
  289. ace->data_ptr = src;
  290. }
  291. static struct ace_reg_ops ace_reg_be16_ops = {
  292. .in = ace_in_be16,
  293. .out = ace_out_be16,
  294. .datain = ace_datain_be16,
  295. .dataout = ace_dataout_be16,
  296. };
  297. static struct ace_reg_ops ace_reg_le16_ops = {
  298. .in = ace_in_le16,
  299. .out = ace_out_le16,
  300. .datain = ace_datain_le16,
  301. .dataout = ace_dataout_le16,
  302. };
  303. static inline u16 ace_in(struct ace_device *ace, int reg)
  304. {
  305. return ace->reg_ops->in(ace, reg);
  306. }
  307. static inline u32 ace_in32(struct ace_device *ace, int reg)
  308. {
  309. return ace_in(ace, reg) | (ace_in(ace, reg + 2) << 16);
  310. }
  311. static inline void ace_out(struct ace_device *ace, int reg, u16 val)
  312. {
  313. ace->reg_ops->out(ace, reg, val);
  314. }
  315. static inline void ace_out32(struct ace_device *ace, int reg, u32 val)
  316. {
  317. ace_out(ace, reg, val);
  318. ace_out(ace, reg + 2, val >> 16);
  319. }
  320. /* ---------------------------------------------------------------------
  321. * Debug support functions
  322. */
  323. #if defined(DEBUG)
  324. static void ace_dump_mem(void *base, int len)
  325. {
  326. const char *ptr = base;
  327. int i, j;
  328. for (i = 0; i < len; i += 16) {
  329. printk(KERN_INFO "%.8x:", i);
  330. for (j = 0; j < 16; j++) {
  331. if (!(j % 4))
  332. printk(" ");
  333. printk("%.2x", ptr[i + j]);
  334. }
  335. printk(" ");
  336. for (j = 0; j < 16; j++)
  337. printk("%c", isprint(ptr[i + j]) ? ptr[i + j] : '.');
  338. printk("\n");
  339. }
  340. }
  341. #else
  342. static inline void ace_dump_mem(void *base, int len)
  343. {
  344. }
  345. #endif
  346. static void ace_dump_regs(struct ace_device *ace)
  347. {
  348. dev_info(ace->dev,
  349. " ctrl: %.8x seccnt/cmd: %.4x ver:%.4x\n"
  350. " status:%.8x mpu_lba:%.8x busmode:%4x\n"
  351. " error: %.8x cfg_lba:%.8x fatstat:%.4x\n",
  352. ace_in32(ace, ACE_CTRL),
  353. ace_in(ace, ACE_SECCNTCMD),
  354. ace_in(ace, ACE_VERSION),
  355. ace_in32(ace, ACE_STATUS),
  356. ace_in32(ace, ACE_MPULBA),
  357. ace_in(ace, ACE_BUSMODE),
  358. ace_in32(ace, ACE_ERROR),
  359. ace_in32(ace, ACE_CFGLBA), ace_in(ace, ACE_FATSTAT));
  360. }
  361. static void ace_fix_driveid(u16 *id)
  362. {
  363. #if defined(__BIG_ENDIAN)
  364. int i;
  365. /* All half words have wrong byte order; swap the bytes */
  366. for (i = 0; i < ATA_ID_WORDS; i++, id++)
  367. *id = le16_to_cpu(*id);
  368. #endif
  369. }
  370. /* ---------------------------------------------------------------------
  371. * Finite State Machine (FSM) implementation
  372. */
  373. /* FSM tasks; used to direct state transitions */
  374. #define ACE_TASK_IDLE 0
  375. #define ACE_TASK_IDENTIFY 1
  376. #define ACE_TASK_READ 2
  377. #define ACE_TASK_WRITE 3
  378. #define ACE_FSM_NUM_TASKS 4
  379. /* FSM state definitions */
  380. #define ACE_FSM_STATE_IDLE 0
  381. #define ACE_FSM_STATE_REQ_LOCK 1
  382. #define ACE_FSM_STATE_WAIT_LOCK 2
  383. #define ACE_FSM_STATE_WAIT_CFREADY 3
  384. #define ACE_FSM_STATE_IDENTIFY_PREPARE 4
  385. #define ACE_FSM_STATE_IDENTIFY_TRANSFER 5
  386. #define ACE_FSM_STATE_IDENTIFY_COMPLETE 6
  387. #define ACE_FSM_STATE_REQ_PREPARE 7
  388. #define ACE_FSM_STATE_REQ_TRANSFER 8
  389. #define ACE_FSM_STATE_REQ_COMPLETE 9
  390. #define ACE_FSM_STATE_ERROR 10
  391. #define ACE_FSM_NUM_STATES 11
  392. /* Set flag to exit FSM loop and reschedule tasklet */
  393. static inline void ace_fsm_yieldpoll(struct ace_device *ace)
  394. {
  395. tasklet_schedule(&ace->fsm_tasklet);
  396. ace->fsm_continue_flag = 0;
  397. }
  398. static inline void ace_fsm_yield(struct ace_device *ace)
  399. {
  400. dev_dbg(ace->dev, "%s()\n", __func__);
  401. ace_fsm_yieldpoll(ace);
  402. }
  403. /* Set flag to exit FSM loop and wait for IRQ to reschedule tasklet */
  404. static inline void ace_fsm_yieldirq(struct ace_device *ace)
  405. {
  406. dev_dbg(ace->dev, "ace_fsm_yieldirq()\n");
  407. if (ace->irq > 0)
  408. ace->fsm_continue_flag = 0;
  409. else
  410. ace_fsm_yieldpoll(ace);
  411. }
  412. static bool ace_has_next_request(struct request_queue *q)
  413. {
  414. struct ace_device *ace = q->queuedata;
  415. return !list_empty(&ace->rq_list);
  416. }
  417. /* Get the next read/write request; ending requests that we don't handle */
  418. static struct request *ace_get_next_request(struct request_queue *q)
  419. {
  420. struct ace_device *ace = q->queuedata;
  421. struct request *rq;
  422. rq = list_first_entry_or_null(&ace->rq_list, struct request, queuelist);
  423. if (rq) {
  424. list_del_init(&rq->queuelist);
  425. blk_mq_start_request(rq);
  426. }
  427. return NULL;
  428. }
  429. static void ace_fsm_dostate(struct ace_device *ace)
  430. {
  431. struct request *req;
  432. u32 status;
  433. u16 val;
  434. int count;
  435. #if defined(DEBUG)
  436. dev_dbg(ace->dev, "fsm_state=%i, id_req_count=%i\n",
  437. ace->fsm_state, ace->id_req_count);
  438. #endif
  439. /* Verify that there is actually a CF in the slot. If not, then
  440. * bail out back to the idle state and wake up all the waiters */
  441. status = ace_in32(ace, ACE_STATUS);
  442. if ((status & ACE_STATUS_CFDETECT) == 0) {
  443. ace->fsm_state = ACE_FSM_STATE_IDLE;
  444. ace->media_change = 1;
  445. set_capacity(ace->gd, 0);
  446. dev_info(ace->dev, "No CF in slot\n");
  447. /* Drop all in-flight and pending requests */
  448. if (ace->req) {
  449. blk_mq_end_request(ace->req, BLK_STS_IOERR);
  450. ace->req = NULL;
  451. }
  452. while ((req = ace_get_next_request(ace->queue)) != NULL)
  453. blk_mq_end_request(req, BLK_STS_IOERR);
  454. /* Drop back to IDLE state and notify waiters */
  455. ace->fsm_state = ACE_FSM_STATE_IDLE;
  456. ace->id_result = -EIO;
  457. while (ace->id_req_count) {
  458. complete(&ace->id_completion);
  459. ace->id_req_count--;
  460. }
  461. }
  462. switch (ace->fsm_state) {
  463. case ACE_FSM_STATE_IDLE:
  464. /* See if there is anything to do */
  465. if (ace->id_req_count || ace_has_next_request(ace->queue)) {
  466. ace->fsm_iter_num++;
  467. ace->fsm_state = ACE_FSM_STATE_REQ_LOCK;
  468. mod_timer(&ace->stall_timer, jiffies + HZ);
  469. if (!timer_pending(&ace->stall_timer))
  470. add_timer(&ace->stall_timer);
  471. break;
  472. }
  473. del_timer(&ace->stall_timer);
  474. ace->fsm_continue_flag = 0;
  475. break;
  476. case ACE_FSM_STATE_REQ_LOCK:
  477. if (ace_in(ace, ACE_STATUS) & ACE_STATUS_MPULOCK) {
  478. /* Already have the lock, jump to next state */
  479. ace->fsm_state = ACE_FSM_STATE_WAIT_CFREADY;
  480. break;
  481. }
  482. /* Request the lock */
  483. val = ace_in(ace, ACE_CTRL);
  484. ace_out(ace, ACE_CTRL, val | ACE_CTRL_LOCKREQ);
  485. ace->fsm_state = ACE_FSM_STATE_WAIT_LOCK;
  486. break;
  487. case ACE_FSM_STATE_WAIT_LOCK:
  488. if (ace_in(ace, ACE_STATUS) & ACE_STATUS_MPULOCK) {
  489. /* got the lock; move to next state */
  490. ace->fsm_state = ACE_FSM_STATE_WAIT_CFREADY;
  491. break;
  492. }
  493. /* wait a bit for the lock */
  494. ace_fsm_yield(ace);
  495. break;
  496. case ACE_FSM_STATE_WAIT_CFREADY:
  497. status = ace_in32(ace, ACE_STATUS);
  498. if (!(status & ACE_STATUS_RDYFORCFCMD) ||
  499. (status & ACE_STATUS_CFBSY)) {
  500. /* CF card isn't ready; it needs to be polled */
  501. ace_fsm_yield(ace);
  502. break;
  503. }
  504. /* Device is ready for command; determine what to do next */
  505. if (ace->id_req_count)
  506. ace->fsm_state = ACE_FSM_STATE_IDENTIFY_PREPARE;
  507. else
  508. ace->fsm_state = ACE_FSM_STATE_REQ_PREPARE;
  509. break;
  510. case ACE_FSM_STATE_IDENTIFY_PREPARE:
  511. /* Send identify command */
  512. ace->fsm_task = ACE_TASK_IDENTIFY;
  513. ace->data_ptr = ace->cf_id;
  514. ace->data_count = ACE_BUF_PER_SECTOR;
  515. ace_out(ace, ACE_SECCNTCMD, ACE_SECCNTCMD_IDENTIFY);
  516. /* As per datasheet, put config controller in reset */
  517. val = ace_in(ace, ACE_CTRL);
  518. ace_out(ace, ACE_CTRL, val | ACE_CTRL_CFGRESET);
  519. /* irq handler takes over from this point; wait for the
  520. * transfer to complete */
  521. ace->fsm_state = ACE_FSM_STATE_IDENTIFY_TRANSFER;
  522. ace_fsm_yieldirq(ace);
  523. break;
  524. case ACE_FSM_STATE_IDENTIFY_TRANSFER:
  525. /* Check that the sysace is ready to receive data */
  526. status = ace_in32(ace, ACE_STATUS);
  527. if (status & ACE_STATUS_CFBSY) {
  528. dev_dbg(ace->dev, "CFBSY set; t=%i iter=%i dc=%i\n",
  529. ace->fsm_task, ace->fsm_iter_num,
  530. ace->data_count);
  531. ace_fsm_yield(ace);
  532. break;
  533. }
  534. if (!(status & ACE_STATUS_DATABUFRDY)) {
  535. ace_fsm_yield(ace);
  536. break;
  537. }
  538. /* Transfer the next buffer */
  539. ace->reg_ops->datain(ace);
  540. ace->data_count--;
  541. /* If there are still buffers to be transfers; jump out here */
  542. if (ace->data_count != 0) {
  543. ace_fsm_yieldirq(ace);
  544. break;
  545. }
  546. /* transfer finished; kick state machine */
  547. dev_dbg(ace->dev, "identify finished\n");
  548. ace->fsm_state = ACE_FSM_STATE_IDENTIFY_COMPLETE;
  549. break;
  550. case ACE_FSM_STATE_IDENTIFY_COMPLETE:
  551. ace_fix_driveid(ace->cf_id);
  552. ace_dump_mem(ace->cf_id, 512); /* Debug: Dump out disk ID */
  553. if (ace->data_result) {
  554. /* Error occurred, disable the disk */
  555. ace->media_change = 1;
  556. set_capacity(ace->gd, 0);
  557. dev_err(ace->dev, "error fetching CF id (%i)\n",
  558. ace->data_result);
  559. } else {
  560. ace->media_change = 0;
  561. /* Record disk parameters */
  562. set_capacity(ace->gd,
  563. ata_id_u32(ace->cf_id, ATA_ID_LBA_CAPACITY));
  564. dev_info(ace->dev, "capacity: %i sectors\n",
  565. ata_id_u32(ace->cf_id, ATA_ID_LBA_CAPACITY));
  566. }
  567. /* We're done, drop to IDLE state and notify waiters */
  568. ace->fsm_state = ACE_FSM_STATE_IDLE;
  569. ace->id_result = ace->data_result;
  570. while (ace->id_req_count) {
  571. complete(&ace->id_completion);
  572. ace->id_req_count--;
  573. }
  574. break;
  575. case ACE_FSM_STATE_REQ_PREPARE:
  576. req = ace_get_next_request(ace->queue);
  577. if (!req) {
  578. ace->fsm_state = ACE_FSM_STATE_IDLE;
  579. break;
  580. }
  581. /* Okay, it's a data request, set it up for transfer */
  582. dev_dbg(ace->dev,
  583. "request: sec=%llx hcnt=%x, ccnt=%x, dir=%i\n",
  584. (unsigned long long)blk_rq_pos(req),
  585. blk_rq_sectors(req), blk_rq_cur_sectors(req),
  586. rq_data_dir(req));
  587. ace->req = req;
  588. ace->data_ptr = bio_data(req->bio);
  589. ace->data_count = blk_rq_cur_sectors(req) * ACE_BUF_PER_SECTOR;
  590. ace_out32(ace, ACE_MPULBA, blk_rq_pos(req) & 0x0FFFFFFF);
  591. count = blk_rq_sectors(req);
  592. if (rq_data_dir(req)) {
  593. /* Kick off write request */
  594. dev_dbg(ace->dev, "write data\n");
  595. ace->fsm_task = ACE_TASK_WRITE;
  596. ace_out(ace, ACE_SECCNTCMD,
  597. count | ACE_SECCNTCMD_WRITE_DATA);
  598. } else {
  599. /* Kick off read request */
  600. dev_dbg(ace->dev, "read data\n");
  601. ace->fsm_task = ACE_TASK_READ;
  602. ace_out(ace, ACE_SECCNTCMD,
  603. count | ACE_SECCNTCMD_READ_DATA);
  604. }
  605. /* As per datasheet, put config controller in reset */
  606. val = ace_in(ace, ACE_CTRL);
  607. ace_out(ace, ACE_CTRL, val | ACE_CTRL_CFGRESET);
  608. /* Move to the transfer state. The systemace will raise
  609. * an interrupt once there is something to do
  610. */
  611. ace->fsm_state = ACE_FSM_STATE_REQ_TRANSFER;
  612. if (ace->fsm_task == ACE_TASK_READ)
  613. ace_fsm_yieldirq(ace); /* wait for data ready */
  614. break;
  615. case ACE_FSM_STATE_REQ_TRANSFER:
  616. /* Check that the sysace is ready to receive data */
  617. status = ace_in32(ace, ACE_STATUS);
  618. if (status & ACE_STATUS_CFBSY) {
  619. dev_dbg(ace->dev,
  620. "CFBSY set; t=%i iter=%i c=%i dc=%i irq=%i\n",
  621. ace->fsm_task, ace->fsm_iter_num,
  622. blk_rq_cur_sectors(ace->req) * 16,
  623. ace->data_count, ace->in_irq);
  624. ace_fsm_yield(ace); /* need to poll CFBSY bit */
  625. break;
  626. }
  627. if (!(status & ACE_STATUS_DATABUFRDY)) {
  628. dev_dbg(ace->dev,
  629. "DATABUF not set; t=%i iter=%i c=%i dc=%i irq=%i\n",
  630. ace->fsm_task, ace->fsm_iter_num,
  631. blk_rq_cur_sectors(ace->req) * 16,
  632. ace->data_count, ace->in_irq);
  633. ace_fsm_yieldirq(ace);
  634. break;
  635. }
  636. /* Transfer the next buffer */
  637. if (ace->fsm_task == ACE_TASK_WRITE)
  638. ace->reg_ops->dataout(ace);
  639. else
  640. ace->reg_ops->datain(ace);
  641. ace->data_count--;
  642. /* If there are still buffers to be transfers; jump out here */
  643. if (ace->data_count != 0) {
  644. ace_fsm_yieldirq(ace);
  645. break;
  646. }
  647. /* bio finished; is there another one? */
  648. if (blk_update_request(ace->req, BLK_STS_OK,
  649. blk_rq_cur_bytes(ace->req))) {
  650. /* dev_dbg(ace->dev, "next block; h=%u c=%u\n",
  651. * blk_rq_sectors(ace->req),
  652. * blk_rq_cur_sectors(ace->req));
  653. */
  654. ace->data_ptr = bio_data(ace->req->bio);
  655. ace->data_count = blk_rq_cur_sectors(ace->req) * 16;
  656. ace_fsm_yieldirq(ace);
  657. break;
  658. }
  659. ace->fsm_state = ACE_FSM_STATE_REQ_COMPLETE;
  660. break;
  661. case ACE_FSM_STATE_REQ_COMPLETE:
  662. ace->req = NULL;
  663. /* Finished request; go to idle state */
  664. ace->fsm_state = ACE_FSM_STATE_IDLE;
  665. break;
  666. default:
  667. ace->fsm_state = ACE_FSM_STATE_IDLE;
  668. break;
  669. }
  670. }
  671. static void ace_fsm_tasklet(unsigned long data)
  672. {
  673. struct ace_device *ace = (void *)data;
  674. unsigned long flags;
  675. spin_lock_irqsave(&ace->lock, flags);
  676. /* Loop over state machine until told to stop */
  677. ace->fsm_continue_flag = 1;
  678. while (ace->fsm_continue_flag)
  679. ace_fsm_dostate(ace);
  680. spin_unlock_irqrestore(&ace->lock, flags);
  681. }
  682. static void ace_stall_timer(struct timer_list *t)
  683. {
  684. struct ace_device *ace = from_timer(ace, t, stall_timer);
  685. unsigned long flags;
  686. dev_warn(ace->dev,
  687. "kicking stalled fsm; state=%i task=%i iter=%i dc=%i\n",
  688. ace->fsm_state, ace->fsm_task, ace->fsm_iter_num,
  689. ace->data_count);
  690. spin_lock_irqsave(&ace->lock, flags);
  691. /* Rearm the stall timer *before* entering FSM (which may then
  692. * delete the timer) */
  693. mod_timer(&ace->stall_timer, jiffies + HZ);
  694. /* Loop over state machine until told to stop */
  695. ace->fsm_continue_flag = 1;
  696. while (ace->fsm_continue_flag)
  697. ace_fsm_dostate(ace);
  698. spin_unlock_irqrestore(&ace->lock, flags);
  699. }
  700. /* ---------------------------------------------------------------------
  701. * Interrupt handling routines
  702. */
  703. static int ace_interrupt_checkstate(struct ace_device *ace)
  704. {
  705. u32 sreg = ace_in32(ace, ACE_STATUS);
  706. u16 creg = ace_in(ace, ACE_CTRL);
  707. /* Check for error occurrence */
  708. if ((sreg & (ACE_STATUS_CFGERROR | ACE_STATUS_CFCERROR)) &&
  709. (creg & ACE_CTRL_ERRORIRQ)) {
  710. dev_err(ace->dev, "transfer failure\n");
  711. ace_dump_regs(ace);
  712. return -EIO;
  713. }
  714. return 0;
  715. }
  716. static irqreturn_t ace_interrupt(int irq, void *dev_id)
  717. {
  718. u16 creg;
  719. struct ace_device *ace = dev_id;
  720. /* be safe and get the lock */
  721. spin_lock(&ace->lock);
  722. ace->in_irq = 1;
  723. /* clear the interrupt */
  724. creg = ace_in(ace, ACE_CTRL);
  725. ace_out(ace, ACE_CTRL, creg | ACE_CTRL_RESETIRQ);
  726. ace_out(ace, ACE_CTRL, creg);
  727. /* check for IO failures */
  728. if (ace_interrupt_checkstate(ace))
  729. ace->data_result = -EIO;
  730. if (ace->fsm_task == 0) {
  731. dev_err(ace->dev,
  732. "spurious irq; stat=%.8x ctrl=%.8x cmd=%.4x\n",
  733. ace_in32(ace, ACE_STATUS), ace_in32(ace, ACE_CTRL),
  734. ace_in(ace, ACE_SECCNTCMD));
  735. dev_err(ace->dev, "fsm_task=%i fsm_state=%i data_count=%i\n",
  736. ace->fsm_task, ace->fsm_state, ace->data_count);
  737. }
  738. /* Loop over state machine until told to stop */
  739. ace->fsm_continue_flag = 1;
  740. while (ace->fsm_continue_flag)
  741. ace_fsm_dostate(ace);
  742. /* done with interrupt; drop the lock */
  743. ace->in_irq = 0;
  744. spin_unlock(&ace->lock);
  745. return IRQ_HANDLED;
  746. }
  747. /* ---------------------------------------------------------------------
  748. * Block ops
  749. */
  750. static blk_status_t ace_queue_rq(struct blk_mq_hw_ctx *hctx,
  751. const struct blk_mq_queue_data *bd)
  752. {
  753. struct ace_device *ace = hctx->queue->queuedata;
  754. struct request *req = bd->rq;
  755. if (blk_rq_is_passthrough(req)) {
  756. blk_mq_start_request(req);
  757. return BLK_STS_IOERR;
  758. }
  759. spin_lock_irq(&ace->lock);
  760. list_add_tail(&req->queuelist, &ace->rq_list);
  761. spin_unlock_irq(&ace->lock);
  762. tasklet_schedule(&ace->fsm_tasklet);
  763. return BLK_STS_OK;
  764. }
  765. static unsigned int ace_check_events(struct gendisk *gd, unsigned int clearing)
  766. {
  767. struct ace_device *ace = gd->private_data;
  768. dev_dbg(ace->dev, "ace_check_events(): %i\n", ace->media_change);
  769. return ace->media_change ? DISK_EVENT_MEDIA_CHANGE : 0;
  770. }
  771. static void ace_media_changed(struct ace_device *ace)
  772. {
  773. unsigned long flags;
  774. dev_dbg(ace->dev, "requesting cf id and scheduling tasklet\n");
  775. spin_lock_irqsave(&ace->lock, flags);
  776. ace->id_req_count++;
  777. spin_unlock_irqrestore(&ace->lock, flags);
  778. tasklet_schedule(&ace->fsm_tasklet);
  779. wait_for_completion(&ace->id_completion);
  780. dev_dbg(ace->dev, "revalidate complete\n");
  781. }
  782. static int ace_open(struct block_device *bdev, fmode_t mode)
  783. {
  784. struct ace_device *ace = bdev->bd_disk->private_data;
  785. unsigned long flags;
  786. dev_dbg(ace->dev, "ace_open() users=%i\n", ace->users + 1);
  787. mutex_lock(&xsysace_mutex);
  788. spin_lock_irqsave(&ace->lock, flags);
  789. ace->users++;
  790. spin_unlock_irqrestore(&ace->lock, flags);
  791. if (bdev_check_media_change(bdev) && ace->media_change)
  792. ace_media_changed(ace);
  793. mutex_unlock(&xsysace_mutex);
  794. return 0;
  795. }
  796. static void ace_release(struct gendisk *disk, fmode_t mode)
  797. {
  798. struct ace_device *ace = disk->private_data;
  799. unsigned long flags;
  800. u16 val;
  801. dev_dbg(ace->dev, "ace_release() users=%i\n", ace->users - 1);
  802. mutex_lock(&xsysace_mutex);
  803. spin_lock_irqsave(&ace->lock, flags);
  804. ace->users--;
  805. if (ace->users == 0) {
  806. val = ace_in(ace, ACE_CTRL);
  807. ace_out(ace, ACE_CTRL, val & ~ACE_CTRL_LOCKREQ);
  808. }
  809. spin_unlock_irqrestore(&ace->lock, flags);
  810. mutex_unlock(&xsysace_mutex);
  811. }
  812. static int ace_getgeo(struct block_device *bdev, struct hd_geometry *geo)
  813. {
  814. struct ace_device *ace = bdev->bd_disk->private_data;
  815. u16 *cf_id = ace->cf_id;
  816. dev_dbg(ace->dev, "ace_getgeo()\n");
  817. geo->heads = cf_id[ATA_ID_HEADS];
  818. geo->sectors = cf_id[ATA_ID_SECTORS];
  819. geo->cylinders = cf_id[ATA_ID_CYLS];
  820. return 0;
  821. }
  822. static const struct block_device_operations ace_fops = {
  823. .owner = THIS_MODULE,
  824. .open = ace_open,
  825. .release = ace_release,
  826. .check_events = ace_check_events,
  827. .getgeo = ace_getgeo,
  828. };
  829. static const struct blk_mq_ops ace_mq_ops = {
  830. .queue_rq = ace_queue_rq,
  831. };
  832. /* --------------------------------------------------------------------
  833. * SystemACE device setup/teardown code
  834. */
  835. static int ace_setup(struct ace_device *ace)
  836. {
  837. u16 version;
  838. u16 val;
  839. int rc;
  840. dev_dbg(ace->dev, "ace_setup(ace=0x%p)\n", ace);
  841. dev_dbg(ace->dev, "physaddr=0x%llx irq=%i\n",
  842. (unsigned long long)ace->physaddr, ace->irq);
  843. spin_lock_init(&ace->lock);
  844. init_completion(&ace->id_completion);
  845. INIT_LIST_HEAD(&ace->rq_list);
  846. /*
  847. * Map the device
  848. */
  849. ace->baseaddr = ioremap(ace->physaddr, 0x80);
  850. if (!ace->baseaddr)
  851. goto err_ioremap;
  852. /*
  853. * Initialize the state machine tasklet and stall timer
  854. */
  855. tasklet_init(&ace->fsm_tasklet, ace_fsm_tasklet, (unsigned long)ace);
  856. timer_setup(&ace->stall_timer, ace_stall_timer, 0);
  857. /*
  858. * Initialize the request queue
  859. */
  860. ace->queue = blk_mq_init_sq_queue(&ace->tag_set, &ace_mq_ops, 2,
  861. BLK_MQ_F_SHOULD_MERGE);
  862. if (IS_ERR(ace->queue)) {
  863. rc = PTR_ERR(ace->queue);
  864. ace->queue = NULL;
  865. goto err_blk_initq;
  866. }
  867. ace->queue->queuedata = ace;
  868. blk_queue_logical_block_size(ace->queue, 512);
  869. blk_queue_bounce_limit(ace->queue, BLK_BOUNCE_HIGH);
  870. /*
  871. * Allocate and initialize GD structure
  872. */
  873. ace->gd = alloc_disk(ACE_NUM_MINORS);
  874. if (!ace->gd)
  875. goto err_alloc_disk;
  876. ace->gd->major = ace_major;
  877. ace->gd->first_minor = ace->id * ACE_NUM_MINORS;
  878. ace->gd->fops = &ace_fops;
  879. ace->gd->events = DISK_EVENT_MEDIA_CHANGE;
  880. ace->gd->queue = ace->queue;
  881. ace->gd->private_data = ace;
  882. snprintf(ace->gd->disk_name, 32, "xs%c", ace->id + 'a');
  883. /* set bus width */
  884. if (ace->bus_width == ACE_BUS_WIDTH_16) {
  885. /* 0x0101 should work regardless of endianess */
  886. ace_out_le16(ace, ACE_BUSMODE, 0x0101);
  887. /* read it back to determine endianess */
  888. if (ace_in_le16(ace, ACE_BUSMODE) == 0x0001)
  889. ace->reg_ops = &ace_reg_le16_ops;
  890. else
  891. ace->reg_ops = &ace_reg_be16_ops;
  892. } else {
  893. ace_out_8(ace, ACE_BUSMODE, 0x00);
  894. ace->reg_ops = &ace_reg_8_ops;
  895. }
  896. /* Make sure version register is sane */
  897. version = ace_in(ace, ACE_VERSION);
  898. if ((version == 0) || (version == 0xFFFF))
  899. goto err_read;
  900. /* Put sysace in a sane state by clearing most control reg bits */
  901. ace_out(ace, ACE_CTRL, ACE_CTRL_FORCECFGMODE |
  902. ACE_CTRL_DATABUFRDYIRQ | ACE_CTRL_ERRORIRQ);
  903. /* Now we can hook up the irq handler */
  904. if (ace->irq > 0) {
  905. rc = request_irq(ace->irq, ace_interrupt, 0, "systemace", ace);
  906. if (rc) {
  907. /* Failure - fall back to polled mode */
  908. dev_err(ace->dev, "request_irq failed\n");
  909. ace->irq = rc;
  910. }
  911. }
  912. /* Enable interrupts */
  913. val = ace_in(ace, ACE_CTRL);
  914. val |= ACE_CTRL_DATABUFRDYIRQ | ACE_CTRL_ERRORIRQ;
  915. ace_out(ace, ACE_CTRL, val);
  916. /* Print the identification */
  917. dev_info(ace->dev, "Xilinx SystemACE revision %i.%i.%i\n",
  918. (version >> 12) & 0xf, (version >> 8) & 0x0f, version & 0xff);
  919. dev_dbg(ace->dev, "physaddr 0x%llx, mapped to 0x%p, irq=%i\n",
  920. (unsigned long long) ace->physaddr, ace->baseaddr, ace->irq);
  921. ace->media_change = 1;
  922. ace_media_changed(ace);
  923. /* Make the sysace device 'live' */
  924. add_disk(ace->gd);
  925. return 0;
  926. err_read:
  927. /* prevent double queue cleanup */
  928. ace->gd->queue = NULL;
  929. put_disk(ace->gd);
  930. err_alloc_disk:
  931. blk_cleanup_queue(ace->queue);
  932. blk_mq_free_tag_set(&ace->tag_set);
  933. err_blk_initq:
  934. iounmap(ace->baseaddr);
  935. err_ioremap:
  936. dev_info(ace->dev, "xsysace: error initializing device at 0x%llx\n",
  937. (unsigned long long) ace->physaddr);
  938. return -ENOMEM;
  939. }
  940. static void ace_teardown(struct ace_device *ace)
  941. {
  942. if (ace->gd) {
  943. del_gendisk(ace->gd);
  944. put_disk(ace->gd);
  945. }
  946. if (ace->queue) {
  947. blk_cleanup_queue(ace->queue);
  948. blk_mq_free_tag_set(&ace->tag_set);
  949. }
  950. tasklet_kill(&ace->fsm_tasklet);
  951. if (ace->irq > 0)
  952. free_irq(ace->irq, ace);
  953. iounmap(ace->baseaddr);
  954. }
  955. static int ace_alloc(struct device *dev, int id, resource_size_t physaddr,
  956. int irq, int bus_width)
  957. {
  958. struct ace_device *ace;
  959. int rc;
  960. dev_dbg(dev, "ace_alloc(%p)\n", dev);
  961. /* Allocate and initialize the ace device structure */
  962. ace = kzalloc(sizeof(struct ace_device), GFP_KERNEL);
  963. if (!ace) {
  964. rc = -ENOMEM;
  965. goto err_alloc;
  966. }
  967. ace->dev = dev;
  968. ace->id = id;
  969. ace->physaddr = physaddr;
  970. ace->irq = irq;
  971. ace->bus_width = bus_width;
  972. /* Call the setup code */
  973. rc = ace_setup(ace);
  974. if (rc)
  975. goto err_setup;
  976. dev_set_drvdata(dev, ace);
  977. return 0;
  978. err_setup:
  979. dev_set_drvdata(dev, NULL);
  980. kfree(ace);
  981. err_alloc:
  982. dev_err(dev, "could not initialize device, err=%i\n", rc);
  983. return rc;
  984. }
  985. static void ace_free(struct device *dev)
  986. {
  987. struct ace_device *ace = dev_get_drvdata(dev);
  988. dev_dbg(dev, "ace_free(%p)\n", dev);
  989. if (ace) {
  990. ace_teardown(ace);
  991. dev_set_drvdata(dev, NULL);
  992. kfree(ace);
  993. }
  994. }
  995. /* ---------------------------------------------------------------------
  996. * Platform Bus Support
  997. */
  998. static int ace_probe(struct platform_device *dev)
  999. {
  1000. int bus_width = ACE_BUS_WIDTH_16; /* FIXME: should not be hard coded */
  1001. resource_size_t physaddr;
  1002. struct resource *res;
  1003. u32 id = dev->id;
  1004. int irq;
  1005. int i;
  1006. dev_dbg(&dev->dev, "ace_probe(%p)\n", dev);
  1007. /* device id and bus width */
  1008. if (of_property_read_u32(dev->dev.of_node, "port-number", &id))
  1009. id = 0;
  1010. if (of_find_property(dev->dev.of_node, "8-bit", NULL))
  1011. bus_width = ACE_BUS_WIDTH_8;
  1012. res = platform_get_resource(dev, IORESOURCE_MEM, 0);
  1013. if (!res)
  1014. return -EINVAL;
  1015. physaddr = res->start;
  1016. if (!physaddr)
  1017. return -ENODEV;
  1018. irq = platform_get_irq_optional(dev, 0);
  1019. /* Call the bus-independent setup code */
  1020. return ace_alloc(&dev->dev, id, physaddr, irq, bus_width);
  1021. }
  1022. /*
  1023. * Platform bus remove() method
  1024. */
  1025. static int ace_remove(struct platform_device *dev)
  1026. {
  1027. ace_free(&dev->dev);
  1028. return 0;
  1029. }
  1030. #if defined(CONFIG_OF)
  1031. /* Match table for of_platform binding */
  1032. static const struct of_device_id ace_of_match[] = {
  1033. { .compatible = "xlnx,opb-sysace-1.00.b", },
  1034. { .compatible = "xlnx,opb-sysace-1.00.c", },
  1035. { .compatible = "xlnx,xps-sysace-1.00.a", },
  1036. { .compatible = "xlnx,sysace", },
  1037. {},
  1038. };
  1039. MODULE_DEVICE_TABLE(of, ace_of_match);
  1040. #else /* CONFIG_OF */
  1041. #define ace_of_match NULL
  1042. #endif /* CONFIG_OF */
  1043. static struct platform_driver ace_platform_driver = {
  1044. .probe = ace_probe,
  1045. .remove = ace_remove,
  1046. .driver = {
  1047. .name = "xsysace",
  1048. .of_match_table = ace_of_match,
  1049. },
  1050. };
  1051. /* ---------------------------------------------------------------------
  1052. * Module init/exit routines
  1053. */
  1054. static int __init ace_init(void)
  1055. {
  1056. int rc;
  1057. ace_major = register_blkdev(ace_major, "xsysace");
  1058. if (ace_major <= 0) {
  1059. rc = -ENOMEM;
  1060. goto err_blk;
  1061. }
  1062. rc = platform_driver_register(&ace_platform_driver);
  1063. if (rc)
  1064. goto err_plat;
  1065. pr_info("Xilinx SystemACE device driver, major=%i\n", ace_major);
  1066. return 0;
  1067. err_plat:
  1068. unregister_blkdev(ace_major, "xsysace");
  1069. err_blk:
  1070. printk(KERN_ERR "xsysace: registration failed; err=%i\n", rc);
  1071. return rc;
  1072. }
  1073. module_init(ace_init);
  1074. static void __exit ace_exit(void)
  1075. {
  1076. pr_debug("Unregistering Xilinx SystemACE driver\n");
  1077. platform_driver_unregister(&ace_platform_driver);
  1078. unregister_blkdev(ace_major, "xsysace");
  1079. }
  1080. module_exit(ace_exit);