driver_pci.c 8.2 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306
  1. /*
  2. * Broadcom specific AMBA
  3. * PCI Core
  4. *
  5. * Copyright 2005, 2011, Broadcom Corporation
  6. * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
  7. * Copyright 2011, 2012, Hauke Mehrtens <hauke@hauke-m.de>
  8. *
  9. * Licensed under the GNU/GPL. See COPYING for details.
  10. */
  11. #include "bcma_private.h"
  12. #include <linux/export.h>
  13. #include <linux/bcma/bcma.h>
  14. /**************************************************
  15. * R/W ops.
  16. **************************************************/
  17. u32 bcma_pcie_read(struct bcma_drv_pci *pc, u32 address)
  18. {
  19. pcicore_write32(pc, BCMA_CORE_PCI_PCIEIND_ADDR, address);
  20. pcicore_read32(pc, BCMA_CORE_PCI_PCIEIND_ADDR);
  21. return pcicore_read32(pc, BCMA_CORE_PCI_PCIEIND_DATA);
  22. }
  23. static void bcma_pcie_write(struct bcma_drv_pci *pc, u32 address, u32 data)
  24. {
  25. pcicore_write32(pc, BCMA_CORE_PCI_PCIEIND_ADDR, address);
  26. pcicore_read32(pc, BCMA_CORE_PCI_PCIEIND_ADDR);
  27. pcicore_write32(pc, BCMA_CORE_PCI_PCIEIND_DATA, data);
  28. }
  29. static void bcma_pcie_mdio_set_phy(struct bcma_drv_pci *pc, u16 phy)
  30. {
  31. u32 v;
  32. int i;
  33. v = BCMA_CORE_PCI_MDIODATA_START;
  34. v |= BCMA_CORE_PCI_MDIODATA_WRITE;
  35. v |= (BCMA_CORE_PCI_MDIODATA_DEV_ADDR <<
  36. BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF);
  37. v |= (BCMA_CORE_PCI_MDIODATA_BLK_ADDR <<
  38. BCMA_CORE_PCI_MDIODATA_REGADDR_SHF);
  39. v |= BCMA_CORE_PCI_MDIODATA_TA;
  40. v |= (phy << 4);
  41. pcicore_write32(pc, BCMA_CORE_PCI_MDIO_DATA, v);
  42. udelay(10);
  43. for (i = 0; i < 200; i++) {
  44. v = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_CONTROL);
  45. if (v & BCMA_CORE_PCI_MDIOCTL_ACCESS_DONE)
  46. break;
  47. usleep_range(1000, 2000);
  48. }
  49. }
  50. static u16 bcma_pcie_mdio_read(struct bcma_drv_pci *pc, u16 device, u8 address)
  51. {
  52. int max_retries = 10;
  53. u16 ret = 0;
  54. u32 v;
  55. int i;
  56. /* enable mdio access to SERDES */
  57. v = BCMA_CORE_PCI_MDIOCTL_PREAM_EN;
  58. v |= BCMA_CORE_PCI_MDIOCTL_DIVISOR_VAL;
  59. pcicore_write32(pc, BCMA_CORE_PCI_MDIO_CONTROL, v);
  60. if (pc->core->id.rev >= 10) {
  61. max_retries = 200;
  62. bcma_pcie_mdio_set_phy(pc, device);
  63. v = (BCMA_CORE_PCI_MDIODATA_DEV_ADDR <<
  64. BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF);
  65. v |= (address << BCMA_CORE_PCI_MDIODATA_REGADDR_SHF);
  66. } else {
  67. v = (device << BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF_OLD);
  68. v |= (address << BCMA_CORE_PCI_MDIODATA_REGADDR_SHF_OLD);
  69. }
  70. v |= BCMA_CORE_PCI_MDIODATA_START;
  71. v |= BCMA_CORE_PCI_MDIODATA_READ;
  72. v |= BCMA_CORE_PCI_MDIODATA_TA;
  73. pcicore_write32(pc, BCMA_CORE_PCI_MDIO_DATA, v);
  74. /* Wait for the device to complete the transaction */
  75. udelay(10);
  76. for (i = 0; i < max_retries; i++) {
  77. v = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_CONTROL);
  78. if (v & BCMA_CORE_PCI_MDIOCTL_ACCESS_DONE) {
  79. udelay(10);
  80. ret = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_DATA);
  81. break;
  82. }
  83. usleep_range(1000, 2000);
  84. }
  85. pcicore_write32(pc, BCMA_CORE_PCI_MDIO_CONTROL, 0);
  86. return ret;
  87. }
  88. static void bcma_pcie_mdio_write(struct bcma_drv_pci *pc, u16 device,
  89. u8 address, u16 data)
  90. {
  91. int max_retries = 10;
  92. u32 v;
  93. int i;
  94. /* enable mdio access to SERDES */
  95. v = BCMA_CORE_PCI_MDIOCTL_PREAM_EN;
  96. v |= BCMA_CORE_PCI_MDIOCTL_DIVISOR_VAL;
  97. pcicore_write32(pc, BCMA_CORE_PCI_MDIO_CONTROL, v);
  98. if (pc->core->id.rev >= 10) {
  99. max_retries = 200;
  100. bcma_pcie_mdio_set_phy(pc, device);
  101. v = (BCMA_CORE_PCI_MDIODATA_DEV_ADDR <<
  102. BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF);
  103. v |= (address << BCMA_CORE_PCI_MDIODATA_REGADDR_SHF);
  104. } else {
  105. v = (device << BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF_OLD);
  106. v |= (address << BCMA_CORE_PCI_MDIODATA_REGADDR_SHF_OLD);
  107. }
  108. v |= BCMA_CORE_PCI_MDIODATA_START;
  109. v |= BCMA_CORE_PCI_MDIODATA_WRITE;
  110. v |= BCMA_CORE_PCI_MDIODATA_TA;
  111. v |= data;
  112. pcicore_write32(pc, BCMA_CORE_PCI_MDIO_DATA, v);
  113. /* Wait for the device to complete the transaction */
  114. udelay(10);
  115. for (i = 0; i < max_retries; i++) {
  116. v = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_CONTROL);
  117. if (v & BCMA_CORE_PCI_MDIOCTL_ACCESS_DONE)
  118. break;
  119. usleep_range(1000, 2000);
  120. }
  121. pcicore_write32(pc, BCMA_CORE_PCI_MDIO_CONTROL, 0);
  122. }
  123. static u16 bcma_pcie_mdio_writeread(struct bcma_drv_pci *pc, u16 device,
  124. u8 address, u16 data)
  125. {
  126. bcma_pcie_mdio_write(pc, device, address, data);
  127. return bcma_pcie_mdio_read(pc, device, address);
  128. }
  129. /**************************************************
  130. * Early init.
  131. **************************************************/
  132. static void bcma_core_pci_fixcfg(struct bcma_drv_pci *pc)
  133. {
  134. struct bcma_device *core = pc->core;
  135. u16 val16, core_index;
  136. uint regoff;
  137. regoff = BCMA_CORE_PCI_SPROM(BCMA_CORE_PCI_SPROM_PI_OFFSET);
  138. core_index = (u16)core->core_index;
  139. val16 = pcicore_read16(pc, regoff);
  140. if (((val16 & BCMA_CORE_PCI_SPROM_PI_MASK) >> BCMA_CORE_PCI_SPROM_PI_SHIFT)
  141. != core_index) {
  142. val16 = (core_index << BCMA_CORE_PCI_SPROM_PI_SHIFT) |
  143. (val16 & ~BCMA_CORE_PCI_SPROM_PI_MASK);
  144. pcicore_write16(pc, regoff, val16);
  145. }
  146. }
  147. /*
  148. * Apply some early fixes required before accessing SPROM.
  149. * See also si_pci_fixcfg.
  150. */
  151. void bcma_core_pci_early_init(struct bcma_drv_pci *pc)
  152. {
  153. if (pc->early_setup_done)
  154. return;
  155. pc->hostmode = bcma_core_pci_is_in_hostmode(pc);
  156. if (pc->hostmode)
  157. goto out;
  158. bcma_core_pci_fixcfg(pc);
  159. out:
  160. pc->early_setup_done = true;
  161. }
  162. /**************************************************
  163. * Workarounds.
  164. **************************************************/
  165. static u8 bcma_pcicore_polarity_workaround(struct bcma_drv_pci *pc)
  166. {
  167. u32 tmp;
  168. tmp = bcma_pcie_read(pc, BCMA_CORE_PCI_PLP_STATUSREG);
  169. if (tmp & BCMA_CORE_PCI_PLP_POLARITYINV_STAT)
  170. return BCMA_CORE_PCI_SERDES_RX_CTRL_FORCE |
  171. BCMA_CORE_PCI_SERDES_RX_CTRL_POLARITY;
  172. else
  173. return BCMA_CORE_PCI_SERDES_RX_CTRL_FORCE;
  174. }
  175. static void bcma_pcicore_serdes_workaround(struct bcma_drv_pci *pc)
  176. {
  177. u16 tmp;
  178. bcma_pcie_mdio_write(pc, BCMA_CORE_PCI_MDIODATA_DEV_RX,
  179. BCMA_CORE_PCI_SERDES_RX_CTRL,
  180. bcma_pcicore_polarity_workaround(pc));
  181. tmp = bcma_pcie_mdio_read(pc, BCMA_CORE_PCI_MDIODATA_DEV_PLL,
  182. BCMA_CORE_PCI_SERDES_PLL_CTRL);
  183. if (tmp & BCMA_CORE_PCI_PLL_CTRL_FREQDET_EN)
  184. bcma_pcie_mdio_write(pc, BCMA_CORE_PCI_MDIODATA_DEV_PLL,
  185. BCMA_CORE_PCI_SERDES_PLL_CTRL,
  186. tmp & ~BCMA_CORE_PCI_PLL_CTRL_FREQDET_EN);
  187. }
  188. /* Fix MISC config to allow coming out of L2/L3-Ready state w/o PRST */
  189. /* Needs to happen when coming out of 'standby'/'hibernate' */
  190. static void bcma_core_pci_config_fixup(struct bcma_drv_pci *pc)
  191. {
  192. u16 val16;
  193. uint regoff;
  194. regoff = BCMA_CORE_PCI_SPROM(BCMA_CORE_PCI_SPROM_MISC_CONFIG);
  195. val16 = pcicore_read16(pc, regoff);
  196. if (!(val16 & BCMA_CORE_PCI_SPROM_L23READY_EXIT_NOPERST)) {
  197. val16 |= BCMA_CORE_PCI_SPROM_L23READY_EXIT_NOPERST;
  198. pcicore_write16(pc, regoff, val16);
  199. }
  200. }
  201. /**************************************************
  202. * Init.
  203. **************************************************/
  204. static void bcma_core_pci_clientmode_init(struct bcma_drv_pci *pc)
  205. {
  206. bcma_pcicore_serdes_workaround(pc);
  207. bcma_core_pci_config_fixup(pc);
  208. }
  209. void bcma_core_pci_init(struct bcma_drv_pci *pc)
  210. {
  211. if (pc->setup_done)
  212. return;
  213. bcma_core_pci_early_init(pc);
  214. if (pc->hostmode)
  215. bcma_core_pci_hostmode_init(pc);
  216. else
  217. bcma_core_pci_clientmode_init(pc);
  218. }
  219. void bcma_core_pci_power_save(struct bcma_bus *bus, bool up)
  220. {
  221. struct bcma_drv_pci *pc;
  222. u16 data;
  223. if (bus->hosttype != BCMA_HOSTTYPE_PCI)
  224. return;
  225. pc = &bus->drv_pci[0];
  226. if (pc->core->id.rev >= 15 && pc->core->id.rev <= 20) {
  227. data = up ? 0x74 : 0x7C;
  228. bcma_pcie_mdio_writeread(pc, BCMA_CORE_PCI_MDIO_BLK1,
  229. BCMA_CORE_PCI_MDIO_BLK1_MGMT1, 0x7F64);
  230. bcma_pcie_mdio_writeread(pc, BCMA_CORE_PCI_MDIO_BLK1,
  231. BCMA_CORE_PCI_MDIO_BLK1_MGMT3, data);
  232. } else if (pc->core->id.rev >= 21 && pc->core->id.rev <= 22) {
  233. data = up ? 0x75 : 0x7D;
  234. bcma_pcie_mdio_writeread(pc, BCMA_CORE_PCI_MDIO_BLK1,
  235. BCMA_CORE_PCI_MDIO_BLK1_MGMT1, 0x7E65);
  236. bcma_pcie_mdio_writeread(pc, BCMA_CORE_PCI_MDIO_BLK1,
  237. BCMA_CORE_PCI_MDIO_BLK1_MGMT3, data);
  238. }
  239. }
  240. EXPORT_SYMBOL_GPL(bcma_core_pci_power_save);
  241. static void bcma_core_pci_extend_L1timer(struct bcma_drv_pci *pc, bool extend)
  242. {
  243. u32 w;
  244. w = bcma_pcie_read(pc, BCMA_CORE_PCI_DLLP_PMTHRESHREG);
  245. if (extend)
  246. w |= BCMA_CORE_PCI_ASPMTIMER_EXTEND;
  247. else
  248. w &= ~BCMA_CORE_PCI_ASPMTIMER_EXTEND;
  249. bcma_pcie_write(pc, BCMA_CORE_PCI_DLLP_PMTHRESHREG, w);
  250. bcma_pcie_read(pc, BCMA_CORE_PCI_DLLP_PMTHRESHREG);
  251. }
  252. void bcma_core_pci_up(struct bcma_drv_pci *pc)
  253. {
  254. bcma_core_pci_extend_L1timer(pc, true);
  255. }
  256. void bcma_core_pci_down(struct bcma_drv_pci *pc)
  257. {
  258. bcma_core_pci_extend_L1timer(pc, false);
  259. }