nicstar.c 73 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * nicstar.c
  4. *
  5. * Device driver supporting CBR for IDT 77201/77211 "NICStAR" based cards.
  6. *
  7. * IMPORTANT: The included file nicstarmac.c was NOT WRITTEN BY ME.
  8. * It was taken from the frle-0.22 device driver.
  9. * As the file doesn't have a copyright notice, in the file
  10. * nicstarmac.copyright I put the copyright notice from the
  11. * frle-0.22 device driver.
  12. * Some code is based on the nicstar driver by M. Welsh.
  13. *
  14. * Author: Rui Prior (rprior@inescn.pt)
  15. * PowerPC support by Jay Talbott (jay_talbott@mcg.mot.com) April 1999
  16. *
  17. *
  18. * (C) INESC 1999
  19. */
  20. /*
  21. * IMPORTANT INFORMATION
  22. *
  23. * There are currently three types of spinlocks:
  24. *
  25. * 1 - Per card interrupt spinlock (to protect structures and such)
  26. * 2 - Per SCQ scq spinlock
  27. * 3 - Per card resource spinlock (to access registers, etc.)
  28. *
  29. * These must NEVER be grabbed in reverse order.
  30. *
  31. */
  32. /* Header files */
  33. #include <linux/module.h>
  34. #include <linux/kernel.h>
  35. #include <linux/skbuff.h>
  36. #include <linux/atmdev.h>
  37. #include <linux/atm.h>
  38. #include <linux/pci.h>
  39. #include <linux/dma-mapping.h>
  40. #include <linux/types.h>
  41. #include <linux/string.h>
  42. #include <linux/delay.h>
  43. #include <linux/init.h>
  44. #include <linux/sched.h>
  45. #include <linux/timer.h>
  46. #include <linux/interrupt.h>
  47. #include <linux/bitops.h>
  48. #include <linux/slab.h>
  49. #include <linux/idr.h>
  50. #include <asm/io.h>
  51. #include <linux/uaccess.h>
  52. #include <linux/atomic.h>
  53. #include <linux/etherdevice.h>
  54. #include "nicstar.h"
  55. #ifdef CONFIG_ATM_NICSTAR_USE_SUNI
  56. #include "suni.h"
  57. #endif /* CONFIG_ATM_NICSTAR_USE_SUNI */
  58. #ifdef CONFIG_ATM_NICSTAR_USE_IDT77105
  59. #include "idt77105.h"
  60. #endif /* CONFIG_ATM_NICSTAR_USE_IDT77105 */
  61. /* Additional code */
  62. #include "nicstarmac.c"
  63. /* Configurable parameters */
  64. #undef PHY_LOOPBACK
  65. #undef TX_DEBUG
  66. #undef RX_DEBUG
  67. #undef GENERAL_DEBUG
  68. #undef EXTRA_DEBUG
  69. /* Do not touch these */
  70. #ifdef TX_DEBUG
  71. #define TXPRINTK(args...) printk(args)
  72. #else
  73. #define TXPRINTK(args...)
  74. #endif /* TX_DEBUG */
  75. #ifdef RX_DEBUG
  76. #define RXPRINTK(args...) printk(args)
  77. #else
  78. #define RXPRINTK(args...)
  79. #endif /* RX_DEBUG */
  80. #ifdef GENERAL_DEBUG
  81. #define PRINTK(args...) printk(args)
  82. #else
  83. #define PRINTK(args...) do {} while (0)
  84. #endif /* GENERAL_DEBUG */
  85. #ifdef EXTRA_DEBUG
  86. #define XPRINTK(args...) printk(args)
  87. #else
  88. #define XPRINTK(args...)
  89. #endif /* EXTRA_DEBUG */
  90. /* Macros */
  91. #define CMD_BUSY(card) (readl((card)->membase + STAT) & NS_STAT_CMDBZ)
  92. #define NS_DELAY mdelay(1)
  93. #define PTR_DIFF(a, b) ((u32)((unsigned long)(a) - (unsigned long)(b)))
  94. #ifndef ATM_SKB
  95. #define ATM_SKB(s) (&(s)->atm)
  96. #endif
  97. #define scq_virt_to_bus(scq, p) \
  98. (scq->dma + ((unsigned long)(p) - (unsigned long)(scq)->org))
  99. /* Function declarations */
  100. static u32 ns_read_sram(ns_dev * card, u32 sram_address);
  101. static void ns_write_sram(ns_dev * card, u32 sram_address, u32 * value,
  102. int count);
  103. static int ns_init_card(int i, struct pci_dev *pcidev);
  104. static void ns_init_card_error(ns_dev * card, int error);
  105. static scq_info *get_scq(ns_dev *card, int size, u32 scd);
  106. static void free_scq(ns_dev *card, scq_info * scq, struct atm_vcc *vcc);
  107. static void push_rxbufs(ns_dev *, struct sk_buff *);
  108. static irqreturn_t ns_irq_handler(int irq, void *dev_id);
  109. static int ns_open(struct atm_vcc *vcc);
  110. static void ns_close(struct atm_vcc *vcc);
  111. static void fill_tst(ns_dev * card, int n, vc_map * vc);
  112. static int ns_send(struct atm_vcc *vcc, struct sk_buff *skb);
  113. static int push_scqe(ns_dev * card, vc_map * vc, scq_info * scq, ns_scqe * tbd,
  114. struct sk_buff *skb);
  115. static void process_tsq(ns_dev * card);
  116. static void drain_scq(ns_dev * card, scq_info * scq, int pos);
  117. static void process_rsq(ns_dev * card);
  118. static void dequeue_rx(ns_dev * card, ns_rsqe * rsqe);
  119. static void recycle_rx_buf(ns_dev * card, struct sk_buff *skb);
  120. static void recycle_iovec_rx_bufs(ns_dev * card, struct iovec *iov, int count);
  121. static void recycle_iov_buf(ns_dev * card, struct sk_buff *iovb);
  122. static void dequeue_sm_buf(ns_dev * card, struct sk_buff *sb);
  123. static void dequeue_lg_buf(ns_dev * card, struct sk_buff *lb);
  124. static int ns_proc_read(struct atm_dev *dev, loff_t * pos, char *page);
  125. static int ns_ioctl(struct atm_dev *dev, unsigned int cmd, void __user * arg);
  126. #ifdef EXTRA_DEBUG
  127. static void which_list(ns_dev * card, struct sk_buff *skb);
  128. #endif
  129. static void ns_poll(struct timer_list *unused);
  130. static void ns_phy_put(struct atm_dev *dev, unsigned char value,
  131. unsigned long addr);
  132. static unsigned char ns_phy_get(struct atm_dev *dev, unsigned long addr);
  133. /* Global variables */
  134. static struct ns_dev *cards[NS_MAX_CARDS];
  135. static unsigned num_cards;
  136. static const struct atmdev_ops atm_ops = {
  137. .open = ns_open,
  138. .close = ns_close,
  139. .ioctl = ns_ioctl,
  140. .send = ns_send,
  141. .phy_put = ns_phy_put,
  142. .phy_get = ns_phy_get,
  143. .proc_read = ns_proc_read,
  144. .owner = THIS_MODULE,
  145. };
  146. static struct timer_list ns_timer;
  147. static char *mac[NS_MAX_CARDS];
  148. module_param_array(mac, charp, NULL, 0);
  149. MODULE_LICENSE("GPL");
  150. /* Functions */
  151. static int nicstar_init_one(struct pci_dev *pcidev,
  152. const struct pci_device_id *ent)
  153. {
  154. static int index = -1;
  155. unsigned int error;
  156. index++;
  157. cards[index] = NULL;
  158. error = ns_init_card(index, pcidev);
  159. if (error) {
  160. cards[index--] = NULL; /* don't increment index */
  161. goto err_out;
  162. }
  163. return 0;
  164. err_out:
  165. return -ENODEV;
  166. }
  167. static void nicstar_remove_one(struct pci_dev *pcidev)
  168. {
  169. int i, j;
  170. ns_dev *card = pci_get_drvdata(pcidev);
  171. struct sk_buff *hb;
  172. struct sk_buff *iovb;
  173. struct sk_buff *lb;
  174. struct sk_buff *sb;
  175. i = card->index;
  176. if (cards[i] == NULL)
  177. return;
  178. if (card->atmdev->phy && card->atmdev->phy->stop)
  179. card->atmdev->phy->stop(card->atmdev);
  180. /* Stop everything */
  181. writel(0x00000000, card->membase + CFG);
  182. /* De-register device */
  183. atm_dev_deregister(card->atmdev);
  184. /* Disable PCI device */
  185. pci_disable_device(pcidev);
  186. /* Free up resources */
  187. j = 0;
  188. PRINTK("nicstar%d: freeing %d huge buffers.\n", i, card->hbpool.count);
  189. while ((hb = skb_dequeue(&card->hbpool.queue)) != NULL) {
  190. dev_kfree_skb_any(hb);
  191. j++;
  192. }
  193. PRINTK("nicstar%d: %d huge buffers freed.\n", i, j);
  194. j = 0;
  195. PRINTK("nicstar%d: freeing %d iovec buffers.\n", i,
  196. card->iovpool.count);
  197. while ((iovb = skb_dequeue(&card->iovpool.queue)) != NULL) {
  198. dev_kfree_skb_any(iovb);
  199. j++;
  200. }
  201. PRINTK("nicstar%d: %d iovec buffers freed.\n", i, j);
  202. while ((lb = skb_dequeue(&card->lbpool.queue)) != NULL)
  203. dev_kfree_skb_any(lb);
  204. while ((sb = skb_dequeue(&card->sbpool.queue)) != NULL)
  205. dev_kfree_skb_any(sb);
  206. free_scq(card, card->scq0, NULL);
  207. for (j = 0; j < NS_FRSCD_NUM; j++) {
  208. if (card->scd2vc[j] != NULL)
  209. free_scq(card, card->scd2vc[j]->scq, card->scd2vc[j]->tx_vcc);
  210. }
  211. idr_destroy(&card->idr);
  212. dma_free_coherent(&card->pcidev->dev, NS_RSQSIZE + NS_RSQ_ALIGNMENT,
  213. card->rsq.org, card->rsq.dma);
  214. dma_free_coherent(&card->pcidev->dev, NS_TSQSIZE + NS_TSQ_ALIGNMENT,
  215. card->tsq.org, card->tsq.dma);
  216. free_irq(card->pcidev->irq, card);
  217. iounmap(card->membase);
  218. kfree(card);
  219. }
  220. static const struct pci_device_id nicstar_pci_tbl[] = {
  221. { PCI_VDEVICE(IDT, PCI_DEVICE_ID_IDT_IDT77201), 0 },
  222. {0,} /* terminate list */
  223. };
  224. MODULE_DEVICE_TABLE(pci, nicstar_pci_tbl);
  225. static struct pci_driver nicstar_driver = {
  226. .name = "nicstar",
  227. .id_table = nicstar_pci_tbl,
  228. .probe = nicstar_init_one,
  229. .remove = nicstar_remove_one,
  230. };
  231. static int __init nicstar_init(void)
  232. {
  233. unsigned error = 0; /* Initialized to remove compile warning */
  234. XPRINTK("nicstar: nicstar_init() called.\n");
  235. error = pci_register_driver(&nicstar_driver);
  236. TXPRINTK("nicstar: TX debug enabled.\n");
  237. RXPRINTK("nicstar: RX debug enabled.\n");
  238. PRINTK("nicstar: General debug enabled.\n");
  239. #ifdef PHY_LOOPBACK
  240. printk("nicstar: using PHY loopback.\n");
  241. #endif /* PHY_LOOPBACK */
  242. XPRINTK("nicstar: nicstar_init() returned.\n");
  243. if (!error) {
  244. timer_setup(&ns_timer, ns_poll, 0);
  245. ns_timer.expires = jiffies + NS_POLL_PERIOD;
  246. add_timer(&ns_timer);
  247. }
  248. return error;
  249. }
  250. static void __exit nicstar_cleanup(void)
  251. {
  252. XPRINTK("nicstar: nicstar_cleanup() called.\n");
  253. del_timer_sync(&ns_timer);
  254. pci_unregister_driver(&nicstar_driver);
  255. XPRINTK("nicstar: nicstar_cleanup() returned.\n");
  256. }
  257. static u32 ns_read_sram(ns_dev * card, u32 sram_address)
  258. {
  259. unsigned long flags;
  260. u32 data;
  261. sram_address <<= 2;
  262. sram_address &= 0x0007FFFC; /* address must be dword aligned */
  263. sram_address |= 0x50000000; /* SRAM read command */
  264. spin_lock_irqsave(&card->res_lock, flags);
  265. while (CMD_BUSY(card)) ;
  266. writel(sram_address, card->membase + CMD);
  267. while (CMD_BUSY(card)) ;
  268. data = readl(card->membase + DR0);
  269. spin_unlock_irqrestore(&card->res_lock, flags);
  270. return data;
  271. }
  272. static void ns_write_sram(ns_dev * card, u32 sram_address, u32 * value,
  273. int count)
  274. {
  275. unsigned long flags;
  276. int i, c;
  277. count--; /* count range now is 0..3 instead of 1..4 */
  278. c = count;
  279. c <<= 2; /* to use increments of 4 */
  280. spin_lock_irqsave(&card->res_lock, flags);
  281. while (CMD_BUSY(card)) ;
  282. for (i = 0; i <= c; i += 4)
  283. writel(*(value++), card->membase + i);
  284. /* Note: DR# registers are the first 4 dwords in nicstar's memspace,
  285. so card->membase + DR0 == card->membase */
  286. sram_address <<= 2;
  287. sram_address &= 0x0007FFFC;
  288. sram_address |= (0x40000000 | count);
  289. writel(sram_address, card->membase + CMD);
  290. spin_unlock_irqrestore(&card->res_lock, flags);
  291. }
  292. static int ns_init_card(int i, struct pci_dev *pcidev)
  293. {
  294. int j;
  295. struct ns_dev *card = NULL;
  296. unsigned char pci_latency;
  297. unsigned error;
  298. u32 data;
  299. u32 u32d[4];
  300. u32 ns_cfg_rctsize;
  301. int bcount;
  302. unsigned long membase;
  303. error = 0;
  304. if (pci_enable_device(pcidev)) {
  305. printk("nicstar%d: can't enable PCI device\n", i);
  306. error = 2;
  307. ns_init_card_error(card, error);
  308. return error;
  309. }
  310. if (dma_set_mask_and_coherent(&pcidev->dev, DMA_BIT_MASK(32)) != 0) {
  311. printk(KERN_WARNING
  312. "nicstar%d: No suitable DMA available.\n", i);
  313. error = 2;
  314. ns_init_card_error(card, error);
  315. return error;
  316. }
  317. card = kmalloc(sizeof(*card), GFP_KERNEL);
  318. if (!card) {
  319. printk
  320. ("nicstar%d: can't allocate memory for device structure.\n",
  321. i);
  322. error = 2;
  323. ns_init_card_error(card, error);
  324. return error;
  325. }
  326. cards[i] = card;
  327. spin_lock_init(&card->int_lock);
  328. spin_lock_init(&card->res_lock);
  329. pci_set_drvdata(pcidev, card);
  330. card->index = i;
  331. card->atmdev = NULL;
  332. card->pcidev = pcidev;
  333. membase = pci_resource_start(pcidev, 1);
  334. card->membase = ioremap(membase, NS_IOREMAP_SIZE);
  335. if (!card->membase) {
  336. printk("nicstar%d: can't ioremap() membase.\n", i);
  337. error = 3;
  338. ns_init_card_error(card, error);
  339. return error;
  340. }
  341. PRINTK("nicstar%d: membase at 0x%p.\n", i, card->membase);
  342. pci_set_master(pcidev);
  343. if (pci_read_config_byte(pcidev, PCI_LATENCY_TIMER, &pci_latency) != 0) {
  344. printk("nicstar%d: can't read PCI latency timer.\n", i);
  345. error = 6;
  346. ns_init_card_error(card, error);
  347. return error;
  348. }
  349. #ifdef NS_PCI_LATENCY
  350. if (pci_latency < NS_PCI_LATENCY) {
  351. PRINTK("nicstar%d: setting PCI latency timer to %d.\n", i,
  352. NS_PCI_LATENCY);
  353. for (j = 1; j < 4; j++) {
  354. if (pci_write_config_byte
  355. (pcidev, PCI_LATENCY_TIMER, NS_PCI_LATENCY) != 0)
  356. break;
  357. }
  358. if (j == 4) {
  359. printk
  360. ("nicstar%d: can't set PCI latency timer to %d.\n",
  361. i, NS_PCI_LATENCY);
  362. error = 7;
  363. ns_init_card_error(card, error);
  364. return error;
  365. }
  366. }
  367. #endif /* NS_PCI_LATENCY */
  368. /* Clear timer overflow */
  369. data = readl(card->membase + STAT);
  370. if (data & NS_STAT_TMROF)
  371. writel(NS_STAT_TMROF, card->membase + STAT);
  372. /* Software reset */
  373. writel(NS_CFG_SWRST, card->membase + CFG);
  374. NS_DELAY;
  375. writel(0x00000000, card->membase + CFG);
  376. /* PHY reset */
  377. writel(0x00000008, card->membase + GP);
  378. NS_DELAY;
  379. writel(0x00000001, card->membase + GP);
  380. NS_DELAY;
  381. while (CMD_BUSY(card)) ;
  382. writel(NS_CMD_WRITE_UTILITY | 0x00000100, card->membase + CMD); /* Sync UTOPIA with SAR clock */
  383. NS_DELAY;
  384. /* Detect PHY type */
  385. while (CMD_BUSY(card)) ;
  386. writel(NS_CMD_READ_UTILITY | 0x00000200, card->membase + CMD);
  387. while (CMD_BUSY(card)) ;
  388. data = readl(card->membase + DR0);
  389. switch (data) {
  390. case 0x00000009:
  391. printk("nicstar%d: PHY seems to be 25 Mbps.\n", i);
  392. card->max_pcr = ATM_25_PCR;
  393. while (CMD_BUSY(card)) ;
  394. writel(0x00000008, card->membase + DR0);
  395. writel(NS_CMD_WRITE_UTILITY | 0x00000200, card->membase + CMD);
  396. /* Clear an eventual pending interrupt */
  397. writel(NS_STAT_SFBQF, card->membase + STAT);
  398. #ifdef PHY_LOOPBACK
  399. while (CMD_BUSY(card)) ;
  400. writel(0x00000022, card->membase + DR0);
  401. writel(NS_CMD_WRITE_UTILITY | 0x00000202, card->membase + CMD);
  402. #endif /* PHY_LOOPBACK */
  403. break;
  404. case 0x00000030:
  405. case 0x00000031:
  406. printk("nicstar%d: PHY seems to be 155 Mbps.\n", i);
  407. card->max_pcr = ATM_OC3_PCR;
  408. #ifdef PHY_LOOPBACK
  409. while (CMD_BUSY(card)) ;
  410. writel(0x00000002, card->membase + DR0);
  411. writel(NS_CMD_WRITE_UTILITY | 0x00000205, card->membase + CMD);
  412. #endif /* PHY_LOOPBACK */
  413. break;
  414. default:
  415. printk("nicstar%d: unknown PHY type (0x%08X).\n", i, data);
  416. error = 8;
  417. ns_init_card_error(card, error);
  418. return error;
  419. }
  420. writel(0x00000000, card->membase + GP);
  421. /* Determine SRAM size */
  422. data = 0x76543210;
  423. ns_write_sram(card, 0x1C003, &data, 1);
  424. data = 0x89ABCDEF;
  425. ns_write_sram(card, 0x14003, &data, 1);
  426. if (ns_read_sram(card, 0x14003) == 0x89ABCDEF &&
  427. ns_read_sram(card, 0x1C003) == 0x76543210)
  428. card->sram_size = 128;
  429. else
  430. card->sram_size = 32;
  431. PRINTK("nicstar%d: %dK x 32bit SRAM size.\n", i, card->sram_size);
  432. card->rct_size = NS_MAX_RCTSIZE;
  433. #if (NS_MAX_RCTSIZE == 4096)
  434. if (card->sram_size == 128)
  435. printk
  436. ("nicstar%d: limiting maximum VCI. See NS_MAX_RCTSIZE in nicstar.h\n",
  437. i);
  438. #elif (NS_MAX_RCTSIZE == 16384)
  439. if (card->sram_size == 32) {
  440. printk
  441. ("nicstar%d: wasting memory. See NS_MAX_RCTSIZE in nicstar.h\n",
  442. i);
  443. card->rct_size = 4096;
  444. }
  445. #else
  446. #error NS_MAX_RCTSIZE must be either 4096 or 16384 in nicstar.c
  447. #endif
  448. card->vpibits = NS_VPIBITS;
  449. if (card->rct_size == 4096)
  450. card->vcibits = 12 - NS_VPIBITS;
  451. else /* card->rct_size == 16384 */
  452. card->vcibits = 14 - NS_VPIBITS;
  453. /* Initialize the nicstar eeprom/eprom stuff, for the MAC addr */
  454. if (mac[i] == NULL)
  455. nicstar_init_eprom(card->membase);
  456. /* Set the VPI/VCI MSb mask to zero so we can receive OAM cells */
  457. writel(0x00000000, card->membase + VPM);
  458. card->intcnt = 0;
  459. if (request_irq
  460. (pcidev->irq, &ns_irq_handler, IRQF_SHARED, "nicstar", card) != 0) {
  461. pr_err("nicstar%d: can't allocate IRQ %d.\n", i, pcidev->irq);
  462. error = 9;
  463. ns_init_card_error(card, error);
  464. return error;
  465. }
  466. /* Initialize TSQ */
  467. card->tsq.org = dma_alloc_coherent(&card->pcidev->dev,
  468. NS_TSQSIZE + NS_TSQ_ALIGNMENT,
  469. &card->tsq.dma, GFP_KERNEL);
  470. if (card->tsq.org == NULL) {
  471. printk("nicstar%d: can't allocate TSQ.\n", i);
  472. error = 10;
  473. ns_init_card_error(card, error);
  474. return error;
  475. }
  476. card->tsq.base = PTR_ALIGN(card->tsq.org, NS_TSQ_ALIGNMENT);
  477. card->tsq.next = card->tsq.base;
  478. card->tsq.last = card->tsq.base + (NS_TSQ_NUM_ENTRIES - 1);
  479. for (j = 0; j < NS_TSQ_NUM_ENTRIES; j++)
  480. ns_tsi_init(card->tsq.base + j);
  481. writel(0x00000000, card->membase + TSQH);
  482. writel(ALIGN(card->tsq.dma, NS_TSQ_ALIGNMENT), card->membase + TSQB);
  483. PRINTK("nicstar%d: TSQ base at 0x%p.\n", i, card->tsq.base);
  484. /* Initialize RSQ */
  485. card->rsq.org = dma_alloc_coherent(&card->pcidev->dev,
  486. NS_RSQSIZE + NS_RSQ_ALIGNMENT,
  487. &card->rsq.dma, GFP_KERNEL);
  488. if (card->rsq.org == NULL) {
  489. printk("nicstar%d: can't allocate RSQ.\n", i);
  490. error = 11;
  491. ns_init_card_error(card, error);
  492. return error;
  493. }
  494. card->rsq.base = PTR_ALIGN(card->rsq.org, NS_RSQ_ALIGNMENT);
  495. card->rsq.next = card->rsq.base;
  496. card->rsq.last = card->rsq.base + (NS_RSQ_NUM_ENTRIES - 1);
  497. for (j = 0; j < NS_RSQ_NUM_ENTRIES; j++)
  498. ns_rsqe_init(card->rsq.base + j);
  499. writel(0x00000000, card->membase + RSQH);
  500. writel(ALIGN(card->rsq.dma, NS_RSQ_ALIGNMENT), card->membase + RSQB);
  501. PRINTK("nicstar%d: RSQ base at 0x%p.\n", i, card->rsq.base);
  502. /* Initialize SCQ0, the only VBR SCQ used */
  503. card->scq1 = NULL;
  504. card->scq2 = NULL;
  505. card->scq0 = get_scq(card, VBR_SCQSIZE, NS_VRSCD0);
  506. if (card->scq0 == NULL) {
  507. printk("nicstar%d: can't get SCQ0.\n", i);
  508. error = 12;
  509. ns_init_card_error(card, error);
  510. return error;
  511. }
  512. u32d[0] = scq_virt_to_bus(card->scq0, card->scq0->base);
  513. u32d[1] = (u32) 0x00000000;
  514. u32d[2] = (u32) 0xffffffff;
  515. u32d[3] = (u32) 0x00000000;
  516. ns_write_sram(card, NS_VRSCD0, u32d, 4);
  517. ns_write_sram(card, NS_VRSCD1, u32d, 4); /* These last two won't be used */
  518. ns_write_sram(card, NS_VRSCD2, u32d, 4); /* but are initialized, just in case... */
  519. card->scq0->scd = NS_VRSCD0;
  520. PRINTK("nicstar%d: VBR-SCQ0 base at 0x%p.\n", i, card->scq0->base);
  521. /* Initialize TSTs */
  522. card->tst_addr = NS_TST0;
  523. card->tst_free_entries = NS_TST_NUM_ENTRIES;
  524. data = NS_TST_OPCODE_VARIABLE;
  525. for (j = 0; j < NS_TST_NUM_ENTRIES; j++)
  526. ns_write_sram(card, NS_TST0 + j, &data, 1);
  527. data = ns_tste_make(NS_TST_OPCODE_END, NS_TST0);
  528. ns_write_sram(card, NS_TST0 + NS_TST_NUM_ENTRIES, &data, 1);
  529. for (j = 0; j < NS_TST_NUM_ENTRIES; j++)
  530. ns_write_sram(card, NS_TST1 + j, &data, 1);
  531. data = ns_tste_make(NS_TST_OPCODE_END, NS_TST1);
  532. ns_write_sram(card, NS_TST1 + NS_TST_NUM_ENTRIES, &data, 1);
  533. for (j = 0; j < NS_TST_NUM_ENTRIES; j++)
  534. card->tste2vc[j] = NULL;
  535. writel(NS_TST0 << 2, card->membase + TSTB);
  536. /* Initialize RCT. AAL type is set on opening the VC. */
  537. #ifdef RCQ_SUPPORT
  538. u32d[0] = NS_RCTE_RAWCELLINTEN;
  539. #else
  540. u32d[0] = 0x00000000;
  541. #endif /* RCQ_SUPPORT */
  542. u32d[1] = 0x00000000;
  543. u32d[2] = 0x00000000;
  544. u32d[3] = 0xFFFFFFFF;
  545. for (j = 0; j < card->rct_size; j++)
  546. ns_write_sram(card, j * 4, u32d, 4);
  547. memset(card->vcmap, 0, sizeof(card->vcmap));
  548. for (j = 0; j < NS_FRSCD_NUM; j++)
  549. card->scd2vc[j] = NULL;
  550. /* Initialize buffer levels */
  551. card->sbnr.min = MIN_SB;
  552. card->sbnr.init = NUM_SB;
  553. card->sbnr.max = MAX_SB;
  554. card->lbnr.min = MIN_LB;
  555. card->lbnr.init = NUM_LB;
  556. card->lbnr.max = MAX_LB;
  557. card->iovnr.min = MIN_IOVB;
  558. card->iovnr.init = NUM_IOVB;
  559. card->iovnr.max = MAX_IOVB;
  560. card->hbnr.min = MIN_HB;
  561. card->hbnr.init = NUM_HB;
  562. card->hbnr.max = MAX_HB;
  563. card->sm_handle = NULL;
  564. card->sm_addr = 0x00000000;
  565. card->lg_handle = NULL;
  566. card->lg_addr = 0x00000000;
  567. card->efbie = 1; /* To prevent push_rxbufs from enabling the interrupt */
  568. idr_init(&card->idr);
  569. /* Pre-allocate some huge buffers */
  570. skb_queue_head_init(&card->hbpool.queue);
  571. card->hbpool.count = 0;
  572. for (j = 0; j < NUM_HB; j++) {
  573. struct sk_buff *hb;
  574. hb = __dev_alloc_skb(NS_HBUFSIZE, GFP_KERNEL);
  575. if (hb == NULL) {
  576. printk
  577. ("nicstar%d: can't allocate %dth of %d huge buffers.\n",
  578. i, j, NUM_HB);
  579. error = 13;
  580. ns_init_card_error(card, error);
  581. return error;
  582. }
  583. NS_PRV_BUFTYPE(hb) = BUF_NONE;
  584. skb_queue_tail(&card->hbpool.queue, hb);
  585. card->hbpool.count++;
  586. }
  587. /* Allocate large buffers */
  588. skb_queue_head_init(&card->lbpool.queue);
  589. card->lbpool.count = 0; /* Not used */
  590. for (j = 0; j < NUM_LB; j++) {
  591. struct sk_buff *lb;
  592. lb = __dev_alloc_skb(NS_LGSKBSIZE, GFP_KERNEL);
  593. if (lb == NULL) {
  594. printk
  595. ("nicstar%d: can't allocate %dth of %d large buffers.\n",
  596. i, j, NUM_LB);
  597. error = 14;
  598. ns_init_card_error(card, error);
  599. return error;
  600. }
  601. NS_PRV_BUFTYPE(lb) = BUF_LG;
  602. skb_queue_tail(&card->lbpool.queue, lb);
  603. skb_reserve(lb, NS_SMBUFSIZE);
  604. push_rxbufs(card, lb);
  605. /* Due to the implementation of push_rxbufs() this is 1, not 0 */
  606. if (j == 1) {
  607. card->rcbuf = lb;
  608. card->rawcell = (struct ns_rcqe *) lb->data;
  609. card->rawch = NS_PRV_DMA(lb);
  610. }
  611. }
  612. /* Test for strange behaviour which leads to crashes */
  613. if ((bcount =
  614. ns_stat_lfbqc_get(readl(card->membase + STAT))) < card->lbnr.min) {
  615. printk
  616. ("nicstar%d: Strange... Just allocated %d large buffers and lfbqc = %d.\n",
  617. i, j, bcount);
  618. error = 14;
  619. ns_init_card_error(card, error);
  620. return error;
  621. }
  622. /* Allocate small buffers */
  623. skb_queue_head_init(&card->sbpool.queue);
  624. card->sbpool.count = 0; /* Not used */
  625. for (j = 0; j < NUM_SB; j++) {
  626. struct sk_buff *sb;
  627. sb = __dev_alloc_skb(NS_SMSKBSIZE, GFP_KERNEL);
  628. if (sb == NULL) {
  629. printk
  630. ("nicstar%d: can't allocate %dth of %d small buffers.\n",
  631. i, j, NUM_SB);
  632. error = 15;
  633. ns_init_card_error(card, error);
  634. return error;
  635. }
  636. NS_PRV_BUFTYPE(sb) = BUF_SM;
  637. skb_queue_tail(&card->sbpool.queue, sb);
  638. skb_reserve(sb, NS_AAL0_HEADER);
  639. push_rxbufs(card, sb);
  640. }
  641. /* Test for strange behaviour which leads to crashes */
  642. if ((bcount =
  643. ns_stat_sfbqc_get(readl(card->membase + STAT))) < card->sbnr.min) {
  644. printk
  645. ("nicstar%d: Strange... Just allocated %d small buffers and sfbqc = %d.\n",
  646. i, j, bcount);
  647. error = 15;
  648. ns_init_card_error(card, error);
  649. return error;
  650. }
  651. /* Allocate iovec buffers */
  652. skb_queue_head_init(&card->iovpool.queue);
  653. card->iovpool.count = 0;
  654. for (j = 0; j < NUM_IOVB; j++) {
  655. struct sk_buff *iovb;
  656. iovb = alloc_skb(NS_IOVBUFSIZE, GFP_KERNEL);
  657. if (iovb == NULL) {
  658. printk
  659. ("nicstar%d: can't allocate %dth of %d iovec buffers.\n",
  660. i, j, NUM_IOVB);
  661. error = 16;
  662. ns_init_card_error(card, error);
  663. return error;
  664. }
  665. NS_PRV_BUFTYPE(iovb) = BUF_NONE;
  666. skb_queue_tail(&card->iovpool.queue, iovb);
  667. card->iovpool.count++;
  668. }
  669. /* Configure NICStAR */
  670. if (card->rct_size == 4096)
  671. ns_cfg_rctsize = NS_CFG_RCTSIZE_4096_ENTRIES;
  672. else /* (card->rct_size == 16384) */
  673. ns_cfg_rctsize = NS_CFG_RCTSIZE_16384_ENTRIES;
  674. card->efbie = 1;
  675. /* Register device */
  676. card->atmdev = atm_dev_register("nicstar", &card->pcidev->dev, &atm_ops,
  677. -1, NULL);
  678. if (card->atmdev == NULL) {
  679. printk("nicstar%d: can't register device.\n", i);
  680. error = 17;
  681. ns_init_card_error(card, error);
  682. return error;
  683. }
  684. if (mac[i] == NULL || !mac_pton(mac[i], card->atmdev->esi)) {
  685. nicstar_read_eprom(card->membase, NICSTAR_EPROM_MAC_ADDR_OFFSET,
  686. card->atmdev->esi, 6);
  687. if (ether_addr_equal(card->atmdev->esi, "\x00\x00\x00\x00\x00\x00")) {
  688. nicstar_read_eprom(card->membase,
  689. NICSTAR_EPROM_MAC_ADDR_OFFSET_ALT,
  690. card->atmdev->esi, 6);
  691. }
  692. }
  693. printk("nicstar%d: MAC address %pM\n", i, card->atmdev->esi);
  694. card->atmdev->dev_data = card;
  695. card->atmdev->ci_range.vpi_bits = card->vpibits;
  696. card->atmdev->ci_range.vci_bits = card->vcibits;
  697. card->atmdev->link_rate = card->max_pcr;
  698. card->atmdev->phy = NULL;
  699. #ifdef CONFIG_ATM_NICSTAR_USE_SUNI
  700. if (card->max_pcr == ATM_OC3_PCR)
  701. suni_init(card->atmdev);
  702. #endif /* CONFIG_ATM_NICSTAR_USE_SUNI */
  703. #ifdef CONFIG_ATM_NICSTAR_USE_IDT77105
  704. if (card->max_pcr == ATM_25_PCR)
  705. idt77105_init(card->atmdev);
  706. #endif /* CONFIG_ATM_NICSTAR_USE_IDT77105 */
  707. if (card->atmdev->phy && card->atmdev->phy->start)
  708. card->atmdev->phy->start(card->atmdev);
  709. writel(NS_CFG_RXPATH | NS_CFG_SMBUFSIZE | NS_CFG_LGBUFSIZE | NS_CFG_EFBIE | NS_CFG_RSQSIZE | NS_CFG_VPIBITS | ns_cfg_rctsize | NS_CFG_RXINT_NODELAY | NS_CFG_RAWIE | /* Only enabled if RCQ_SUPPORT */
  710. NS_CFG_RSQAFIE | NS_CFG_TXEN | NS_CFG_TXIE | NS_CFG_TSQFIE_OPT | /* Only enabled if ENABLE_TSQFIE */
  711. NS_CFG_PHYIE, card->membase + CFG);
  712. num_cards++;
  713. return error;
  714. }
  715. static void ns_init_card_error(ns_dev *card, int error)
  716. {
  717. if (error >= 17) {
  718. writel(0x00000000, card->membase + CFG);
  719. }
  720. if (error >= 16) {
  721. struct sk_buff *iovb;
  722. while ((iovb = skb_dequeue(&card->iovpool.queue)) != NULL)
  723. dev_kfree_skb_any(iovb);
  724. }
  725. if (error >= 15) {
  726. struct sk_buff *sb;
  727. while ((sb = skb_dequeue(&card->sbpool.queue)) != NULL)
  728. dev_kfree_skb_any(sb);
  729. free_scq(card, card->scq0, NULL);
  730. }
  731. if (error >= 14) {
  732. struct sk_buff *lb;
  733. while ((lb = skb_dequeue(&card->lbpool.queue)) != NULL)
  734. dev_kfree_skb_any(lb);
  735. }
  736. if (error >= 13) {
  737. struct sk_buff *hb;
  738. while ((hb = skb_dequeue(&card->hbpool.queue)) != NULL)
  739. dev_kfree_skb_any(hb);
  740. }
  741. if (error >= 12) {
  742. dma_free_coherent(&card->pcidev->dev, NS_RSQSIZE + NS_RSQ_ALIGNMENT,
  743. card->rsq.org, card->rsq.dma);
  744. }
  745. if (error >= 11) {
  746. dma_free_coherent(&card->pcidev->dev, NS_TSQSIZE + NS_TSQ_ALIGNMENT,
  747. card->tsq.org, card->tsq.dma);
  748. }
  749. if (error >= 10) {
  750. free_irq(card->pcidev->irq, card);
  751. }
  752. if (error >= 4) {
  753. iounmap(card->membase);
  754. }
  755. if (error >= 3) {
  756. pci_disable_device(card->pcidev);
  757. kfree(card);
  758. }
  759. }
  760. static scq_info *get_scq(ns_dev *card, int size, u32 scd)
  761. {
  762. scq_info *scq;
  763. int i;
  764. if (size != VBR_SCQSIZE && size != CBR_SCQSIZE)
  765. return NULL;
  766. scq = kmalloc(sizeof(*scq), GFP_KERNEL);
  767. if (!scq)
  768. return NULL;
  769. scq->org = dma_alloc_coherent(&card->pcidev->dev,
  770. 2 * size, &scq->dma, GFP_KERNEL);
  771. if (!scq->org) {
  772. kfree(scq);
  773. return NULL;
  774. }
  775. scq->skb = kmalloc_array(size / NS_SCQE_SIZE,
  776. sizeof(*scq->skb),
  777. GFP_KERNEL);
  778. if (!scq->skb) {
  779. dma_free_coherent(&card->pcidev->dev,
  780. 2 * size, scq->org, scq->dma);
  781. kfree(scq);
  782. return NULL;
  783. }
  784. scq->num_entries = size / NS_SCQE_SIZE;
  785. scq->base = PTR_ALIGN(scq->org, size);
  786. scq->next = scq->base;
  787. scq->last = scq->base + (scq->num_entries - 1);
  788. scq->tail = scq->last;
  789. scq->scd = scd;
  790. scq->num_entries = size / NS_SCQE_SIZE;
  791. scq->tbd_count = 0;
  792. init_waitqueue_head(&scq->scqfull_waitq);
  793. scq->full = 0;
  794. spin_lock_init(&scq->lock);
  795. for (i = 0; i < scq->num_entries; i++)
  796. scq->skb[i] = NULL;
  797. return scq;
  798. }
  799. /* For variable rate SCQ vcc must be NULL */
  800. static void free_scq(ns_dev *card, scq_info *scq, struct atm_vcc *vcc)
  801. {
  802. int i;
  803. if (scq->num_entries == VBR_SCQ_NUM_ENTRIES)
  804. for (i = 0; i < scq->num_entries; i++) {
  805. if (scq->skb[i] != NULL) {
  806. vcc = ATM_SKB(scq->skb[i])->vcc;
  807. if (vcc->pop != NULL)
  808. vcc->pop(vcc, scq->skb[i]);
  809. else
  810. dev_kfree_skb_any(scq->skb[i]);
  811. }
  812. } else { /* vcc must be != NULL */
  813. if (vcc == NULL) {
  814. printk
  815. ("nicstar: free_scq() called with vcc == NULL for fixed rate scq.");
  816. for (i = 0; i < scq->num_entries; i++)
  817. dev_kfree_skb_any(scq->skb[i]);
  818. } else
  819. for (i = 0; i < scq->num_entries; i++) {
  820. if (scq->skb[i] != NULL) {
  821. if (vcc->pop != NULL)
  822. vcc->pop(vcc, scq->skb[i]);
  823. else
  824. dev_kfree_skb_any(scq->skb[i]);
  825. }
  826. }
  827. }
  828. kfree(scq->skb);
  829. dma_free_coherent(&card->pcidev->dev,
  830. 2 * (scq->num_entries == VBR_SCQ_NUM_ENTRIES ?
  831. VBR_SCQSIZE : CBR_SCQSIZE),
  832. scq->org, scq->dma);
  833. kfree(scq);
  834. }
  835. /* The handles passed must be pointers to the sk_buff containing the small
  836. or large buffer(s) cast to u32. */
  837. static void push_rxbufs(ns_dev * card, struct sk_buff *skb)
  838. {
  839. struct sk_buff *handle1, *handle2;
  840. int id1, id2;
  841. u32 addr1, addr2;
  842. u32 stat;
  843. unsigned long flags;
  844. /* *BARF* */
  845. handle2 = NULL;
  846. addr2 = 0;
  847. handle1 = skb;
  848. addr1 = dma_map_single(&card->pcidev->dev,
  849. skb->data,
  850. (NS_PRV_BUFTYPE(skb) == BUF_SM
  851. ? NS_SMSKBSIZE : NS_LGSKBSIZE),
  852. DMA_TO_DEVICE);
  853. NS_PRV_DMA(skb) = addr1; /* save so we can unmap later */
  854. #ifdef GENERAL_DEBUG
  855. if (!addr1)
  856. printk("nicstar%d: push_rxbufs called with addr1 = 0.\n",
  857. card->index);
  858. #endif /* GENERAL_DEBUG */
  859. stat = readl(card->membase + STAT);
  860. card->sbfqc = ns_stat_sfbqc_get(stat);
  861. card->lbfqc = ns_stat_lfbqc_get(stat);
  862. if (NS_PRV_BUFTYPE(skb) == BUF_SM) {
  863. if (!addr2) {
  864. if (card->sm_addr) {
  865. addr2 = card->sm_addr;
  866. handle2 = card->sm_handle;
  867. card->sm_addr = 0x00000000;
  868. card->sm_handle = NULL;
  869. } else { /* (!sm_addr) */
  870. card->sm_addr = addr1;
  871. card->sm_handle = handle1;
  872. }
  873. }
  874. } else { /* buf_type == BUF_LG */
  875. if (!addr2) {
  876. if (card->lg_addr) {
  877. addr2 = card->lg_addr;
  878. handle2 = card->lg_handle;
  879. card->lg_addr = 0x00000000;
  880. card->lg_handle = NULL;
  881. } else { /* (!lg_addr) */
  882. card->lg_addr = addr1;
  883. card->lg_handle = handle1;
  884. }
  885. }
  886. }
  887. if (addr2) {
  888. if (NS_PRV_BUFTYPE(skb) == BUF_SM) {
  889. if (card->sbfqc >= card->sbnr.max) {
  890. skb_unlink(handle1, &card->sbpool.queue);
  891. dev_kfree_skb_any(handle1);
  892. skb_unlink(handle2, &card->sbpool.queue);
  893. dev_kfree_skb_any(handle2);
  894. return;
  895. } else
  896. card->sbfqc += 2;
  897. } else { /* (buf_type == BUF_LG) */
  898. if (card->lbfqc >= card->lbnr.max) {
  899. skb_unlink(handle1, &card->lbpool.queue);
  900. dev_kfree_skb_any(handle1);
  901. skb_unlink(handle2, &card->lbpool.queue);
  902. dev_kfree_skb_any(handle2);
  903. return;
  904. } else
  905. card->lbfqc += 2;
  906. }
  907. id1 = idr_alloc(&card->idr, handle1, 0, 0, GFP_ATOMIC);
  908. if (id1 < 0)
  909. goto out;
  910. id2 = idr_alloc(&card->idr, handle2, 0, 0, GFP_ATOMIC);
  911. if (id2 < 0)
  912. goto out;
  913. spin_lock_irqsave(&card->res_lock, flags);
  914. while (CMD_BUSY(card)) ;
  915. writel(addr2, card->membase + DR3);
  916. writel(id2, card->membase + DR2);
  917. writel(addr1, card->membase + DR1);
  918. writel(id1, card->membase + DR0);
  919. writel(NS_CMD_WRITE_FREEBUFQ | NS_PRV_BUFTYPE(skb),
  920. card->membase + CMD);
  921. spin_unlock_irqrestore(&card->res_lock, flags);
  922. XPRINTK("nicstar%d: Pushing %s buffers at 0x%x and 0x%x.\n",
  923. card->index,
  924. (NS_PRV_BUFTYPE(skb) == BUF_SM ? "small" : "large"),
  925. addr1, addr2);
  926. }
  927. if (!card->efbie && card->sbfqc >= card->sbnr.min &&
  928. card->lbfqc >= card->lbnr.min) {
  929. card->efbie = 1;
  930. writel((readl(card->membase + CFG) | NS_CFG_EFBIE),
  931. card->membase + CFG);
  932. }
  933. out:
  934. return;
  935. }
  936. static irqreturn_t ns_irq_handler(int irq, void *dev_id)
  937. {
  938. u32 stat_r;
  939. ns_dev *card;
  940. struct atm_dev *dev;
  941. unsigned long flags;
  942. card = (ns_dev *) dev_id;
  943. dev = card->atmdev;
  944. card->intcnt++;
  945. PRINTK("nicstar%d: NICStAR generated an interrupt\n", card->index);
  946. spin_lock_irqsave(&card->int_lock, flags);
  947. stat_r = readl(card->membase + STAT);
  948. /* Transmit Status Indicator has been written to T. S. Queue */
  949. if (stat_r & NS_STAT_TSIF) {
  950. TXPRINTK("nicstar%d: TSI interrupt\n", card->index);
  951. process_tsq(card);
  952. writel(NS_STAT_TSIF, card->membase + STAT);
  953. }
  954. /* Incomplete CS-PDU has been transmitted */
  955. if (stat_r & NS_STAT_TXICP) {
  956. writel(NS_STAT_TXICP, card->membase + STAT);
  957. TXPRINTK("nicstar%d: Incomplete CS-PDU transmitted.\n",
  958. card->index);
  959. }
  960. /* Transmit Status Queue 7/8 full */
  961. if (stat_r & NS_STAT_TSQF) {
  962. writel(NS_STAT_TSQF, card->membase + STAT);
  963. PRINTK("nicstar%d: TSQ full.\n", card->index);
  964. process_tsq(card);
  965. }
  966. /* Timer overflow */
  967. if (stat_r & NS_STAT_TMROF) {
  968. writel(NS_STAT_TMROF, card->membase + STAT);
  969. PRINTK("nicstar%d: Timer overflow.\n", card->index);
  970. }
  971. /* PHY device interrupt signal active */
  972. if (stat_r & NS_STAT_PHYI) {
  973. writel(NS_STAT_PHYI, card->membase + STAT);
  974. PRINTK("nicstar%d: PHY interrupt.\n", card->index);
  975. if (dev->phy && dev->phy->interrupt) {
  976. dev->phy->interrupt(dev);
  977. }
  978. }
  979. /* Small Buffer Queue is full */
  980. if (stat_r & NS_STAT_SFBQF) {
  981. writel(NS_STAT_SFBQF, card->membase + STAT);
  982. printk("nicstar%d: Small free buffer queue is full.\n",
  983. card->index);
  984. }
  985. /* Large Buffer Queue is full */
  986. if (stat_r & NS_STAT_LFBQF) {
  987. writel(NS_STAT_LFBQF, card->membase + STAT);
  988. printk("nicstar%d: Large free buffer queue is full.\n",
  989. card->index);
  990. }
  991. /* Receive Status Queue is full */
  992. if (stat_r & NS_STAT_RSQF) {
  993. writel(NS_STAT_RSQF, card->membase + STAT);
  994. printk("nicstar%d: RSQ full.\n", card->index);
  995. process_rsq(card);
  996. }
  997. /* Complete CS-PDU received */
  998. if (stat_r & NS_STAT_EOPDU) {
  999. RXPRINTK("nicstar%d: End of CS-PDU received.\n", card->index);
  1000. process_rsq(card);
  1001. writel(NS_STAT_EOPDU, card->membase + STAT);
  1002. }
  1003. /* Raw cell received */
  1004. if (stat_r & NS_STAT_RAWCF) {
  1005. writel(NS_STAT_RAWCF, card->membase + STAT);
  1006. #ifndef RCQ_SUPPORT
  1007. printk("nicstar%d: Raw cell received and no support yet...\n",
  1008. card->index);
  1009. #endif /* RCQ_SUPPORT */
  1010. /* NOTE: the following procedure may keep a raw cell pending until the
  1011. next interrupt. As this preliminary support is only meant to
  1012. avoid buffer leakage, this is not an issue. */
  1013. while (readl(card->membase + RAWCT) != card->rawch) {
  1014. if (ns_rcqe_islast(card->rawcell)) {
  1015. struct sk_buff *oldbuf;
  1016. oldbuf = card->rcbuf;
  1017. card->rcbuf = idr_find(&card->idr,
  1018. ns_rcqe_nextbufhandle(card->rawcell));
  1019. card->rawch = NS_PRV_DMA(card->rcbuf);
  1020. card->rawcell = (struct ns_rcqe *)
  1021. card->rcbuf->data;
  1022. recycle_rx_buf(card, oldbuf);
  1023. } else {
  1024. card->rawch += NS_RCQE_SIZE;
  1025. card->rawcell++;
  1026. }
  1027. }
  1028. }
  1029. /* Small buffer queue is empty */
  1030. if (stat_r & NS_STAT_SFBQE) {
  1031. int i;
  1032. struct sk_buff *sb;
  1033. writel(NS_STAT_SFBQE, card->membase + STAT);
  1034. printk("nicstar%d: Small free buffer queue empty.\n",
  1035. card->index);
  1036. for (i = 0; i < card->sbnr.min; i++) {
  1037. sb = dev_alloc_skb(NS_SMSKBSIZE);
  1038. if (sb == NULL) {
  1039. writel(readl(card->membase + CFG) &
  1040. ~NS_CFG_EFBIE, card->membase + CFG);
  1041. card->efbie = 0;
  1042. break;
  1043. }
  1044. NS_PRV_BUFTYPE(sb) = BUF_SM;
  1045. skb_queue_tail(&card->sbpool.queue, sb);
  1046. skb_reserve(sb, NS_AAL0_HEADER);
  1047. push_rxbufs(card, sb);
  1048. }
  1049. card->sbfqc = i;
  1050. process_rsq(card);
  1051. }
  1052. /* Large buffer queue empty */
  1053. if (stat_r & NS_STAT_LFBQE) {
  1054. int i;
  1055. struct sk_buff *lb;
  1056. writel(NS_STAT_LFBQE, card->membase + STAT);
  1057. printk("nicstar%d: Large free buffer queue empty.\n",
  1058. card->index);
  1059. for (i = 0; i < card->lbnr.min; i++) {
  1060. lb = dev_alloc_skb(NS_LGSKBSIZE);
  1061. if (lb == NULL) {
  1062. writel(readl(card->membase + CFG) &
  1063. ~NS_CFG_EFBIE, card->membase + CFG);
  1064. card->efbie = 0;
  1065. break;
  1066. }
  1067. NS_PRV_BUFTYPE(lb) = BUF_LG;
  1068. skb_queue_tail(&card->lbpool.queue, lb);
  1069. skb_reserve(lb, NS_SMBUFSIZE);
  1070. push_rxbufs(card, lb);
  1071. }
  1072. card->lbfqc = i;
  1073. process_rsq(card);
  1074. }
  1075. /* Receive Status Queue is 7/8 full */
  1076. if (stat_r & NS_STAT_RSQAF) {
  1077. writel(NS_STAT_RSQAF, card->membase + STAT);
  1078. RXPRINTK("nicstar%d: RSQ almost full.\n", card->index);
  1079. process_rsq(card);
  1080. }
  1081. spin_unlock_irqrestore(&card->int_lock, flags);
  1082. PRINTK("nicstar%d: end of interrupt service\n", card->index);
  1083. return IRQ_HANDLED;
  1084. }
  1085. static int ns_open(struct atm_vcc *vcc)
  1086. {
  1087. ns_dev *card;
  1088. vc_map *vc;
  1089. unsigned long tmpl, modl;
  1090. int tcr, tcra; /* target cell rate, and absolute value */
  1091. int n = 0; /* Number of entries in the TST. Initialized to remove
  1092. the compiler warning. */
  1093. u32 u32d[4];
  1094. int frscdi = 0; /* Index of the SCD. Initialized to remove the compiler
  1095. warning. How I wish compilers were clever enough to
  1096. tell which variables can truly be used
  1097. uninitialized... */
  1098. int inuse; /* tx or rx vc already in use by another vcc */
  1099. short vpi = vcc->vpi;
  1100. int vci = vcc->vci;
  1101. card = (ns_dev *) vcc->dev->dev_data;
  1102. PRINTK("nicstar%d: opening vpi.vci %d.%d \n", card->index, (int)vpi,
  1103. vci);
  1104. if (vcc->qos.aal != ATM_AAL5 && vcc->qos.aal != ATM_AAL0) {
  1105. PRINTK("nicstar%d: unsupported AAL.\n", card->index);
  1106. return -EINVAL;
  1107. }
  1108. vc = &(card->vcmap[vpi << card->vcibits | vci]);
  1109. vcc->dev_data = vc;
  1110. inuse = 0;
  1111. if (vcc->qos.txtp.traffic_class != ATM_NONE && vc->tx)
  1112. inuse = 1;
  1113. if (vcc->qos.rxtp.traffic_class != ATM_NONE && vc->rx)
  1114. inuse += 2;
  1115. if (inuse) {
  1116. printk("nicstar%d: %s vci already in use.\n", card->index,
  1117. inuse == 1 ? "tx" : inuse == 2 ? "rx" : "tx and rx");
  1118. return -EINVAL;
  1119. }
  1120. set_bit(ATM_VF_ADDR, &vcc->flags);
  1121. /* NOTE: You are not allowed to modify an open connection's QOS. To change
  1122. that, remove the ATM_VF_PARTIAL flag checking. There may be other changes
  1123. needed to do that. */
  1124. if (!test_bit(ATM_VF_PARTIAL, &vcc->flags)) {
  1125. scq_info *scq;
  1126. set_bit(ATM_VF_PARTIAL, &vcc->flags);
  1127. if (vcc->qos.txtp.traffic_class == ATM_CBR) {
  1128. /* Check requested cell rate and availability of SCD */
  1129. if (vcc->qos.txtp.max_pcr == 0 && vcc->qos.txtp.pcr == 0
  1130. && vcc->qos.txtp.min_pcr == 0) {
  1131. PRINTK
  1132. ("nicstar%d: trying to open a CBR vc with cell rate = 0 \n",
  1133. card->index);
  1134. clear_bit(ATM_VF_PARTIAL, &vcc->flags);
  1135. clear_bit(ATM_VF_ADDR, &vcc->flags);
  1136. return -EINVAL;
  1137. }
  1138. tcr = atm_pcr_goal(&(vcc->qos.txtp));
  1139. tcra = tcr >= 0 ? tcr : -tcr;
  1140. PRINTK("nicstar%d: target cell rate = %d.\n",
  1141. card->index, vcc->qos.txtp.max_pcr);
  1142. tmpl =
  1143. (unsigned long)tcra *(unsigned long)
  1144. NS_TST_NUM_ENTRIES;
  1145. modl = tmpl % card->max_pcr;
  1146. n = (int)(tmpl / card->max_pcr);
  1147. if (tcr > 0) {
  1148. if (modl > 0)
  1149. n++;
  1150. } else if (tcr == 0) {
  1151. if ((n =
  1152. (card->tst_free_entries -
  1153. NS_TST_RESERVED)) <= 0) {
  1154. PRINTK
  1155. ("nicstar%d: no CBR bandwidth free.\n",
  1156. card->index);
  1157. clear_bit(ATM_VF_PARTIAL, &vcc->flags);
  1158. clear_bit(ATM_VF_ADDR, &vcc->flags);
  1159. return -EINVAL;
  1160. }
  1161. }
  1162. if (n == 0) {
  1163. printk
  1164. ("nicstar%d: selected bandwidth < granularity.\n",
  1165. card->index);
  1166. clear_bit(ATM_VF_PARTIAL, &vcc->flags);
  1167. clear_bit(ATM_VF_ADDR, &vcc->flags);
  1168. return -EINVAL;
  1169. }
  1170. if (n > (card->tst_free_entries - NS_TST_RESERVED)) {
  1171. PRINTK
  1172. ("nicstar%d: not enough free CBR bandwidth.\n",
  1173. card->index);
  1174. clear_bit(ATM_VF_PARTIAL, &vcc->flags);
  1175. clear_bit(ATM_VF_ADDR, &vcc->flags);
  1176. return -EINVAL;
  1177. } else
  1178. card->tst_free_entries -= n;
  1179. XPRINTK("nicstar%d: writing %d tst entries.\n",
  1180. card->index, n);
  1181. for (frscdi = 0; frscdi < NS_FRSCD_NUM; frscdi++) {
  1182. if (card->scd2vc[frscdi] == NULL) {
  1183. card->scd2vc[frscdi] = vc;
  1184. break;
  1185. }
  1186. }
  1187. if (frscdi == NS_FRSCD_NUM) {
  1188. PRINTK
  1189. ("nicstar%d: no SCD available for CBR channel.\n",
  1190. card->index);
  1191. card->tst_free_entries += n;
  1192. clear_bit(ATM_VF_PARTIAL, &vcc->flags);
  1193. clear_bit(ATM_VF_ADDR, &vcc->flags);
  1194. return -EBUSY;
  1195. }
  1196. vc->cbr_scd = NS_FRSCD + frscdi * NS_FRSCD_SIZE;
  1197. scq = get_scq(card, CBR_SCQSIZE, vc->cbr_scd);
  1198. if (scq == NULL) {
  1199. PRINTK("nicstar%d: can't get fixed rate SCQ.\n",
  1200. card->index);
  1201. card->scd2vc[frscdi] = NULL;
  1202. card->tst_free_entries += n;
  1203. clear_bit(ATM_VF_PARTIAL, &vcc->flags);
  1204. clear_bit(ATM_VF_ADDR, &vcc->flags);
  1205. return -ENOMEM;
  1206. }
  1207. vc->scq = scq;
  1208. u32d[0] = scq_virt_to_bus(scq, scq->base);
  1209. u32d[1] = (u32) 0x00000000;
  1210. u32d[2] = (u32) 0xffffffff;
  1211. u32d[3] = (u32) 0x00000000;
  1212. ns_write_sram(card, vc->cbr_scd, u32d, 4);
  1213. fill_tst(card, n, vc);
  1214. } else if (vcc->qos.txtp.traffic_class == ATM_UBR) {
  1215. vc->cbr_scd = 0x00000000;
  1216. vc->scq = card->scq0;
  1217. }
  1218. if (vcc->qos.txtp.traffic_class != ATM_NONE) {
  1219. vc->tx = 1;
  1220. vc->tx_vcc = vcc;
  1221. vc->tbd_count = 0;
  1222. }
  1223. if (vcc->qos.rxtp.traffic_class != ATM_NONE) {
  1224. u32 status;
  1225. vc->rx = 1;
  1226. vc->rx_vcc = vcc;
  1227. vc->rx_iov = NULL;
  1228. /* Open the connection in hardware */
  1229. if (vcc->qos.aal == ATM_AAL5)
  1230. status = NS_RCTE_AAL5 | NS_RCTE_CONNECTOPEN;
  1231. else /* vcc->qos.aal == ATM_AAL0 */
  1232. status = NS_RCTE_AAL0 | NS_RCTE_CONNECTOPEN;
  1233. #ifdef RCQ_SUPPORT
  1234. status |= NS_RCTE_RAWCELLINTEN;
  1235. #endif /* RCQ_SUPPORT */
  1236. ns_write_sram(card,
  1237. NS_RCT +
  1238. (vpi << card->vcibits | vci) *
  1239. NS_RCT_ENTRY_SIZE, &status, 1);
  1240. }
  1241. }
  1242. set_bit(ATM_VF_READY, &vcc->flags);
  1243. return 0;
  1244. }
  1245. static void ns_close(struct atm_vcc *vcc)
  1246. {
  1247. vc_map *vc;
  1248. ns_dev *card;
  1249. u32 data;
  1250. int i;
  1251. vc = vcc->dev_data;
  1252. card = vcc->dev->dev_data;
  1253. PRINTK("nicstar%d: closing vpi.vci %d.%d \n", card->index,
  1254. (int)vcc->vpi, vcc->vci);
  1255. clear_bit(ATM_VF_READY, &vcc->flags);
  1256. if (vcc->qos.rxtp.traffic_class != ATM_NONE) {
  1257. u32 addr;
  1258. unsigned long flags;
  1259. addr =
  1260. NS_RCT +
  1261. (vcc->vpi << card->vcibits | vcc->vci) * NS_RCT_ENTRY_SIZE;
  1262. spin_lock_irqsave(&card->res_lock, flags);
  1263. while (CMD_BUSY(card)) ;
  1264. writel(NS_CMD_CLOSE_CONNECTION | addr << 2,
  1265. card->membase + CMD);
  1266. spin_unlock_irqrestore(&card->res_lock, flags);
  1267. vc->rx = 0;
  1268. if (vc->rx_iov != NULL) {
  1269. struct sk_buff *iovb;
  1270. u32 stat;
  1271. stat = readl(card->membase + STAT);
  1272. card->sbfqc = ns_stat_sfbqc_get(stat);
  1273. card->lbfqc = ns_stat_lfbqc_get(stat);
  1274. PRINTK
  1275. ("nicstar%d: closing a VC with pending rx buffers.\n",
  1276. card->index);
  1277. iovb = vc->rx_iov;
  1278. recycle_iovec_rx_bufs(card, (struct iovec *)iovb->data,
  1279. NS_PRV_IOVCNT(iovb));
  1280. NS_PRV_IOVCNT(iovb) = 0;
  1281. spin_lock_irqsave(&card->int_lock, flags);
  1282. recycle_iov_buf(card, iovb);
  1283. spin_unlock_irqrestore(&card->int_lock, flags);
  1284. vc->rx_iov = NULL;
  1285. }
  1286. }
  1287. if (vcc->qos.txtp.traffic_class != ATM_NONE) {
  1288. vc->tx = 0;
  1289. }
  1290. if (vcc->qos.txtp.traffic_class == ATM_CBR) {
  1291. unsigned long flags;
  1292. ns_scqe *scqep;
  1293. scq_info *scq;
  1294. scq = vc->scq;
  1295. for (;;) {
  1296. spin_lock_irqsave(&scq->lock, flags);
  1297. scqep = scq->next;
  1298. if (scqep == scq->base)
  1299. scqep = scq->last;
  1300. else
  1301. scqep--;
  1302. if (scqep == scq->tail) {
  1303. spin_unlock_irqrestore(&scq->lock, flags);
  1304. break;
  1305. }
  1306. /* If the last entry is not a TSR, place one in the SCQ in order to
  1307. be able to completely drain it and then close. */
  1308. if (!ns_scqe_is_tsr(scqep) && scq->tail != scq->next) {
  1309. ns_scqe tsr;
  1310. u32 scdi, scqi;
  1311. u32 data;
  1312. int index;
  1313. tsr.word_1 = ns_tsr_mkword_1(NS_TSR_INTENABLE);
  1314. scdi = (vc->cbr_scd - NS_FRSCD) / NS_FRSCD_SIZE;
  1315. scqi = scq->next - scq->base;
  1316. tsr.word_2 = ns_tsr_mkword_2(scdi, scqi);
  1317. tsr.word_3 = 0x00000000;
  1318. tsr.word_4 = 0x00000000;
  1319. *scq->next = tsr;
  1320. index = (int)scqi;
  1321. scq->skb[index] = NULL;
  1322. if (scq->next == scq->last)
  1323. scq->next = scq->base;
  1324. else
  1325. scq->next++;
  1326. data = scq_virt_to_bus(scq, scq->next);
  1327. ns_write_sram(card, scq->scd, &data, 1);
  1328. }
  1329. spin_unlock_irqrestore(&scq->lock, flags);
  1330. schedule();
  1331. }
  1332. /* Free all TST entries */
  1333. data = NS_TST_OPCODE_VARIABLE;
  1334. for (i = 0; i < NS_TST_NUM_ENTRIES; i++) {
  1335. if (card->tste2vc[i] == vc) {
  1336. ns_write_sram(card, card->tst_addr + i, &data,
  1337. 1);
  1338. card->tste2vc[i] = NULL;
  1339. card->tst_free_entries++;
  1340. }
  1341. }
  1342. card->scd2vc[(vc->cbr_scd - NS_FRSCD) / NS_FRSCD_SIZE] = NULL;
  1343. free_scq(card, vc->scq, vcc);
  1344. }
  1345. /* remove all references to vcc before deleting it */
  1346. if (vcc->qos.txtp.traffic_class != ATM_NONE) {
  1347. unsigned long flags;
  1348. scq_info *scq = card->scq0;
  1349. spin_lock_irqsave(&scq->lock, flags);
  1350. for (i = 0; i < scq->num_entries; i++) {
  1351. if (scq->skb[i] && ATM_SKB(scq->skb[i])->vcc == vcc) {
  1352. ATM_SKB(scq->skb[i])->vcc = NULL;
  1353. atm_return(vcc, scq->skb[i]->truesize);
  1354. PRINTK
  1355. ("nicstar: deleted pending vcc mapping\n");
  1356. }
  1357. }
  1358. spin_unlock_irqrestore(&scq->lock, flags);
  1359. }
  1360. vcc->dev_data = NULL;
  1361. clear_bit(ATM_VF_PARTIAL, &vcc->flags);
  1362. clear_bit(ATM_VF_ADDR, &vcc->flags);
  1363. #ifdef RX_DEBUG
  1364. {
  1365. u32 stat, cfg;
  1366. stat = readl(card->membase + STAT);
  1367. cfg = readl(card->membase + CFG);
  1368. printk("STAT = 0x%08X CFG = 0x%08X \n", stat, cfg);
  1369. printk
  1370. ("TSQ: base = 0x%p next = 0x%p last = 0x%p TSQT = 0x%08X \n",
  1371. card->tsq.base, card->tsq.next,
  1372. card->tsq.last, readl(card->membase + TSQT));
  1373. printk
  1374. ("RSQ: base = 0x%p next = 0x%p last = 0x%p RSQT = 0x%08X \n",
  1375. card->rsq.base, card->rsq.next,
  1376. card->rsq.last, readl(card->membase + RSQT));
  1377. printk("Empty free buffer queue interrupt %s \n",
  1378. card->efbie ? "enabled" : "disabled");
  1379. printk("SBCNT = %d count = %d LBCNT = %d count = %d \n",
  1380. ns_stat_sfbqc_get(stat), card->sbpool.count,
  1381. ns_stat_lfbqc_get(stat), card->lbpool.count);
  1382. printk("hbpool.count = %d iovpool.count = %d \n",
  1383. card->hbpool.count, card->iovpool.count);
  1384. }
  1385. #endif /* RX_DEBUG */
  1386. }
  1387. static void fill_tst(ns_dev * card, int n, vc_map * vc)
  1388. {
  1389. u32 new_tst;
  1390. unsigned long cl;
  1391. int e, r;
  1392. u32 data;
  1393. /* It would be very complicated to keep the two TSTs synchronized while
  1394. assuring that writes are only made to the inactive TST. So, for now I
  1395. will use only one TST. If problems occur, I will change this again */
  1396. new_tst = card->tst_addr;
  1397. /* Fill procedure */
  1398. for (e = 0; e < NS_TST_NUM_ENTRIES; e++) {
  1399. if (card->tste2vc[e] == NULL)
  1400. break;
  1401. }
  1402. if (e == NS_TST_NUM_ENTRIES) {
  1403. printk("nicstar%d: No free TST entries found. \n", card->index);
  1404. return;
  1405. }
  1406. r = n;
  1407. cl = NS_TST_NUM_ENTRIES;
  1408. data = ns_tste_make(NS_TST_OPCODE_FIXED, vc->cbr_scd);
  1409. while (r > 0) {
  1410. if (cl >= NS_TST_NUM_ENTRIES && card->tste2vc[e] == NULL) {
  1411. card->tste2vc[e] = vc;
  1412. ns_write_sram(card, new_tst + e, &data, 1);
  1413. cl -= NS_TST_NUM_ENTRIES;
  1414. r--;
  1415. }
  1416. if (++e == NS_TST_NUM_ENTRIES) {
  1417. e = 0;
  1418. }
  1419. cl += n;
  1420. }
  1421. /* End of fill procedure */
  1422. data = ns_tste_make(NS_TST_OPCODE_END, new_tst);
  1423. ns_write_sram(card, new_tst + NS_TST_NUM_ENTRIES, &data, 1);
  1424. ns_write_sram(card, card->tst_addr + NS_TST_NUM_ENTRIES, &data, 1);
  1425. card->tst_addr = new_tst;
  1426. }
  1427. static int ns_send(struct atm_vcc *vcc, struct sk_buff *skb)
  1428. {
  1429. ns_dev *card;
  1430. vc_map *vc;
  1431. scq_info *scq;
  1432. unsigned long buflen;
  1433. ns_scqe scqe;
  1434. u32 flags; /* TBD flags, not CPU flags */
  1435. card = vcc->dev->dev_data;
  1436. TXPRINTK("nicstar%d: ns_send() called.\n", card->index);
  1437. if ((vc = (vc_map *) vcc->dev_data) == NULL) {
  1438. printk("nicstar%d: vcc->dev_data == NULL on ns_send().\n",
  1439. card->index);
  1440. atomic_inc(&vcc->stats->tx_err);
  1441. dev_kfree_skb_any(skb);
  1442. return -EINVAL;
  1443. }
  1444. if (!vc->tx) {
  1445. printk("nicstar%d: Trying to transmit on a non-tx VC.\n",
  1446. card->index);
  1447. atomic_inc(&vcc->stats->tx_err);
  1448. dev_kfree_skb_any(skb);
  1449. return -EINVAL;
  1450. }
  1451. if (vcc->qos.aal != ATM_AAL5 && vcc->qos.aal != ATM_AAL0) {
  1452. printk("nicstar%d: Only AAL0 and AAL5 are supported.\n",
  1453. card->index);
  1454. atomic_inc(&vcc->stats->tx_err);
  1455. dev_kfree_skb_any(skb);
  1456. return -EINVAL;
  1457. }
  1458. if (skb_shinfo(skb)->nr_frags != 0) {
  1459. printk("nicstar%d: No scatter-gather yet.\n", card->index);
  1460. atomic_inc(&vcc->stats->tx_err);
  1461. dev_kfree_skb_any(skb);
  1462. return -EINVAL;
  1463. }
  1464. ATM_SKB(skb)->vcc = vcc;
  1465. NS_PRV_DMA(skb) = dma_map_single(&card->pcidev->dev, skb->data,
  1466. skb->len, DMA_TO_DEVICE);
  1467. if (vcc->qos.aal == ATM_AAL5) {
  1468. buflen = (skb->len + 47 + 8) / 48 * 48; /* Multiple of 48 */
  1469. flags = NS_TBD_AAL5;
  1470. scqe.word_2 = cpu_to_le32(NS_PRV_DMA(skb));
  1471. scqe.word_3 = cpu_to_le32(skb->len);
  1472. scqe.word_4 =
  1473. ns_tbd_mkword_4(0, (u32) vcc->vpi, (u32) vcc->vci, 0,
  1474. ATM_SKB(skb)->
  1475. atm_options & ATM_ATMOPT_CLP ? 1 : 0);
  1476. flags |= NS_TBD_EOPDU;
  1477. } else { /* (vcc->qos.aal == ATM_AAL0) */
  1478. buflen = ATM_CELL_PAYLOAD; /* i.e., 48 bytes */
  1479. flags = NS_TBD_AAL0;
  1480. scqe.word_2 = cpu_to_le32(NS_PRV_DMA(skb) + NS_AAL0_HEADER);
  1481. scqe.word_3 = cpu_to_le32(0x00000000);
  1482. if (*skb->data & 0x02) /* Payload type 1 - end of pdu */
  1483. flags |= NS_TBD_EOPDU;
  1484. scqe.word_4 =
  1485. cpu_to_le32(*((u32 *) skb->data) & ~NS_TBD_VC_MASK);
  1486. /* Force the VPI/VCI to be the same as in VCC struct */
  1487. scqe.word_4 |=
  1488. cpu_to_le32((((u32) vcc->
  1489. vpi) << NS_TBD_VPI_SHIFT | ((u32) vcc->
  1490. vci) <<
  1491. NS_TBD_VCI_SHIFT) & NS_TBD_VC_MASK);
  1492. }
  1493. if (vcc->qos.txtp.traffic_class == ATM_CBR) {
  1494. scqe.word_1 = ns_tbd_mkword_1_novbr(flags, (u32) buflen);
  1495. scq = ((vc_map *) vcc->dev_data)->scq;
  1496. } else {
  1497. scqe.word_1 =
  1498. ns_tbd_mkword_1(flags, (u32) 1, (u32) 1, (u32) buflen);
  1499. scq = card->scq0;
  1500. }
  1501. if (push_scqe(card, vc, scq, &scqe, skb) != 0) {
  1502. atomic_inc(&vcc->stats->tx_err);
  1503. dma_unmap_single(&card->pcidev->dev, NS_PRV_DMA(skb), skb->len,
  1504. DMA_TO_DEVICE);
  1505. dev_kfree_skb_any(skb);
  1506. return -EIO;
  1507. }
  1508. atomic_inc(&vcc->stats->tx);
  1509. return 0;
  1510. }
  1511. static int push_scqe(ns_dev * card, vc_map * vc, scq_info * scq, ns_scqe * tbd,
  1512. struct sk_buff *skb)
  1513. {
  1514. unsigned long flags;
  1515. ns_scqe tsr;
  1516. u32 scdi, scqi;
  1517. int scq_is_vbr;
  1518. u32 data;
  1519. int index;
  1520. spin_lock_irqsave(&scq->lock, flags);
  1521. while (scq->tail == scq->next) {
  1522. if (in_interrupt()) {
  1523. spin_unlock_irqrestore(&scq->lock, flags);
  1524. printk("nicstar%d: Error pushing TBD.\n", card->index);
  1525. return 1;
  1526. }
  1527. scq->full = 1;
  1528. wait_event_interruptible_lock_irq_timeout(scq->scqfull_waitq,
  1529. scq->tail != scq->next,
  1530. scq->lock,
  1531. SCQFULL_TIMEOUT);
  1532. if (scq->full) {
  1533. spin_unlock_irqrestore(&scq->lock, flags);
  1534. printk("nicstar%d: Timeout pushing TBD.\n",
  1535. card->index);
  1536. return 1;
  1537. }
  1538. }
  1539. *scq->next = *tbd;
  1540. index = (int)(scq->next - scq->base);
  1541. scq->skb[index] = skb;
  1542. XPRINTK("nicstar%d: sending skb at 0x%p (pos %d).\n",
  1543. card->index, skb, index);
  1544. XPRINTK("nicstar%d: TBD written:\n0x%x\n0x%x\n0x%x\n0x%x\n at 0x%p.\n",
  1545. card->index, le32_to_cpu(tbd->word_1), le32_to_cpu(tbd->word_2),
  1546. le32_to_cpu(tbd->word_3), le32_to_cpu(tbd->word_4),
  1547. scq->next);
  1548. if (scq->next == scq->last)
  1549. scq->next = scq->base;
  1550. else
  1551. scq->next++;
  1552. vc->tbd_count++;
  1553. if (scq->num_entries == VBR_SCQ_NUM_ENTRIES) {
  1554. scq->tbd_count++;
  1555. scq_is_vbr = 1;
  1556. } else
  1557. scq_is_vbr = 0;
  1558. if (vc->tbd_count >= MAX_TBD_PER_VC
  1559. || scq->tbd_count >= MAX_TBD_PER_SCQ) {
  1560. int has_run = 0;
  1561. while (scq->tail == scq->next) {
  1562. if (in_interrupt()) {
  1563. data = scq_virt_to_bus(scq, scq->next);
  1564. ns_write_sram(card, scq->scd, &data, 1);
  1565. spin_unlock_irqrestore(&scq->lock, flags);
  1566. printk("nicstar%d: Error pushing TSR.\n",
  1567. card->index);
  1568. return 0;
  1569. }
  1570. scq->full = 1;
  1571. if (has_run++)
  1572. break;
  1573. wait_event_interruptible_lock_irq_timeout(scq->scqfull_waitq,
  1574. scq->tail != scq->next,
  1575. scq->lock,
  1576. SCQFULL_TIMEOUT);
  1577. }
  1578. if (!scq->full) {
  1579. tsr.word_1 = ns_tsr_mkword_1(NS_TSR_INTENABLE);
  1580. if (scq_is_vbr)
  1581. scdi = NS_TSR_SCDISVBR;
  1582. else
  1583. scdi = (vc->cbr_scd - NS_FRSCD) / NS_FRSCD_SIZE;
  1584. scqi = scq->next - scq->base;
  1585. tsr.word_2 = ns_tsr_mkword_2(scdi, scqi);
  1586. tsr.word_3 = 0x00000000;
  1587. tsr.word_4 = 0x00000000;
  1588. *scq->next = tsr;
  1589. index = (int)scqi;
  1590. scq->skb[index] = NULL;
  1591. XPRINTK
  1592. ("nicstar%d: TSR written:\n0x%x\n0x%x\n0x%x\n0x%x\n at 0x%p.\n",
  1593. card->index, le32_to_cpu(tsr.word_1),
  1594. le32_to_cpu(tsr.word_2), le32_to_cpu(tsr.word_3),
  1595. le32_to_cpu(tsr.word_4), scq->next);
  1596. if (scq->next == scq->last)
  1597. scq->next = scq->base;
  1598. else
  1599. scq->next++;
  1600. vc->tbd_count = 0;
  1601. scq->tbd_count = 0;
  1602. } else
  1603. PRINTK("nicstar%d: Timeout pushing TSR.\n",
  1604. card->index);
  1605. }
  1606. data = scq_virt_to_bus(scq, scq->next);
  1607. ns_write_sram(card, scq->scd, &data, 1);
  1608. spin_unlock_irqrestore(&scq->lock, flags);
  1609. return 0;
  1610. }
  1611. static void process_tsq(ns_dev * card)
  1612. {
  1613. u32 scdi;
  1614. scq_info *scq;
  1615. ns_tsi *previous = NULL, *one_ahead, *two_ahead;
  1616. int serviced_entries; /* flag indicating at least on entry was serviced */
  1617. serviced_entries = 0;
  1618. if (card->tsq.next == card->tsq.last)
  1619. one_ahead = card->tsq.base;
  1620. else
  1621. one_ahead = card->tsq.next + 1;
  1622. if (one_ahead == card->tsq.last)
  1623. two_ahead = card->tsq.base;
  1624. else
  1625. two_ahead = one_ahead + 1;
  1626. while (!ns_tsi_isempty(card->tsq.next) || !ns_tsi_isempty(one_ahead) ||
  1627. !ns_tsi_isempty(two_ahead))
  1628. /* At most two empty, as stated in the 77201 errata */
  1629. {
  1630. serviced_entries = 1;
  1631. /* Skip the one or two possible empty entries */
  1632. while (ns_tsi_isempty(card->tsq.next)) {
  1633. if (card->tsq.next == card->tsq.last)
  1634. card->tsq.next = card->tsq.base;
  1635. else
  1636. card->tsq.next++;
  1637. }
  1638. if (!ns_tsi_tmrof(card->tsq.next)) {
  1639. scdi = ns_tsi_getscdindex(card->tsq.next);
  1640. if (scdi == NS_TSI_SCDISVBR)
  1641. scq = card->scq0;
  1642. else {
  1643. if (card->scd2vc[scdi] == NULL) {
  1644. printk
  1645. ("nicstar%d: could not find VC from SCD index.\n",
  1646. card->index);
  1647. ns_tsi_init(card->tsq.next);
  1648. return;
  1649. }
  1650. scq = card->scd2vc[scdi]->scq;
  1651. }
  1652. drain_scq(card, scq, ns_tsi_getscqpos(card->tsq.next));
  1653. scq->full = 0;
  1654. wake_up_interruptible(&(scq->scqfull_waitq));
  1655. }
  1656. ns_tsi_init(card->tsq.next);
  1657. previous = card->tsq.next;
  1658. if (card->tsq.next == card->tsq.last)
  1659. card->tsq.next = card->tsq.base;
  1660. else
  1661. card->tsq.next++;
  1662. if (card->tsq.next == card->tsq.last)
  1663. one_ahead = card->tsq.base;
  1664. else
  1665. one_ahead = card->tsq.next + 1;
  1666. if (one_ahead == card->tsq.last)
  1667. two_ahead = card->tsq.base;
  1668. else
  1669. two_ahead = one_ahead + 1;
  1670. }
  1671. if (serviced_entries)
  1672. writel(PTR_DIFF(previous, card->tsq.base),
  1673. card->membase + TSQH);
  1674. }
  1675. static void drain_scq(ns_dev * card, scq_info * scq, int pos)
  1676. {
  1677. struct atm_vcc *vcc;
  1678. struct sk_buff *skb;
  1679. int i;
  1680. unsigned long flags;
  1681. XPRINTK("nicstar%d: drain_scq() called, scq at 0x%p, pos %d.\n",
  1682. card->index, scq, pos);
  1683. if (pos >= scq->num_entries) {
  1684. printk("nicstar%d: Bad index on drain_scq().\n", card->index);
  1685. return;
  1686. }
  1687. spin_lock_irqsave(&scq->lock, flags);
  1688. i = (int)(scq->tail - scq->base);
  1689. if (++i == scq->num_entries)
  1690. i = 0;
  1691. while (i != pos) {
  1692. skb = scq->skb[i];
  1693. XPRINTK("nicstar%d: freeing skb at 0x%p (index %d).\n",
  1694. card->index, skb, i);
  1695. if (skb != NULL) {
  1696. dma_unmap_single(&card->pcidev->dev,
  1697. NS_PRV_DMA(skb),
  1698. skb->len,
  1699. DMA_TO_DEVICE);
  1700. vcc = ATM_SKB(skb)->vcc;
  1701. if (vcc && vcc->pop != NULL) {
  1702. vcc->pop(vcc, skb);
  1703. } else {
  1704. dev_kfree_skb_irq(skb);
  1705. }
  1706. scq->skb[i] = NULL;
  1707. }
  1708. if (++i == scq->num_entries)
  1709. i = 0;
  1710. }
  1711. scq->tail = scq->base + pos;
  1712. spin_unlock_irqrestore(&scq->lock, flags);
  1713. }
  1714. static void process_rsq(ns_dev * card)
  1715. {
  1716. ns_rsqe *previous;
  1717. if (!ns_rsqe_valid(card->rsq.next))
  1718. return;
  1719. do {
  1720. dequeue_rx(card, card->rsq.next);
  1721. ns_rsqe_init(card->rsq.next);
  1722. previous = card->rsq.next;
  1723. if (card->rsq.next == card->rsq.last)
  1724. card->rsq.next = card->rsq.base;
  1725. else
  1726. card->rsq.next++;
  1727. } while (ns_rsqe_valid(card->rsq.next));
  1728. writel(PTR_DIFF(previous, card->rsq.base), card->membase + RSQH);
  1729. }
  1730. static void dequeue_rx(ns_dev * card, ns_rsqe * rsqe)
  1731. {
  1732. u32 vpi, vci;
  1733. vc_map *vc;
  1734. struct sk_buff *iovb;
  1735. struct iovec *iov;
  1736. struct atm_vcc *vcc;
  1737. struct sk_buff *skb;
  1738. unsigned short aal5_len;
  1739. int len;
  1740. u32 stat;
  1741. u32 id;
  1742. stat = readl(card->membase + STAT);
  1743. card->sbfqc = ns_stat_sfbqc_get(stat);
  1744. card->lbfqc = ns_stat_lfbqc_get(stat);
  1745. id = le32_to_cpu(rsqe->buffer_handle);
  1746. skb = idr_remove(&card->idr, id);
  1747. if (!skb) {
  1748. RXPRINTK(KERN_ERR
  1749. "nicstar%d: skb not found!\n", card->index);
  1750. return;
  1751. }
  1752. dma_sync_single_for_cpu(&card->pcidev->dev,
  1753. NS_PRV_DMA(skb),
  1754. (NS_PRV_BUFTYPE(skb) == BUF_SM
  1755. ? NS_SMSKBSIZE : NS_LGSKBSIZE),
  1756. DMA_FROM_DEVICE);
  1757. dma_unmap_single(&card->pcidev->dev,
  1758. NS_PRV_DMA(skb),
  1759. (NS_PRV_BUFTYPE(skb) == BUF_SM
  1760. ? NS_SMSKBSIZE : NS_LGSKBSIZE),
  1761. DMA_FROM_DEVICE);
  1762. vpi = ns_rsqe_vpi(rsqe);
  1763. vci = ns_rsqe_vci(rsqe);
  1764. if (vpi >= 1UL << card->vpibits || vci >= 1UL << card->vcibits) {
  1765. printk("nicstar%d: SDU received for out-of-range vc %d.%d.\n",
  1766. card->index, vpi, vci);
  1767. recycle_rx_buf(card, skb);
  1768. return;
  1769. }
  1770. vc = &(card->vcmap[vpi << card->vcibits | vci]);
  1771. if (!vc->rx) {
  1772. RXPRINTK("nicstar%d: SDU received on non-rx vc %d.%d.\n",
  1773. card->index, vpi, vci);
  1774. recycle_rx_buf(card, skb);
  1775. return;
  1776. }
  1777. vcc = vc->rx_vcc;
  1778. if (vcc->qos.aal == ATM_AAL0) {
  1779. struct sk_buff *sb;
  1780. unsigned char *cell;
  1781. int i;
  1782. cell = skb->data;
  1783. for (i = ns_rsqe_cellcount(rsqe); i; i--) {
  1784. sb = dev_alloc_skb(NS_SMSKBSIZE);
  1785. if (!sb) {
  1786. printk
  1787. ("nicstar%d: Can't allocate buffers for aal0.\n",
  1788. card->index);
  1789. atomic_add(i, &vcc->stats->rx_drop);
  1790. break;
  1791. }
  1792. if (!atm_charge(vcc, sb->truesize)) {
  1793. RXPRINTK
  1794. ("nicstar%d: atm_charge() dropped aal0 packets.\n",
  1795. card->index);
  1796. atomic_add(i - 1, &vcc->stats->rx_drop); /* already increased by 1 */
  1797. dev_kfree_skb_any(sb);
  1798. break;
  1799. }
  1800. /* Rebuild the header */
  1801. *((u32 *) sb->data) = le32_to_cpu(rsqe->word_1) << 4 |
  1802. (ns_rsqe_clp(rsqe) ? 0x00000001 : 0x00000000);
  1803. if (i == 1 && ns_rsqe_eopdu(rsqe))
  1804. *((u32 *) sb->data) |= 0x00000002;
  1805. skb_put(sb, NS_AAL0_HEADER);
  1806. memcpy(skb_tail_pointer(sb), cell, ATM_CELL_PAYLOAD);
  1807. skb_put(sb, ATM_CELL_PAYLOAD);
  1808. ATM_SKB(sb)->vcc = vcc;
  1809. __net_timestamp(sb);
  1810. vcc->push(vcc, sb);
  1811. atomic_inc(&vcc->stats->rx);
  1812. cell += ATM_CELL_PAYLOAD;
  1813. }
  1814. recycle_rx_buf(card, skb);
  1815. return;
  1816. }
  1817. /* To reach this point, the AAL layer can only be AAL5 */
  1818. if ((iovb = vc->rx_iov) == NULL) {
  1819. iovb = skb_dequeue(&(card->iovpool.queue));
  1820. if (iovb == NULL) { /* No buffers in the queue */
  1821. iovb = alloc_skb(NS_IOVBUFSIZE, GFP_ATOMIC);
  1822. if (iovb == NULL) {
  1823. printk("nicstar%d: Out of iovec buffers.\n",
  1824. card->index);
  1825. atomic_inc(&vcc->stats->rx_drop);
  1826. recycle_rx_buf(card, skb);
  1827. return;
  1828. }
  1829. NS_PRV_BUFTYPE(iovb) = BUF_NONE;
  1830. } else if (--card->iovpool.count < card->iovnr.min) {
  1831. struct sk_buff *new_iovb;
  1832. if ((new_iovb =
  1833. alloc_skb(NS_IOVBUFSIZE, GFP_ATOMIC)) != NULL) {
  1834. NS_PRV_BUFTYPE(iovb) = BUF_NONE;
  1835. skb_queue_tail(&card->iovpool.queue, new_iovb);
  1836. card->iovpool.count++;
  1837. }
  1838. }
  1839. vc->rx_iov = iovb;
  1840. NS_PRV_IOVCNT(iovb) = 0;
  1841. iovb->len = 0;
  1842. iovb->data = iovb->head;
  1843. skb_reset_tail_pointer(iovb);
  1844. /* IMPORTANT: a pointer to the sk_buff containing the small or large
  1845. buffer is stored as iovec base, NOT a pointer to the
  1846. small or large buffer itself. */
  1847. } else if (NS_PRV_IOVCNT(iovb) >= NS_MAX_IOVECS) {
  1848. printk("nicstar%d: received too big AAL5 SDU.\n", card->index);
  1849. atomic_inc(&vcc->stats->rx_err);
  1850. recycle_iovec_rx_bufs(card, (struct iovec *)iovb->data,
  1851. NS_MAX_IOVECS);
  1852. NS_PRV_IOVCNT(iovb) = 0;
  1853. iovb->len = 0;
  1854. iovb->data = iovb->head;
  1855. skb_reset_tail_pointer(iovb);
  1856. }
  1857. iov = &((struct iovec *)iovb->data)[NS_PRV_IOVCNT(iovb)++];
  1858. iov->iov_base = (void *)skb;
  1859. iov->iov_len = ns_rsqe_cellcount(rsqe) * 48;
  1860. iovb->len += iov->iov_len;
  1861. #ifdef EXTRA_DEBUG
  1862. if (NS_PRV_IOVCNT(iovb) == 1) {
  1863. if (NS_PRV_BUFTYPE(skb) != BUF_SM) {
  1864. printk
  1865. ("nicstar%d: Expected a small buffer, and this is not one.\n",
  1866. card->index);
  1867. which_list(card, skb);
  1868. atomic_inc(&vcc->stats->rx_err);
  1869. recycle_rx_buf(card, skb);
  1870. vc->rx_iov = NULL;
  1871. recycle_iov_buf(card, iovb);
  1872. return;
  1873. }
  1874. } else { /* NS_PRV_IOVCNT(iovb) >= 2 */
  1875. if (NS_PRV_BUFTYPE(skb) != BUF_LG) {
  1876. printk
  1877. ("nicstar%d: Expected a large buffer, and this is not one.\n",
  1878. card->index);
  1879. which_list(card, skb);
  1880. atomic_inc(&vcc->stats->rx_err);
  1881. recycle_iovec_rx_bufs(card, (struct iovec *)iovb->data,
  1882. NS_PRV_IOVCNT(iovb));
  1883. vc->rx_iov = NULL;
  1884. recycle_iov_buf(card, iovb);
  1885. return;
  1886. }
  1887. }
  1888. #endif /* EXTRA_DEBUG */
  1889. if (ns_rsqe_eopdu(rsqe)) {
  1890. /* This works correctly regardless of the endianness of the host */
  1891. unsigned char *L1L2 = (unsigned char *)
  1892. (skb->data + iov->iov_len - 6);
  1893. aal5_len = L1L2[0] << 8 | L1L2[1];
  1894. len = (aal5_len == 0x0000) ? 0x10000 : aal5_len;
  1895. if (ns_rsqe_crcerr(rsqe) ||
  1896. len + 8 > iovb->len || len + (47 + 8) < iovb->len) {
  1897. printk("nicstar%d: AAL5 CRC error", card->index);
  1898. if (len + 8 > iovb->len || len + (47 + 8) < iovb->len)
  1899. printk(" - PDU size mismatch.\n");
  1900. else
  1901. printk(".\n");
  1902. atomic_inc(&vcc->stats->rx_err);
  1903. recycle_iovec_rx_bufs(card, (struct iovec *)iovb->data,
  1904. NS_PRV_IOVCNT(iovb));
  1905. vc->rx_iov = NULL;
  1906. recycle_iov_buf(card, iovb);
  1907. return;
  1908. }
  1909. /* By this point we (hopefully) have a complete SDU without errors. */
  1910. if (NS_PRV_IOVCNT(iovb) == 1) { /* Just a small buffer */
  1911. /* skb points to a small buffer */
  1912. if (!atm_charge(vcc, skb->truesize)) {
  1913. push_rxbufs(card, skb);
  1914. atomic_inc(&vcc->stats->rx_drop);
  1915. } else {
  1916. skb_put(skb, len);
  1917. dequeue_sm_buf(card, skb);
  1918. ATM_SKB(skb)->vcc = vcc;
  1919. __net_timestamp(skb);
  1920. vcc->push(vcc, skb);
  1921. atomic_inc(&vcc->stats->rx);
  1922. }
  1923. } else if (NS_PRV_IOVCNT(iovb) == 2) { /* One small plus one large buffer */
  1924. struct sk_buff *sb;
  1925. sb = (struct sk_buff *)(iov - 1)->iov_base;
  1926. /* skb points to a large buffer */
  1927. if (len <= NS_SMBUFSIZE) {
  1928. if (!atm_charge(vcc, sb->truesize)) {
  1929. push_rxbufs(card, sb);
  1930. atomic_inc(&vcc->stats->rx_drop);
  1931. } else {
  1932. skb_put(sb, len);
  1933. dequeue_sm_buf(card, sb);
  1934. ATM_SKB(sb)->vcc = vcc;
  1935. __net_timestamp(sb);
  1936. vcc->push(vcc, sb);
  1937. atomic_inc(&vcc->stats->rx);
  1938. }
  1939. push_rxbufs(card, skb);
  1940. } else { /* len > NS_SMBUFSIZE, the usual case */
  1941. if (!atm_charge(vcc, skb->truesize)) {
  1942. push_rxbufs(card, skb);
  1943. atomic_inc(&vcc->stats->rx_drop);
  1944. } else {
  1945. dequeue_lg_buf(card, skb);
  1946. skb_push(skb, NS_SMBUFSIZE);
  1947. skb_copy_from_linear_data(sb, skb->data,
  1948. NS_SMBUFSIZE);
  1949. skb_put(skb, len - NS_SMBUFSIZE);
  1950. ATM_SKB(skb)->vcc = vcc;
  1951. __net_timestamp(skb);
  1952. vcc->push(vcc, skb);
  1953. atomic_inc(&vcc->stats->rx);
  1954. }
  1955. push_rxbufs(card, sb);
  1956. }
  1957. } else { /* Must push a huge buffer */
  1958. struct sk_buff *hb, *sb, *lb;
  1959. int remaining, tocopy;
  1960. int j;
  1961. hb = skb_dequeue(&(card->hbpool.queue));
  1962. if (hb == NULL) { /* No buffers in the queue */
  1963. hb = dev_alloc_skb(NS_HBUFSIZE);
  1964. if (hb == NULL) {
  1965. printk
  1966. ("nicstar%d: Out of huge buffers.\n",
  1967. card->index);
  1968. atomic_inc(&vcc->stats->rx_drop);
  1969. recycle_iovec_rx_bufs(card,
  1970. (struct iovec *)
  1971. iovb->data,
  1972. NS_PRV_IOVCNT(iovb));
  1973. vc->rx_iov = NULL;
  1974. recycle_iov_buf(card, iovb);
  1975. return;
  1976. } else if (card->hbpool.count < card->hbnr.min) {
  1977. struct sk_buff *new_hb;
  1978. if ((new_hb =
  1979. dev_alloc_skb(NS_HBUFSIZE)) !=
  1980. NULL) {
  1981. skb_queue_tail(&card->hbpool.
  1982. queue, new_hb);
  1983. card->hbpool.count++;
  1984. }
  1985. }
  1986. NS_PRV_BUFTYPE(hb) = BUF_NONE;
  1987. } else if (--card->hbpool.count < card->hbnr.min) {
  1988. struct sk_buff *new_hb;
  1989. if ((new_hb =
  1990. dev_alloc_skb(NS_HBUFSIZE)) != NULL) {
  1991. NS_PRV_BUFTYPE(new_hb) = BUF_NONE;
  1992. skb_queue_tail(&card->hbpool.queue,
  1993. new_hb);
  1994. card->hbpool.count++;
  1995. }
  1996. if (card->hbpool.count < card->hbnr.min) {
  1997. if ((new_hb =
  1998. dev_alloc_skb(NS_HBUFSIZE)) !=
  1999. NULL) {
  2000. NS_PRV_BUFTYPE(new_hb) =
  2001. BUF_NONE;
  2002. skb_queue_tail(&card->hbpool.
  2003. queue, new_hb);
  2004. card->hbpool.count++;
  2005. }
  2006. }
  2007. }
  2008. iov = (struct iovec *)iovb->data;
  2009. if (!atm_charge(vcc, hb->truesize)) {
  2010. recycle_iovec_rx_bufs(card, iov,
  2011. NS_PRV_IOVCNT(iovb));
  2012. if (card->hbpool.count < card->hbnr.max) {
  2013. skb_queue_tail(&card->hbpool.queue, hb);
  2014. card->hbpool.count++;
  2015. } else
  2016. dev_kfree_skb_any(hb);
  2017. atomic_inc(&vcc->stats->rx_drop);
  2018. } else {
  2019. /* Copy the small buffer to the huge buffer */
  2020. sb = (struct sk_buff *)iov->iov_base;
  2021. skb_copy_from_linear_data(sb, hb->data,
  2022. iov->iov_len);
  2023. skb_put(hb, iov->iov_len);
  2024. remaining = len - iov->iov_len;
  2025. iov++;
  2026. /* Free the small buffer */
  2027. push_rxbufs(card, sb);
  2028. /* Copy all large buffers to the huge buffer and free them */
  2029. for (j = 1; j < NS_PRV_IOVCNT(iovb); j++) {
  2030. lb = (struct sk_buff *)iov->iov_base;
  2031. tocopy =
  2032. min_t(int, remaining, iov->iov_len);
  2033. skb_copy_from_linear_data(lb,
  2034. skb_tail_pointer
  2035. (hb), tocopy);
  2036. skb_put(hb, tocopy);
  2037. iov++;
  2038. remaining -= tocopy;
  2039. push_rxbufs(card, lb);
  2040. }
  2041. #ifdef EXTRA_DEBUG
  2042. if (remaining != 0 || hb->len != len)
  2043. printk
  2044. ("nicstar%d: Huge buffer len mismatch.\n",
  2045. card->index);
  2046. #endif /* EXTRA_DEBUG */
  2047. ATM_SKB(hb)->vcc = vcc;
  2048. __net_timestamp(hb);
  2049. vcc->push(vcc, hb);
  2050. atomic_inc(&vcc->stats->rx);
  2051. }
  2052. }
  2053. vc->rx_iov = NULL;
  2054. recycle_iov_buf(card, iovb);
  2055. }
  2056. }
  2057. static void recycle_rx_buf(ns_dev * card, struct sk_buff *skb)
  2058. {
  2059. if (unlikely(NS_PRV_BUFTYPE(skb) == BUF_NONE)) {
  2060. printk("nicstar%d: What kind of rx buffer is this?\n",
  2061. card->index);
  2062. dev_kfree_skb_any(skb);
  2063. } else
  2064. push_rxbufs(card, skb);
  2065. }
  2066. static void recycle_iovec_rx_bufs(ns_dev * card, struct iovec *iov, int count)
  2067. {
  2068. while (count-- > 0)
  2069. recycle_rx_buf(card, (struct sk_buff *)(iov++)->iov_base);
  2070. }
  2071. static void recycle_iov_buf(ns_dev * card, struct sk_buff *iovb)
  2072. {
  2073. if (card->iovpool.count < card->iovnr.max) {
  2074. skb_queue_tail(&card->iovpool.queue, iovb);
  2075. card->iovpool.count++;
  2076. } else
  2077. dev_kfree_skb_any(iovb);
  2078. }
  2079. static void dequeue_sm_buf(ns_dev * card, struct sk_buff *sb)
  2080. {
  2081. skb_unlink(sb, &card->sbpool.queue);
  2082. if (card->sbfqc < card->sbnr.init) {
  2083. struct sk_buff *new_sb;
  2084. if ((new_sb = dev_alloc_skb(NS_SMSKBSIZE)) != NULL) {
  2085. NS_PRV_BUFTYPE(new_sb) = BUF_SM;
  2086. skb_queue_tail(&card->sbpool.queue, new_sb);
  2087. skb_reserve(new_sb, NS_AAL0_HEADER);
  2088. push_rxbufs(card, new_sb);
  2089. }
  2090. }
  2091. if (card->sbfqc < card->sbnr.init)
  2092. {
  2093. struct sk_buff *new_sb;
  2094. if ((new_sb = dev_alloc_skb(NS_SMSKBSIZE)) != NULL) {
  2095. NS_PRV_BUFTYPE(new_sb) = BUF_SM;
  2096. skb_queue_tail(&card->sbpool.queue, new_sb);
  2097. skb_reserve(new_sb, NS_AAL0_HEADER);
  2098. push_rxbufs(card, new_sb);
  2099. }
  2100. }
  2101. }
  2102. static void dequeue_lg_buf(ns_dev * card, struct sk_buff *lb)
  2103. {
  2104. skb_unlink(lb, &card->lbpool.queue);
  2105. if (card->lbfqc < card->lbnr.init) {
  2106. struct sk_buff *new_lb;
  2107. if ((new_lb = dev_alloc_skb(NS_LGSKBSIZE)) != NULL) {
  2108. NS_PRV_BUFTYPE(new_lb) = BUF_LG;
  2109. skb_queue_tail(&card->lbpool.queue, new_lb);
  2110. skb_reserve(new_lb, NS_SMBUFSIZE);
  2111. push_rxbufs(card, new_lb);
  2112. }
  2113. }
  2114. if (card->lbfqc < card->lbnr.init)
  2115. {
  2116. struct sk_buff *new_lb;
  2117. if ((new_lb = dev_alloc_skb(NS_LGSKBSIZE)) != NULL) {
  2118. NS_PRV_BUFTYPE(new_lb) = BUF_LG;
  2119. skb_queue_tail(&card->lbpool.queue, new_lb);
  2120. skb_reserve(new_lb, NS_SMBUFSIZE);
  2121. push_rxbufs(card, new_lb);
  2122. }
  2123. }
  2124. }
  2125. static int ns_proc_read(struct atm_dev *dev, loff_t * pos, char *page)
  2126. {
  2127. u32 stat;
  2128. ns_dev *card;
  2129. int left;
  2130. left = (int)*pos;
  2131. card = (ns_dev *) dev->dev_data;
  2132. stat = readl(card->membase + STAT);
  2133. if (!left--)
  2134. return sprintf(page, "Pool count min init max \n");
  2135. if (!left--)
  2136. return sprintf(page, "Small %5d %5d %5d %5d \n",
  2137. ns_stat_sfbqc_get(stat), card->sbnr.min,
  2138. card->sbnr.init, card->sbnr.max);
  2139. if (!left--)
  2140. return sprintf(page, "Large %5d %5d %5d %5d \n",
  2141. ns_stat_lfbqc_get(stat), card->lbnr.min,
  2142. card->lbnr.init, card->lbnr.max);
  2143. if (!left--)
  2144. return sprintf(page, "Huge %5d %5d %5d %5d \n",
  2145. card->hbpool.count, card->hbnr.min,
  2146. card->hbnr.init, card->hbnr.max);
  2147. if (!left--)
  2148. return sprintf(page, "Iovec %5d %5d %5d %5d \n",
  2149. card->iovpool.count, card->iovnr.min,
  2150. card->iovnr.init, card->iovnr.max);
  2151. if (!left--) {
  2152. int retval;
  2153. retval =
  2154. sprintf(page, "Interrupt counter: %u \n", card->intcnt);
  2155. card->intcnt = 0;
  2156. return retval;
  2157. }
  2158. #if 0
  2159. /* Dump 25.6 Mbps PHY registers */
  2160. /* Now there's a 25.6 Mbps PHY driver this code isn't needed. I left it
  2161. here just in case it's needed for debugging. */
  2162. if (card->max_pcr == ATM_25_PCR && !left--) {
  2163. u32 phy_regs[4];
  2164. u32 i;
  2165. for (i = 0; i < 4; i++) {
  2166. while (CMD_BUSY(card)) ;
  2167. writel(NS_CMD_READ_UTILITY | 0x00000200 | i,
  2168. card->membase + CMD);
  2169. while (CMD_BUSY(card)) ;
  2170. phy_regs[i] = readl(card->membase + DR0) & 0x000000FF;
  2171. }
  2172. return sprintf(page, "PHY regs: 0x%02X 0x%02X 0x%02X 0x%02X \n",
  2173. phy_regs[0], phy_regs[1], phy_regs[2],
  2174. phy_regs[3]);
  2175. }
  2176. #endif /* 0 - Dump 25.6 Mbps PHY registers */
  2177. #if 0
  2178. /* Dump TST */
  2179. if (left-- < NS_TST_NUM_ENTRIES) {
  2180. if (card->tste2vc[left + 1] == NULL)
  2181. return sprintf(page, "%5d - VBR/UBR \n", left + 1);
  2182. else
  2183. return sprintf(page, "%5d - %d %d \n", left + 1,
  2184. card->tste2vc[left + 1]->tx_vcc->vpi,
  2185. card->tste2vc[left + 1]->tx_vcc->vci);
  2186. }
  2187. #endif /* 0 */
  2188. return 0;
  2189. }
  2190. static int ns_ioctl(struct atm_dev *dev, unsigned int cmd, void __user * arg)
  2191. {
  2192. ns_dev *card;
  2193. pool_levels pl;
  2194. long btype;
  2195. unsigned long flags;
  2196. card = dev->dev_data;
  2197. switch (cmd) {
  2198. case NS_GETPSTAT:
  2199. if (get_user
  2200. (pl.buftype, &((pool_levels __user *) arg)->buftype))
  2201. return -EFAULT;
  2202. switch (pl.buftype) {
  2203. case NS_BUFTYPE_SMALL:
  2204. pl.count =
  2205. ns_stat_sfbqc_get(readl(card->membase + STAT));
  2206. pl.level.min = card->sbnr.min;
  2207. pl.level.init = card->sbnr.init;
  2208. pl.level.max = card->sbnr.max;
  2209. break;
  2210. case NS_BUFTYPE_LARGE:
  2211. pl.count =
  2212. ns_stat_lfbqc_get(readl(card->membase + STAT));
  2213. pl.level.min = card->lbnr.min;
  2214. pl.level.init = card->lbnr.init;
  2215. pl.level.max = card->lbnr.max;
  2216. break;
  2217. case NS_BUFTYPE_HUGE:
  2218. pl.count = card->hbpool.count;
  2219. pl.level.min = card->hbnr.min;
  2220. pl.level.init = card->hbnr.init;
  2221. pl.level.max = card->hbnr.max;
  2222. break;
  2223. case NS_BUFTYPE_IOVEC:
  2224. pl.count = card->iovpool.count;
  2225. pl.level.min = card->iovnr.min;
  2226. pl.level.init = card->iovnr.init;
  2227. pl.level.max = card->iovnr.max;
  2228. break;
  2229. default:
  2230. return -ENOIOCTLCMD;
  2231. }
  2232. if (!copy_to_user((pool_levels __user *) arg, &pl, sizeof(pl)))
  2233. return (sizeof(pl));
  2234. else
  2235. return -EFAULT;
  2236. case NS_SETBUFLEV:
  2237. if (!capable(CAP_NET_ADMIN))
  2238. return -EPERM;
  2239. if (copy_from_user(&pl, (pool_levels __user *) arg, sizeof(pl)))
  2240. return -EFAULT;
  2241. if (pl.level.min >= pl.level.init
  2242. || pl.level.init >= pl.level.max)
  2243. return -EINVAL;
  2244. if (pl.level.min == 0)
  2245. return -EINVAL;
  2246. switch (pl.buftype) {
  2247. case NS_BUFTYPE_SMALL:
  2248. if (pl.level.max > TOP_SB)
  2249. return -EINVAL;
  2250. card->sbnr.min = pl.level.min;
  2251. card->sbnr.init = pl.level.init;
  2252. card->sbnr.max = pl.level.max;
  2253. break;
  2254. case NS_BUFTYPE_LARGE:
  2255. if (pl.level.max > TOP_LB)
  2256. return -EINVAL;
  2257. card->lbnr.min = pl.level.min;
  2258. card->lbnr.init = pl.level.init;
  2259. card->lbnr.max = pl.level.max;
  2260. break;
  2261. case NS_BUFTYPE_HUGE:
  2262. if (pl.level.max > TOP_HB)
  2263. return -EINVAL;
  2264. card->hbnr.min = pl.level.min;
  2265. card->hbnr.init = pl.level.init;
  2266. card->hbnr.max = pl.level.max;
  2267. break;
  2268. case NS_BUFTYPE_IOVEC:
  2269. if (pl.level.max > TOP_IOVB)
  2270. return -EINVAL;
  2271. card->iovnr.min = pl.level.min;
  2272. card->iovnr.init = pl.level.init;
  2273. card->iovnr.max = pl.level.max;
  2274. break;
  2275. default:
  2276. return -EINVAL;
  2277. }
  2278. return 0;
  2279. case NS_ADJBUFLEV:
  2280. if (!capable(CAP_NET_ADMIN))
  2281. return -EPERM;
  2282. btype = (long)arg; /* a long is the same size as a pointer or bigger */
  2283. switch (btype) {
  2284. case NS_BUFTYPE_SMALL:
  2285. while (card->sbfqc < card->sbnr.init) {
  2286. struct sk_buff *sb;
  2287. sb = __dev_alloc_skb(NS_SMSKBSIZE, GFP_KERNEL);
  2288. if (sb == NULL)
  2289. return -ENOMEM;
  2290. NS_PRV_BUFTYPE(sb) = BUF_SM;
  2291. skb_queue_tail(&card->sbpool.queue, sb);
  2292. skb_reserve(sb, NS_AAL0_HEADER);
  2293. push_rxbufs(card, sb);
  2294. }
  2295. break;
  2296. case NS_BUFTYPE_LARGE:
  2297. while (card->lbfqc < card->lbnr.init) {
  2298. struct sk_buff *lb;
  2299. lb = __dev_alloc_skb(NS_LGSKBSIZE, GFP_KERNEL);
  2300. if (lb == NULL)
  2301. return -ENOMEM;
  2302. NS_PRV_BUFTYPE(lb) = BUF_LG;
  2303. skb_queue_tail(&card->lbpool.queue, lb);
  2304. skb_reserve(lb, NS_SMBUFSIZE);
  2305. push_rxbufs(card, lb);
  2306. }
  2307. break;
  2308. case NS_BUFTYPE_HUGE:
  2309. while (card->hbpool.count > card->hbnr.init) {
  2310. struct sk_buff *hb;
  2311. spin_lock_irqsave(&card->int_lock, flags);
  2312. hb = skb_dequeue(&card->hbpool.queue);
  2313. card->hbpool.count--;
  2314. spin_unlock_irqrestore(&card->int_lock, flags);
  2315. if (hb == NULL)
  2316. printk
  2317. ("nicstar%d: huge buffer count inconsistent.\n",
  2318. card->index);
  2319. else
  2320. dev_kfree_skb_any(hb);
  2321. }
  2322. while (card->hbpool.count < card->hbnr.init) {
  2323. struct sk_buff *hb;
  2324. hb = __dev_alloc_skb(NS_HBUFSIZE, GFP_KERNEL);
  2325. if (hb == NULL)
  2326. return -ENOMEM;
  2327. NS_PRV_BUFTYPE(hb) = BUF_NONE;
  2328. spin_lock_irqsave(&card->int_lock, flags);
  2329. skb_queue_tail(&card->hbpool.queue, hb);
  2330. card->hbpool.count++;
  2331. spin_unlock_irqrestore(&card->int_lock, flags);
  2332. }
  2333. break;
  2334. case NS_BUFTYPE_IOVEC:
  2335. while (card->iovpool.count > card->iovnr.init) {
  2336. struct sk_buff *iovb;
  2337. spin_lock_irqsave(&card->int_lock, flags);
  2338. iovb = skb_dequeue(&card->iovpool.queue);
  2339. card->iovpool.count--;
  2340. spin_unlock_irqrestore(&card->int_lock, flags);
  2341. if (iovb == NULL)
  2342. printk
  2343. ("nicstar%d: iovec buffer count inconsistent.\n",
  2344. card->index);
  2345. else
  2346. dev_kfree_skb_any(iovb);
  2347. }
  2348. while (card->iovpool.count < card->iovnr.init) {
  2349. struct sk_buff *iovb;
  2350. iovb = alloc_skb(NS_IOVBUFSIZE, GFP_KERNEL);
  2351. if (iovb == NULL)
  2352. return -ENOMEM;
  2353. NS_PRV_BUFTYPE(iovb) = BUF_NONE;
  2354. spin_lock_irqsave(&card->int_lock, flags);
  2355. skb_queue_tail(&card->iovpool.queue, iovb);
  2356. card->iovpool.count++;
  2357. spin_unlock_irqrestore(&card->int_lock, flags);
  2358. }
  2359. break;
  2360. default:
  2361. return -EINVAL;
  2362. }
  2363. return 0;
  2364. default:
  2365. if (dev->phy && dev->phy->ioctl) {
  2366. return dev->phy->ioctl(dev, cmd, arg);
  2367. } else {
  2368. printk("nicstar%d: %s == NULL \n", card->index,
  2369. dev->phy ? "dev->phy->ioctl" : "dev->phy");
  2370. return -ENOIOCTLCMD;
  2371. }
  2372. }
  2373. }
  2374. #ifdef EXTRA_DEBUG
  2375. static void which_list(ns_dev * card, struct sk_buff *skb)
  2376. {
  2377. printk("skb buf_type: 0x%08x\n", NS_PRV_BUFTYPE(skb));
  2378. }
  2379. #endif /* EXTRA_DEBUG */
  2380. static void ns_poll(struct timer_list *unused)
  2381. {
  2382. int i;
  2383. ns_dev *card;
  2384. unsigned long flags;
  2385. u32 stat_r, stat_w;
  2386. PRINTK("nicstar: Entering ns_poll().\n");
  2387. for (i = 0; i < num_cards; i++) {
  2388. card = cards[i];
  2389. if (!spin_trylock_irqsave(&card->int_lock, flags)) {
  2390. /* Probably it isn't worth spinning */
  2391. continue;
  2392. }
  2393. stat_w = 0;
  2394. stat_r = readl(card->membase + STAT);
  2395. if (stat_r & NS_STAT_TSIF)
  2396. stat_w |= NS_STAT_TSIF;
  2397. if (stat_r & NS_STAT_EOPDU)
  2398. stat_w |= NS_STAT_EOPDU;
  2399. process_tsq(card);
  2400. process_rsq(card);
  2401. writel(stat_w, card->membase + STAT);
  2402. spin_unlock_irqrestore(&card->int_lock, flags);
  2403. }
  2404. mod_timer(&ns_timer, jiffies + NS_POLL_PERIOD);
  2405. PRINTK("nicstar: Leaving ns_poll().\n");
  2406. }
  2407. static void ns_phy_put(struct atm_dev *dev, unsigned char value,
  2408. unsigned long addr)
  2409. {
  2410. ns_dev *card;
  2411. unsigned long flags;
  2412. card = dev->dev_data;
  2413. spin_lock_irqsave(&card->res_lock, flags);
  2414. while (CMD_BUSY(card)) ;
  2415. writel((u32) value, card->membase + DR0);
  2416. writel(NS_CMD_WRITE_UTILITY | 0x00000200 | (addr & 0x000000FF),
  2417. card->membase + CMD);
  2418. spin_unlock_irqrestore(&card->res_lock, flags);
  2419. }
  2420. static unsigned char ns_phy_get(struct atm_dev *dev, unsigned long addr)
  2421. {
  2422. ns_dev *card;
  2423. unsigned long flags;
  2424. u32 data;
  2425. card = dev->dev_data;
  2426. spin_lock_irqsave(&card->res_lock, flags);
  2427. while (CMD_BUSY(card)) ;
  2428. writel(NS_CMD_READ_UTILITY | 0x00000200 | (addr & 0x000000FF),
  2429. card->membase + CMD);
  2430. while (CMD_BUSY(card)) ;
  2431. data = readl(card->membase + DR0) & 0x000000FF;
  2432. spin_unlock_irqrestore(&card->res_lock, flags);
  2433. return (unsigned char)data;
  2434. }
  2435. module_init(nicstar_init);
  2436. module_exit(nicstar_cleanup);