midway.h 7.6 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /* drivers/atm/midway.h - Efficient Networks Midway (SAR) description */
  3. /* Written 1995-1999 by Werner Almesberger, EPFL LRC/ICA */
  4. #ifndef DRIVERS_ATM_MIDWAY_H
  5. #define DRIVERS_ATM_MIDWAY_H
  6. #define NR_VCI 1024 /* number of VCIs */
  7. #define NR_VCI_LD 10 /* log2(NR_VCI) */
  8. #define NR_DMA_RX 512 /* RX DMA queue entries */
  9. #define NR_DMA_TX 512 /* TX DMA queue entries */
  10. #define NR_SERVICE NR_VCI /* service list size */
  11. #define NR_CHAN 8 /* number of TX channels */
  12. #define TS_CLOCK 25000000 /* traffic shaper clock (cell/sec) */
  13. #define MAP_MAX_SIZE 0x00400000 /* memory window for max config */
  14. #define EPROM_SIZE 0x00010000
  15. #define MEM_VALID 0xffc00000 /* mask base address with this */
  16. #define PHY_BASE 0x00020000 /* offset of PHY register are */
  17. #define REG_BASE 0x00040000 /* offset of Midway register area */
  18. #define RAM_BASE 0x00200000 /* offset of RAM area */
  19. #define RAM_INCREMENT 0x00020000 /* probe for RAM every 128kB */
  20. #define MID_VCI_BASE RAM_BASE
  21. #define MID_DMA_RX_BASE (MID_VCI_BASE+NR_VCI*16)
  22. #define MID_DMA_TX_BASE (MID_DMA_RX_BASE+NR_DMA_RX*8)
  23. #define MID_SERVICE_BASE (MID_DMA_TX_BASE+NR_DMA_TX*8)
  24. #define MID_FREE_BASE (MID_SERVICE_BASE+NR_SERVICE*4)
  25. #define MAC_LEN 6 /* atm.h */
  26. #define MID_MIN_BUF_SIZE (1024) /* 1 kB is minimum */
  27. #define MID_MAX_BUF_SIZE (128*1024) /* 128 kB is maximum */
  28. #define RX_DESCR_SIZE 1 /* RX PDU descr is 1 longword */
  29. #define TX_DESCR_SIZE 2 /* TX PDU descr is 2 longwords */
  30. #define AAL5_TRAILER (ATM_AAL5_TRAILER/4) /* AAL5 trailer is 2 longwords */
  31. #define TX_GAP 8 /* TX buffer gap (words) */
  32. /*
  33. * Midway Reset/ID
  34. *
  35. * All values read-only. Writing to this register resets Midway chip.
  36. */
  37. #define MID_RES_ID_MCON 0x00 /* Midway Reset/ID */
  38. #define MID_ID 0xf0000000 /* Midway version */
  39. #define MID_SHIFT 24
  40. #define MID_MOTHER_ID 0x00000700 /* mother board id */
  41. #define MID_MOTHER_SHIFT 8
  42. #define MID_CON_TI 0x00000080 /* 0: normal ctrl; 1: SABRE */
  43. #define MID_CON_SUNI 0x00000040 /* 0: UTOPIA; 1: SUNI */
  44. #define MID_CON_V6 0x00000020 /* 0: non-pipel UTOPIA (required iff
  45. !CON_SUNI; 1: UTOPIA */
  46. #define DAUGHTER_ID 0x0000001f /* daughter board id */
  47. /*
  48. * Interrupt Status Acknowledge, Interrupt Status & Interrupt Enable
  49. */
  50. #define MID_ISA 0x01 /* Interrupt Status Acknowledge */
  51. #define MID_IS 0x02 /* Interrupt Status */
  52. #define MID_IE 0x03 /* Interrupt Enable */
  53. #define MID_TX_COMPLETE_7 0x00010000 /* channel N completed a PDU */
  54. #define MID_TX_COMPLETE_6 0x00008000 /* transmission */
  55. #define MID_TX_COMPLETE_5 0x00004000
  56. #define MID_TX_COMPLETE_4 0x00002000
  57. #define MID_TX_COMPLETE_3 0x00001000
  58. #define MID_TX_COMPLETE_2 0x00000800
  59. #define MID_TX_COMPLETE_1 0x00000400
  60. #define MID_TX_COMPLETE_0 0x00000200
  61. #define MID_TX_COMPLETE 0x0001fe00 /* any TX */
  62. #define MID_TX_DMA_OVFL 0x00000100 /* DMA to adapter overflow */
  63. #define MID_TX_IDENT_MISM 0x00000080 /* TX: ident mismatch => halted */
  64. #define MID_DMA_LERR_ACK 0x00000040 /* LERR - SBus ? */
  65. #define MID_DMA_ERR_ACK 0x00000020 /* DMA error */
  66. #define MID_RX_DMA_COMPLETE 0x00000010 /* DMA to host done */
  67. #define MID_TX_DMA_COMPLETE 0x00000008 /* DMA from host done */
  68. #define MID_SERVICE 0x00000004 /* something in service list */
  69. #define MID_SUNI_INT 0x00000002 /* interrupt from SUNI */
  70. #define MID_STAT_OVFL 0x00000001 /* statistics overflow */
  71. /*
  72. * Master Control/Status
  73. */
  74. #define MID_MC_S 0x04
  75. #define MID_INT_SELECT 0x000001C0 /* Interrupt level (000: off) */
  76. #define MID_INT_SEL_SHIFT 6
  77. #define MID_TX_LOCK_MODE 0x00000020 /* 0: streaming; 1: TX ovfl->lock */
  78. #define MID_DMA_ENABLE 0x00000010 /* R: 0: disable; 1: enable
  79. W: 0: no change; 1: enable */
  80. #define MID_TX_ENABLE 0x00000008 /* R: 0: TX disabled; 1: enabled
  81. W: 0: no change; 1: enable */
  82. #define MID_RX_ENABLE 0x00000004 /* like TX */
  83. #define MID_WAIT_1MS 0x00000002 /* R: 0: timer not running; 1: running
  84. W: 0: no change; 1: no interrupts
  85. for 1 ms */
  86. #define MID_WAIT_500US 0x00000001 /* like WAIT_1MS, but 0.5 ms */
  87. /*
  88. * Statistics
  89. *
  90. * Cleared when reading.
  91. */
  92. #define MID_STAT 0x05
  93. #define MID_VCI_TRASH 0xFFFF0000 /* trashed cells because of VCI mode */
  94. #define MID_VCI_TRASH_SHIFT 16
  95. #define MID_OVFL_TRASH 0x0000FFFF /* trashed cells because of overflow */
  96. /*
  97. * Address registers
  98. */
  99. #define MID_SERV_WRITE 0x06 /* free pos in service area (R, 10 bits) */
  100. #define MID_DMA_ADDR 0x07 /* virtual DMA address (R, 32 bits) */
  101. #define MID_DMA_WR_RX 0x08 /* (RW, 9 bits) */
  102. #define MID_DMA_RD_RX 0x09
  103. #define MID_DMA_WR_TX 0x0A
  104. #define MID_DMA_RD_TX 0x0B
  105. /*
  106. * Transmit Place Registers (0x10+4*channel)
  107. */
  108. #define MID_TX_PLACE(c) (0x10+4*(c))
  109. #define MID_SIZE 0x00003800 /* size, N*256 x 32 bit */
  110. #define MID_SIZE_SHIFT 11
  111. #define MID_LOCATION 0x000007FF /* location in adapter memory (word) */
  112. #define MID_LOC_SKIP 8 /* 8 bits of location are always zero
  113. (applies to all uses of location) */
  114. /*
  115. * Transmit ReadPtr Registers (0x11+4*channel)
  116. */
  117. #define MID_TX_RDPTR(c) (0x11+4*(c))
  118. #define MID_READ_PTR 0x00007FFF /* next word for PHY */
  119. /*
  120. * Transmit DescrStart Registers (0x12+4*channel)
  121. */
  122. #define MID_TX_DESCRSTART(c) (0x12+4*(c))
  123. #define MID_DESCR_START 0x00007FFF /* seg buffer being DMAed */
  124. #define ENI155_MAGIC 0xa54b872d
  125. struct midway_eprom {
  126. unsigned char mac[MAC_LEN],inv_mac[MAC_LEN];
  127. unsigned char pad[36];
  128. u32 serial,inv_serial;
  129. u32 magic,inv_magic;
  130. };
  131. /*
  132. * VCI table entry
  133. */
  134. #define MID_VCI_IN_SERVICE 0x00000001 /* set if VCI is currently in
  135. service list */
  136. #define MID_VCI_SIZE 0x00038000 /* reassembly buffer size,
  137. 2*<size> kB */
  138. #define MID_VCI_SIZE_SHIFT 15
  139. #define MID_VCI_LOCATION 0x1ffc0000 /* buffer location */
  140. #define MID_VCI_LOCATION_SHIFT 18
  141. #define MID_VCI_PTI_MODE 0x20000000 /* 0: trash, 1: preserve */
  142. #define MID_VCI_MODE 0xc0000000
  143. #define MID_VCI_MODE_SHIFT 30
  144. #define MID_VCI_READ 0x00007fff
  145. #define MID_VCI_READ_SHIFT 0
  146. #define MID_VCI_DESCR 0x7fff0000
  147. #define MID_VCI_DESCR_SHIFT 16
  148. #define MID_VCI_COUNT 0x000007ff
  149. #define MID_VCI_COUNT_SHIFT 0
  150. #define MID_VCI_STATE 0x0000c000
  151. #define MID_VCI_STATE_SHIFT 14
  152. #define MID_VCI_WRITE 0x7fff0000
  153. #define MID_VCI_WRITE_SHIFT 16
  154. #define MID_MODE_TRASH 0
  155. #define MID_MODE_RAW 1
  156. #define MID_MODE_AAL5 2
  157. /*
  158. * Reassembly buffer descriptor
  159. */
  160. #define MID_RED_COUNT 0x000007ff
  161. #define MID_RED_CRC_ERR 0x00000800
  162. #define MID_RED_T 0x00001000
  163. #define MID_RED_CE 0x00010000
  164. #define MID_RED_CLP 0x01000000
  165. #define MID_RED_IDEN 0xfe000000
  166. #define MID_RED_SHIFT 25
  167. #define MID_RED_RX_ID 0x1b /* constant identifier */
  168. /*
  169. * Segmentation buffer descriptor
  170. */
  171. #define MID_SEG_COUNT MID_RED_COUNT
  172. #define MID_SEG_RATE 0x01f80000
  173. #define MID_SEG_RATE_SHIFT 19
  174. #define MID_SEG_PR 0x06000000
  175. #define MID_SEG_PR_SHIFT 25
  176. #define MID_SEG_AAL5 0x08000000
  177. #define MID_SEG_ID 0xf0000000
  178. #define MID_SEG_ID_SHIFT 28
  179. #define MID_SEG_MAX_RATE 63
  180. #define MID_SEG_CLP 0x00000001
  181. #define MID_SEG_PTI 0x0000000e
  182. #define MID_SEG_PTI_SHIFT 1
  183. #define MID_SEG_VCI 0x00003ff0
  184. #define MID_SEG_VCI_SHIFT 4
  185. #define MID_SEG_TX_ID 0xb /* constant identifier */
  186. /*
  187. * DMA entry
  188. */
  189. #define MID_DMA_COUNT 0xffff0000
  190. #define MID_DMA_COUNT_SHIFT 16
  191. #define MID_DMA_END 0x00000020
  192. #define MID_DMA_TYPE 0x0000000f
  193. #define MID_DT_JK 0x3
  194. #define MID_DT_WORD 0x0
  195. #define MID_DT_2W 0x7
  196. #define MID_DT_4W 0x4
  197. #define MID_DT_8W 0x5
  198. #define MID_DT_16W 0x6
  199. #define MID_DT_2WM 0xf
  200. #define MID_DT_4WM 0xc
  201. #define MID_DT_8WM 0xd
  202. #define MID_DT_16WM 0xe
  203. /* only for RX*/
  204. #define MID_DMA_VCI 0x0000ffc0
  205. #define MID_DMA_VCI_SHIFT 6
  206. /* only for TX */
  207. #define MID_DMA_CHAN 0x000001c0
  208. #define MID_DMA_CHAN_SHIFT 6
  209. #define MID_DT_BYTE 0x1
  210. #define MID_DT_HWORD 0x2
  211. #endif