idt77252.c 89 KB

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  1. /*******************************************************************
  2. *
  3. * Copyright (c) 2000 ATecoM GmbH
  4. *
  5. * The author may be reached at ecd@atecom.com.
  6. *
  7. * This program is free software; you can redistribute it and/or modify it
  8. * under the terms of the GNU General Public License as published by the
  9. * Free Software Foundation; either version 2 of the License, or (at your
  10. * option) any later version.
  11. *
  12. * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  13. * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  14. * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
  15. * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  16. * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  17. * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
  18. * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  19. * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  20. * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  21. * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  22. *
  23. * You should have received a copy of the GNU General Public License along
  24. * with this program; if not, write to the Free Software Foundation, Inc.,
  25. * 675 Mass Ave, Cambridge, MA 02139, USA.
  26. *
  27. *******************************************************************/
  28. #include <linux/module.h>
  29. #include <linux/pci.h>
  30. #include <linux/poison.h>
  31. #include <linux/skbuff.h>
  32. #include <linux/kernel.h>
  33. #include <linux/vmalloc.h>
  34. #include <linux/netdevice.h>
  35. #include <linux/atmdev.h>
  36. #include <linux/atm.h>
  37. #include <linux/delay.h>
  38. #include <linux/init.h>
  39. #include <linux/interrupt.h>
  40. #include <linux/bitops.h>
  41. #include <linux/wait.h>
  42. #include <linux/jiffies.h>
  43. #include <linux/mutex.h>
  44. #include <linux/slab.h>
  45. #include <asm/io.h>
  46. #include <linux/uaccess.h>
  47. #include <linux/atomic.h>
  48. #include <asm/byteorder.h>
  49. #ifdef CONFIG_ATM_IDT77252_USE_SUNI
  50. #include "suni.h"
  51. #endif /* CONFIG_ATM_IDT77252_USE_SUNI */
  52. #include "idt77252.h"
  53. #include "idt77252_tables.h"
  54. static unsigned int vpibits = 1;
  55. #define ATM_IDT77252_SEND_IDLE 1
  56. /*
  57. * Debug HACKs.
  58. */
  59. #define DEBUG_MODULE 1
  60. #undef HAVE_EEPROM /* does not work, yet. */
  61. #ifdef CONFIG_ATM_IDT77252_DEBUG
  62. static unsigned long debug = DBG_GENERAL;
  63. #endif
  64. #define SAR_RX_DELAY (SAR_CFG_RXINT_NODELAY)
  65. /*
  66. * SCQ Handling.
  67. */
  68. static struct scq_info *alloc_scq(struct idt77252_dev *, int);
  69. static void free_scq(struct idt77252_dev *, struct scq_info *);
  70. static int queue_skb(struct idt77252_dev *, struct vc_map *,
  71. struct sk_buff *, int oam);
  72. static void drain_scq(struct idt77252_dev *, struct vc_map *);
  73. static unsigned long get_free_scd(struct idt77252_dev *, struct vc_map *);
  74. static void fill_scd(struct idt77252_dev *, struct scq_info *, int);
  75. /*
  76. * FBQ Handling.
  77. */
  78. static int push_rx_skb(struct idt77252_dev *,
  79. struct sk_buff *, int queue);
  80. static void recycle_rx_skb(struct idt77252_dev *, struct sk_buff *);
  81. static void flush_rx_pool(struct idt77252_dev *, struct rx_pool *);
  82. static void recycle_rx_pool_skb(struct idt77252_dev *,
  83. struct rx_pool *);
  84. static void add_rx_skb(struct idt77252_dev *, int queue,
  85. unsigned int size, unsigned int count);
  86. /*
  87. * RSQ Handling.
  88. */
  89. static int init_rsq(struct idt77252_dev *);
  90. static void deinit_rsq(struct idt77252_dev *);
  91. static void idt77252_rx(struct idt77252_dev *);
  92. /*
  93. * TSQ handling.
  94. */
  95. static int init_tsq(struct idt77252_dev *);
  96. static void deinit_tsq(struct idt77252_dev *);
  97. static void idt77252_tx(struct idt77252_dev *);
  98. /*
  99. * ATM Interface.
  100. */
  101. static void idt77252_dev_close(struct atm_dev *dev);
  102. static int idt77252_open(struct atm_vcc *vcc);
  103. static void idt77252_close(struct atm_vcc *vcc);
  104. static int idt77252_send(struct atm_vcc *vcc, struct sk_buff *skb);
  105. static int idt77252_send_oam(struct atm_vcc *vcc, void *cell,
  106. int flags);
  107. static void idt77252_phy_put(struct atm_dev *dev, unsigned char value,
  108. unsigned long addr);
  109. static unsigned char idt77252_phy_get(struct atm_dev *dev, unsigned long addr);
  110. static int idt77252_change_qos(struct atm_vcc *vcc, struct atm_qos *qos,
  111. int flags);
  112. static int idt77252_proc_read(struct atm_dev *dev, loff_t * pos,
  113. char *page);
  114. static void idt77252_softint(struct work_struct *work);
  115. static const struct atmdev_ops idt77252_ops =
  116. {
  117. .dev_close = idt77252_dev_close,
  118. .open = idt77252_open,
  119. .close = idt77252_close,
  120. .send = idt77252_send,
  121. .send_oam = idt77252_send_oam,
  122. .phy_put = idt77252_phy_put,
  123. .phy_get = idt77252_phy_get,
  124. .change_qos = idt77252_change_qos,
  125. .proc_read = idt77252_proc_read,
  126. .owner = THIS_MODULE
  127. };
  128. static struct idt77252_dev *idt77252_chain = NULL;
  129. static unsigned int idt77252_sram_write_errors = 0;
  130. /*****************************************************************************/
  131. /* */
  132. /* I/O and Utility Bus */
  133. /* */
  134. /*****************************************************************************/
  135. static void
  136. waitfor_idle(struct idt77252_dev *card)
  137. {
  138. u32 stat;
  139. stat = readl(SAR_REG_STAT);
  140. while (stat & SAR_STAT_CMDBZ)
  141. stat = readl(SAR_REG_STAT);
  142. }
  143. static u32
  144. read_sram(struct idt77252_dev *card, unsigned long addr)
  145. {
  146. unsigned long flags;
  147. u32 value;
  148. spin_lock_irqsave(&card->cmd_lock, flags);
  149. writel(SAR_CMD_READ_SRAM | (addr << 2), SAR_REG_CMD);
  150. waitfor_idle(card);
  151. value = readl(SAR_REG_DR0);
  152. spin_unlock_irqrestore(&card->cmd_lock, flags);
  153. return value;
  154. }
  155. static void
  156. write_sram(struct idt77252_dev *card, unsigned long addr, u32 value)
  157. {
  158. unsigned long flags;
  159. if ((idt77252_sram_write_errors == 0) &&
  160. (((addr > card->tst[0] + card->tst_size - 2) &&
  161. (addr < card->tst[0] + card->tst_size)) ||
  162. ((addr > card->tst[1] + card->tst_size - 2) &&
  163. (addr < card->tst[1] + card->tst_size)))) {
  164. printk("%s: ERROR: TST JMP section at %08lx written: %08x\n",
  165. card->name, addr, value);
  166. }
  167. spin_lock_irqsave(&card->cmd_lock, flags);
  168. writel(value, SAR_REG_DR0);
  169. writel(SAR_CMD_WRITE_SRAM | (addr << 2), SAR_REG_CMD);
  170. waitfor_idle(card);
  171. spin_unlock_irqrestore(&card->cmd_lock, flags);
  172. }
  173. static u8
  174. read_utility(void *dev, unsigned long ubus_addr)
  175. {
  176. struct idt77252_dev *card = dev;
  177. unsigned long flags;
  178. u8 value;
  179. if (!card) {
  180. printk("Error: No such device.\n");
  181. return -1;
  182. }
  183. spin_lock_irqsave(&card->cmd_lock, flags);
  184. writel(SAR_CMD_READ_UTILITY + ubus_addr, SAR_REG_CMD);
  185. waitfor_idle(card);
  186. value = readl(SAR_REG_DR0);
  187. spin_unlock_irqrestore(&card->cmd_lock, flags);
  188. return value;
  189. }
  190. static void
  191. write_utility(void *dev, unsigned long ubus_addr, u8 value)
  192. {
  193. struct idt77252_dev *card = dev;
  194. unsigned long flags;
  195. if (!card) {
  196. printk("Error: No such device.\n");
  197. return;
  198. }
  199. spin_lock_irqsave(&card->cmd_lock, flags);
  200. writel((u32) value, SAR_REG_DR0);
  201. writel(SAR_CMD_WRITE_UTILITY + ubus_addr, SAR_REG_CMD);
  202. waitfor_idle(card);
  203. spin_unlock_irqrestore(&card->cmd_lock, flags);
  204. }
  205. #ifdef HAVE_EEPROM
  206. static u32 rdsrtab[] =
  207. {
  208. SAR_GP_EECS | SAR_GP_EESCLK,
  209. 0,
  210. SAR_GP_EESCLK, /* 0 */
  211. 0,
  212. SAR_GP_EESCLK, /* 0 */
  213. 0,
  214. SAR_GP_EESCLK, /* 0 */
  215. 0,
  216. SAR_GP_EESCLK, /* 0 */
  217. 0,
  218. SAR_GP_EESCLK, /* 0 */
  219. SAR_GP_EEDO,
  220. SAR_GP_EESCLK | SAR_GP_EEDO, /* 1 */
  221. 0,
  222. SAR_GP_EESCLK, /* 0 */
  223. SAR_GP_EEDO,
  224. SAR_GP_EESCLK | SAR_GP_EEDO /* 1 */
  225. };
  226. static u32 wrentab[] =
  227. {
  228. SAR_GP_EECS | SAR_GP_EESCLK,
  229. 0,
  230. SAR_GP_EESCLK, /* 0 */
  231. 0,
  232. SAR_GP_EESCLK, /* 0 */
  233. 0,
  234. SAR_GP_EESCLK, /* 0 */
  235. 0,
  236. SAR_GP_EESCLK, /* 0 */
  237. SAR_GP_EEDO,
  238. SAR_GP_EESCLK | SAR_GP_EEDO, /* 1 */
  239. SAR_GP_EEDO,
  240. SAR_GP_EESCLK | SAR_GP_EEDO, /* 1 */
  241. 0,
  242. SAR_GP_EESCLK, /* 0 */
  243. 0,
  244. SAR_GP_EESCLK /* 0 */
  245. };
  246. static u32 rdtab[] =
  247. {
  248. SAR_GP_EECS | SAR_GP_EESCLK,
  249. 0,
  250. SAR_GP_EESCLK, /* 0 */
  251. 0,
  252. SAR_GP_EESCLK, /* 0 */
  253. 0,
  254. SAR_GP_EESCLK, /* 0 */
  255. 0,
  256. SAR_GP_EESCLK, /* 0 */
  257. 0,
  258. SAR_GP_EESCLK, /* 0 */
  259. 0,
  260. SAR_GP_EESCLK, /* 0 */
  261. SAR_GP_EEDO,
  262. SAR_GP_EESCLK | SAR_GP_EEDO, /* 1 */
  263. SAR_GP_EEDO,
  264. SAR_GP_EESCLK | SAR_GP_EEDO /* 1 */
  265. };
  266. static u32 wrtab[] =
  267. {
  268. SAR_GP_EECS | SAR_GP_EESCLK,
  269. 0,
  270. SAR_GP_EESCLK, /* 0 */
  271. 0,
  272. SAR_GP_EESCLK, /* 0 */
  273. 0,
  274. SAR_GP_EESCLK, /* 0 */
  275. 0,
  276. SAR_GP_EESCLK, /* 0 */
  277. 0,
  278. SAR_GP_EESCLK, /* 0 */
  279. 0,
  280. SAR_GP_EESCLK, /* 0 */
  281. SAR_GP_EEDO,
  282. SAR_GP_EESCLK | SAR_GP_EEDO, /* 1 */
  283. 0,
  284. SAR_GP_EESCLK /* 0 */
  285. };
  286. static u32 clktab[] =
  287. {
  288. 0,
  289. SAR_GP_EESCLK,
  290. 0,
  291. SAR_GP_EESCLK,
  292. 0,
  293. SAR_GP_EESCLK,
  294. 0,
  295. SAR_GP_EESCLK,
  296. 0,
  297. SAR_GP_EESCLK,
  298. 0,
  299. SAR_GP_EESCLK,
  300. 0,
  301. SAR_GP_EESCLK,
  302. 0,
  303. SAR_GP_EESCLK,
  304. 0
  305. };
  306. static u32
  307. idt77252_read_gp(struct idt77252_dev *card)
  308. {
  309. u32 gp;
  310. gp = readl(SAR_REG_GP);
  311. #if 0
  312. printk("RD: %s\n", gp & SAR_GP_EEDI ? "1" : "0");
  313. #endif
  314. return gp;
  315. }
  316. static void
  317. idt77252_write_gp(struct idt77252_dev *card, u32 value)
  318. {
  319. unsigned long flags;
  320. #if 0
  321. printk("WR: %s %s %s\n", value & SAR_GP_EECS ? " " : "/CS",
  322. value & SAR_GP_EESCLK ? "HIGH" : "LOW ",
  323. value & SAR_GP_EEDO ? "1" : "0");
  324. #endif
  325. spin_lock_irqsave(&card->cmd_lock, flags);
  326. waitfor_idle(card);
  327. writel(value, SAR_REG_GP);
  328. spin_unlock_irqrestore(&card->cmd_lock, flags);
  329. }
  330. static u8
  331. idt77252_eeprom_read_status(struct idt77252_dev *card)
  332. {
  333. u8 byte;
  334. u32 gp;
  335. int i, j;
  336. gp = idt77252_read_gp(card) & ~(SAR_GP_EESCLK|SAR_GP_EECS|SAR_GP_EEDO);
  337. for (i = 0; i < ARRAY_SIZE(rdsrtab); i++) {
  338. idt77252_write_gp(card, gp | rdsrtab[i]);
  339. udelay(5);
  340. }
  341. idt77252_write_gp(card, gp | SAR_GP_EECS);
  342. udelay(5);
  343. byte = 0;
  344. for (i = 0, j = 0; i < 8; i++) {
  345. byte <<= 1;
  346. idt77252_write_gp(card, gp | clktab[j++]);
  347. udelay(5);
  348. byte |= idt77252_read_gp(card) & SAR_GP_EEDI ? 1 : 0;
  349. idt77252_write_gp(card, gp | clktab[j++]);
  350. udelay(5);
  351. }
  352. idt77252_write_gp(card, gp | SAR_GP_EECS);
  353. udelay(5);
  354. return byte;
  355. }
  356. static u8
  357. idt77252_eeprom_read_byte(struct idt77252_dev *card, u8 offset)
  358. {
  359. u8 byte;
  360. u32 gp;
  361. int i, j;
  362. gp = idt77252_read_gp(card) & ~(SAR_GP_EESCLK|SAR_GP_EECS|SAR_GP_EEDO);
  363. for (i = 0; i < ARRAY_SIZE(rdtab); i++) {
  364. idt77252_write_gp(card, gp | rdtab[i]);
  365. udelay(5);
  366. }
  367. idt77252_write_gp(card, gp | SAR_GP_EECS);
  368. udelay(5);
  369. for (i = 0, j = 0; i < 8; i++) {
  370. idt77252_write_gp(card, gp | clktab[j++] |
  371. (offset & 1 ? SAR_GP_EEDO : 0));
  372. udelay(5);
  373. idt77252_write_gp(card, gp | clktab[j++] |
  374. (offset & 1 ? SAR_GP_EEDO : 0));
  375. udelay(5);
  376. offset >>= 1;
  377. }
  378. idt77252_write_gp(card, gp | SAR_GP_EECS);
  379. udelay(5);
  380. byte = 0;
  381. for (i = 0, j = 0; i < 8; i++) {
  382. byte <<= 1;
  383. idt77252_write_gp(card, gp | clktab[j++]);
  384. udelay(5);
  385. byte |= idt77252_read_gp(card) & SAR_GP_EEDI ? 1 : 0;
  386. idt77252_write_gp(card, gp | clktab[j++]);
  387. udelay(5);
  388. }
  389. idt77252_write_gp(card, gp | SAR_GP_EECS);
  390. udelay(5);
  391. return byte;
  392. }
  393. static void
  394. idt77252_eeprom_write_byte(struct idt77252_dev *card, u8 offset, u8 data)
  395. {
  396. u32 gp;
  397. int i, j;
  398. gp = idt77252_read_gp(card) & ~(SAR_GP_EESCLK|SAR_GP_EECS|SAR_GP_EEDO);
  399. for (i = 0; i < ARRAY_SIZE(wrentab); i++) {
  400. idt77252_write_gp(card, gp | wrentab[i]);
  401. udelay(5);
  402. }
  403. idt77252_write_gp(card, gp | SAR_GP_EECS);
  404. udelay(5);
  405. for (i = 0; i < ARRAY_SIZE(wrtab); i++) {
  406. idt77252_write_gp(card, gp | wrtab[i]);
  407. udelay(5);
  408. }
  409. idt77252_write_gp(card, gp | SAR_GP_EECS);
  410. udelay(5);
  411. for (i = 0, j = 0; i < 8; i++) {
  412. idt77252_write_gp(card, gp | clktab[j++] |
  413. (offset & 1 ? SAR_GP_EEDO : 0));
  414. udelay(5);
  415. idt77252_write_gp(card, gp | clktab[j++] |
  416. (offset & 1 ? SAR_GP_EEDO : 0));
  417. udelay(5);
  418. offset >>= 1;
  419. }
  420. idt77252_write_gp(card, gp | SAR_GP_EECS);
  421. udelay(5);
  422. for (i = 0, j = 0; i < 8; i++) {
  423. idt77252_write_gp(card, gp | clktab[j++] |
  424. (data & 1 ? SAR_GP_EEDO : 0));
  425. udelay(5);
  426. idt77252_write_gp(card, gp | clktab[j++] |
  427. (data & 1 ? SAR_GP_EEDO : 0));
  428. udelay(5);
  429. data >>= 1;
  430. }
  431. idt77252_write_gp(card, gp | SAR_GP_EECS);
  432. udelay(5);
  433. }
  434. static void
  435. idt77252_eeprom_init(struct idt77252_dev *card)
  436. {
  437. u32 gp;
  438. gp = idt77252_read_gp(card) & ~(SAR_GP_EESCLK|SAR_GP_EECS|SAR_GP_EEDO);
  439. idt77252_write_gp(card, gp | SAR_GP_EECS | SAR_GP_EESCLK);
  440. udelay(5);
  441. idt77252_write_gp(card, gp | SAR_GP_EECS);
  442. udelay(5);
  443. idt77252_write_gp(card, gp | SAR_GP_EECS | SAR_GP_EESCLK);
  444. udelay(5);
  445. idt77252_write_gp(card, gp | SAR_GP_EECS);
  446. udelay(5);
  447. }
  448. #endif /* HAVE_EEPROM */
  449. #ifdef CONFIG_ATM_IDT77252_DEBUG
  450. static void
  451. dump_tct(struct idt77252_dev *card, int index)
  452. {
  453. unsigned long tct;
  454. int i;
  455. tct = (unsigned long) (card->tct_base + index * SAR_SRAM_TCT_SIZE);
  456. printk("%s: TCT %x:", card->name, index);
  457. for (i = 0; i < 8; i++) {
  458. printk(" %08x", read_sram(card, tct + i));
  459. }
  460. printk("\n");
  461. }
  462. static void
  463. idt77252_tx_dump(struct idt77252_dev *card)
  464. {
  465. struct atm_vcc *vcc;
  466. struct vc_map *vc;
  467. int i;
  468. printk("%s\n", __func__);
  469. for (i = 0; i < card->tct_size; i++) {
  470. vc = card->vcs[i];
  471. if (!vc)
  472. continue;
  473. vcc = NULL;
  474. if (vc->rx_vcc)
  475. vcc = vc->rx_vcc;
  476. else if (vc->tx_vcc)
  477. vcc = vc->tx_vcc;
  478. if (!vcc)
  479. continue;
  480. printk("%s: Connection %d:\n", card->name, vc->index);
  481. dump_tct(card, vc->index);
  482. }
  483. }
  484. #endif
  485. /*****************************************************************************/
  486. /* */
  487. /* SCQ Handling */
  488. /* */
  489. /*****************************************************************************/
  490. static int
  491. sb_pool_add(struct idt77252_dev *card, struct sk_buff *skb, int queue)
  492. {
  493. struct sb_pool *pool = &card->sbpool[queue];
  494. int index;
  495. index = pool->index;
  496. while (pool->skb[index]) {
  497. index = (index + 1) & FBQ_MASK;
  498. if (index == pool->index)
  499. return -ENOBUFS;
  500. }
  501. pool->skb[index] = skb;
  502. IDT77252_PRV_POOL(skb) = POOL_HANDLE(queue, index);
  503. pool->index = (index + 1) & FBQ_MASK;
  504. return 0;
  505. }
  506. static void
  507. sb_pool_remove(struct idt77252_dev *card, struct sk_buff *skb)
  508. {
  509. unsigned int queue, index;
  510. u32 handle;
  511. handle = IDT77252_PRV_POOL(skb);
  512. queue = POOL_QUEUE(handle);
  513. if (queue > 3)
  514. return;
  515. index = POOL_INDEX(handle);
  516. if (index > FBQ_SIZE - 1)
  517. return;
  518. card->sbpool[queue].skb[index] = NULL;
  519. }
  520. static struct sk_buff *
  521. sb_pool_skb(struct idt77252_dev *card, u32 handle)
  522. {
  523. unsigned int queue, index;
  524. queue = POOL_QUEUE(handle);
  525. if (queue > 3)
  526. return NULL;
  527. index = POOL_INDEX(handle);
  528. if (index > FBQ_SIZE - 1)
  529. return NULL;
  530. return card->sbpool[queue].skb[index];
  531. }
  532. static struct scq_info *
  533. alloc_scq(struct idt77252_dev *card, int class)
  534. {
  535. struct scq_info *scq;
  536. scq = kzalloc(sizeof(struct scq_info), GFP_KERNEL);
  537. if (!scq)
  538. return NULL;
  539. scq->base = dma_alloc_coherent(&card->pcidev->dev, SCQ_SIZE,
  540. &scq->paddr, GFP_KERNEL);
  541. if (scq->base == NULL) {
  542. kfree(scq);
  543. return NULL;
  544. }
  545. scq->next = scq->base;
  546. scq->last = scq->base + (SCQ_ENTRIES - 1);
  547. atomic_set(&scq->used, 0);
  548. spin_lock_init(&scq->lock);
  549. spin_lock_init(&scq->skblock);
  550. skb_queue_head_init(&scq->transmit);
  551. skb_queue_head_init(&scq->pending);
  552. TXPRINTK("idt77252: SCQ: base 0x%p, next 0x%p, last 0x%p, paddr %08llx\n",
  553. scq->base, scq->next, scq->last, (unsigned long long)scq->paddr);
  554. return scq;
  555. }
  556. static void
  557. free_scq(struct idt77252_dev *card, struct scq_info *scq)
  558. {
  559. struct sk_buff *skb;
  560. struct atm_vcc *vcc;
  561. dma_free_coherent(&card->pcidev->dev, SCQ_SIZE,
  562. scq->base, scq->paddr);
  563. while ((skb = skb_dequeue(&scq->transmit))) {
  564. dma_unmap_single(&card->pcidev->dev, IDT77252_PRV_PADDR(skb),
  565. skb->len, DMA_TO_DEVICE);
  566. vcc = ATM_SKB(skb)->vcc;
  567. if (vcc->pop)
  568. vcc->pop(vcc, skb);
  569. else
  570. dev_kfree_skb(skb);
  571. }
  572. while ((skb = skb_dequeue(&scq->pending))) {
  573. dma_unmap_single(&card->pcidev->dev, IDT77252_PRV_PADDR(skb),
  574. skb->len, DMA_TO_DEVICE);
  575. vcc = ATM_SKB(skb)->vcc;
  576. if (vcc->pop)
  577. vcc->pop(vcc, skb);
  578. else
  579. dev_kfree_skb(skb);
  580. }
  581. kfree(scq);
  582. }
  583. static int
  584. push_on_scq(struct idt77252_dev *card, struct vc_map *vc, struct sk_buff *skb)
  585. {
  586. struct scq_info *scq = vc->scq;
  587. unsigned long flags;
  588. struct scqe *tbd;
  589. int entries;
  590. TXPRINTK("%s: SCQ: next 0x%p\n", card->name, scq->next);
  591. atomic_inc(&scq->used);
  592. entries = atomic_read(&scq->used);
  593. if (entries > (SCQ_ENTRIES - 1)) {
  594. atomic_dec(&scq->used);
  595. goto out;
  596. }
  597. skb_queue_tail(&scq->transmit, skb);
  598. spin_lock_irqsave(&vc->lock, flags);
  599. if (vc->estimator) {
  600. struct atm_vcc *vcc = vc->tx_vcc;
  601. struct sock *sk = sk_atm(vcc);
  602. vc->estimator->cells += (skb->len + 47) / 48;
  603. if (refcount_read(&sk->sk_wmem_alloc) >
  604. (sk->sk_sndbuf >> 1)) {
  605. u32 cps = vc->estimator->maxcps;
  606. vc->estimator->cps = cps;
  607. vc->estimator->avcps = cps << 5;
  608. if (vc->lacr < vc->init_er) {
  609. vc->lacr = vc->init_er;
  610. writel(TCMDQ_LACR | (vc->lacr << 16) |
  611. vc->index, SAR_REG_TCMDQ);
  612. }
  613. }
  614. }
  615. spin_unlock_irqrestore(&vc->lock, flags);
  616. tbd = &IDT77252_PRV_TBD(skb);
  617. spin_lock_irqsave(&scq->lock, flags);
  618. scq->next->word_1 = cpu_to_le32(tbd->word_1 |
  619. SAR_TBD_TSIF | SAR_TBD_GTSI);
  620. scq->next->word_2 = cpu_to_le32(tbd->word_2);
  621. scq->next->word_3 = cpu_to_le32(tbd->word_3);
  622. scq->next->word_4 = cpu_to_le32(tbd->word_4);
  623. if (scq->next == scq->last)
  624. scq->next = scq->base;
  625. else
  626. scq->next++;
  627. write_sram(card, scq->scd,
  628. scq->paddr +
  629. (u32)((unsigned long)scq->next - (unsigned long)scq->base));
  630. spin_unlock_irqrestore(&scq->lock, flags);
  631. scq->trans_start = jiffies;
  632. if (test_and_clear_bit(VCF_IDLE, &vc->flags)) {
  633. writel(TCMDQ_START_LACR | (vc->lacr << 16) | vc->index,
  634. SAR_REG_TCMDQ);
  635. }
  636. TXPRINTK("%d entries in SCQ used (push).\n", atomic_read(&scq->used));
  637. XPRINTK("%s: SCQ (after push %2d) head = 0x%x, next = 0x%p.\n",
  638. card->name, atomic_read(&scq->used),
  639. read_sram(card, scq->scd + 1), scq->next);
  640. return 0;
  641. out:
  642. if (time_after(jiffies, scq->trans_start + HZ)) {
  643. printk("%s: Error pushing TBD for %d.%d\n",
  644. card->name, vc->tx_vcc->vpi, vc->tx_vcc->vci);
  645. #ifdef CONFIG_ATM_IDT77252_DEBUG
  646. idt77252_tx_dump(card);
  647. #endif
  648. scq->trans_start = jiffies;
  649. }
  650. return -ENOBUFS;
  651. }
  652. static void
  653. drain_scq(struct idt77252_dev *card, struct vc_map *vc)
  654. {
  655. struct scq_info *scq = vc->scq;
  656. struct sk_buff *skb;
  657. struct atm_vcc *vcc;
  658. TXPRINTK("%s: SCQ (before drain %2d) next = 0x%p.\n",
  659. card->name, atomic_read(&scq->used), scq->next);
  660. skb = skb_dequeue(&scq->transmit);
  661. if (skb) {
  662. TXPRINTK("%s: freeing skb at %p.\n", card->name, skb);
  663. dma_unmap_single(&card->pcidev->dev, IDT77252_PRV_PADDR(skb),
  664. skb->len, DMA_TO_DEVICE);
  665. vcc = ATM_SKB(skb)->vcc;
  666. if (vcc->pop)
  667. vcc->pop(vcc, skb);
  668. else
  669. dev_kfree_skb(skb);
  670. atomic_inc(&vcc->stats->tx);
  671. }
  672. atomic_dec(&scq->used);
  673. spin_lock(&scq->skblock);
  674. while ((skb = skb_dequeue(&scq->pending))) {
  675. if (push_on_scq(card, vc, skb)) {
  676. skb_queue_head(&vc->scq->pending, skb);
  677. break;
  678. }
  679. }
  680. spin_unlock(&scq->skblock);
  681. }
  682. static int
  683. queue_skb(struct idt77252_dev *card, struct vc_map *vc,
  684. struct sk_buff *skb, int oam)
  685. {
  686. struct atm_vcc *vcc;
  687. struct scqe *tbd;
  688. unsigned long flags;
  689. int error;
  690. int aal;
  691. u32 word4;
  692. if (skb->len == 0) {
  693. printk("%s: invalid skb->len (%d)\n", card->name, skb->len);
  694. return -EINVAL;
  695. }
  696. TXPRINTK("%s: Sending %d bytes of data.\n",
  697. card->name, skb->len);
  698. tbd = &IDT77252_PRV_TBD(skb);
  699. vcc = ATM_SKB(skb)->vcc;
  700. word4 = (skb->data[0] << 24) | (skb->data[1] << 16) |
  701. (skb->data[2] << 8) | (skb->data[3] << 0);
  702. IDT77252_PRV_PADDR(skb) = dma_map_single(&card->pcidev->dev, skb->data,
  703. skb->len, DMA_TO_DEVICE);
  704. error = -EINVAL;
  705. if (oam) {
  706. if (skb->len != 52)
  707. goto errout;
  708. tbd->word_1 = SAR_TBD_OAM | ATM_CELL_PAYLOAD | SAR_TBD_EPDU;
  709. tbd->word_2 = IDT77252_PRV_PADDR(skb) + 4;
  710. tbd->word_3 = 0x00000000;
  711. tbd->word_4 = word4;
  712. if (test_bit(VCF_RSV, &vc->flags))
  713. vc = card->vcs[0];
  714. goto done;
  715. }
  716. if (test_bit(VCF_RSV, &vc->flags)) {
  717. printk("%s: Trying to transmit on reserved VC\n", card->name);
  718. goto errout;
  719. }
  720. aal = vcc->qos.aal;
  721. switch (aal) {
  722. case ATM_AAL0:
  723. case ATM_AAL34:
  724. if (skb->len > 52)
  725. goto errout;
  726. if (aal == ATM_AAL0)
  727. tbd->word_1 = SAR_TBD_EPDU | SAR_TBD_AAL0 |
  728. ATM_CELL_PAYLOAD;
  729. else
  730. tbd->word_1 = SAR_TBD_EPDU | SAR_TBD_AAL34 |
  731. ATM_CELL_PAYLOAD;
  732. tbd->word_2 = IDT77252_PRV_PADDR(skb) + 4;
  733. tbd->word_3 = 0x00000000;
  734. tbd->word_4 = word4;
  735. break;
  736. case ATM_AAL5:
  737. tbd->word_1 = SAR_TBD_EPDU | SAR_TBD_AAL5 | skb->len;
  738. tbd->word_2 = IDT77252_PRV_PADDR(skb);
  739. tbd->word_3 = skb->len;
  740. tbd->word_4 = (vcc->vpi << SAR_TBD_VPI_SHIFT) |
  741. (vcc->vci << SAR_TBD_VCI_SHIFT);
  742. break;
  743. case ATM_AAL1:
  744. case ATM_AAL2:
  745. default:
  746. printk("%s: Traffic type not supported.\n", card->name);
  747. error = -EPROTONOSUPPORT;
  748. goto errout;
  749. }
  750. done:
  751. spin_lock_irqsave(&vc->scq->skblock, flags);
  752. skb_queue_tail(&vc->scq->pending, skb);
  753. while ((skb = skb_dequeue(&vc->scq->pending))) {
  754. if (push_on_scq(card, vc, skb)) {
  755. skb_queue_head(&vc->scq->pending, skb);
  756. break;
  757. }
  758. }
  759. spin_unlock_irqrestore(&vc->scq->skblock, flags);
  760. return 0;
  761. errout:
  762. dma_unmap_single(&card->pcidev->dev, IDT77252_PRV_PADDR(skb),
  763. skb->len, DMA_TO_DEVICE);
  764. return error;
  765. }
  766. static unsigned long
  767. get_free_scd(struct idt77252_dev *card, struct vc_map *vc)
  768. {
  769. int i;
  770. for (i = 0; i < card->scd_size; i++) {
  771. if (!card->scd2vc[i]) {
  772. card->scd2vc[i] = vc;
  773. vc->scd_index = i;
  774. return card->scd_base + i * SAR_SRAM_SCD_SIZE;
  775. }
  776. }
  777. return 0;
  778. }
  779. static void
  780. fill_scd(struct idt77252_dev *card, struct scq_info *scq, int class)
  781. {
  782. write_sram(card, scq->scd, scq->paddr);
  783. write_sram(card, scq->scd + 1, 0x00000000);
  784. write_sram(card, scq->scd + 2, 0xffffffff);
  785. write_sram(card, scq->scd + 3, 0x00000000);
  786. }
  787. static void
  788. clear_scd(struct idt77252_dev *card, struct scq_info *scq, int class)
  789. {
  790. return;
  791. }
  792. /*****************************************************************************/
  793. /* */
  794. /* RSQ Handling */
  795. /* */
  796. /*****************************************************************************/
  797. static int
  798. init_rsq(struct idt77252_dev *card)
  799. {
  800. struct rsq_entry *rsqe;
  801. card->rsq.base = dma_alloc_coherent(&card->pcidev->dev, RSQSIZE,
  802. &card->rsq.paddr, GFP_KERNEL);
  803. if (card->rsq.base == NULL) {
  804. printk("%s: can't allocate RSQ.\n", card->name);
  805. return -1;
  806. }
  807. card->rsq.last = card->rsq.base + RSQ_NUM_ENTRIES - 1;
  808. card->rsq.next = card->rsq.last;
  809. for (rsqe = card->rsq.base; rsqe <= card->rsq.last; rsqe++)
  810. rsqe->word_4 = 0;
  811. writel((unsigned long) card->rsq.last - (unsigned long) card->rsq.base,
  812. SAR_REG_RSQH);
  813. writel(card->rsq.paddr, SAR_REG_RSQB);
  814. IPRINTK("%s: RSQ base at 0x%lx (0x%x).\n", card->name,
  815. (unsigned long) card->rsq.base,
  816. readl(SAR_REG_RSQB));
  817. IPRINTK("%s: RSQ head = 0x%x, base = 0x%x, tail = 0x%x.\n",
  818. card->name,
  819. readl(SAR_REG_RSQH),
  820. readl(SAR_REG_RSQB),
  821. readl(SAR_REG_RSQT));
  822. return 0;
  823. }
  824. static void
  825. deinit_rsq(struct idt77252_dev *card)
  826. {
  827. dma_free_coherent(&card->pcidev->dev, RSQSIZE,
  828. card->rsq.base, card->rsq.paddr);
  829. }
  830. static void
  831. dequeue_rx(struct idt77252_dev *card, struct rsq_entry *rsqe)
  832. {
  833. struct atm_vcc *vcc;
  834. struct sk_buff *skb;
  835. struct rx_pool *rpp;
  836. struct vc_map *vc;
  837. u32 header, vpi, vci;
  838. u32 stat;
  839. int i;
  840. stat = le32_to_cpu(rsqe->word_4);
  841. if (stat & SAR_RSQE_IDLE) {
  842. RXPRINTK("%s: message about inactive connection.\n",
  843. card->name);
  844. return;
  845. }
  846. skb = sb_pool_skb(card, le32_to_cpu(rsqe->word_2));
  847. if (skb == NULL) {
  848. printk("%s: NULL skb in %s, rsqe: %08x %08x %08x %08x\n",
  849. card->name, __func__,
  850. le32_to_cpu(rsqe->word_1), le32_to_cpu(rsqe->word_2),
  851. le32_to_cpu(rsqe->word_3), le32_to_cpu(rsqe->word_4));
  852. return;
  853. }
  854. header = le32_to_cpu(rsqe->word_1);
  855. vpi = (header >> 16) & 0x00ff;
  856. vci = (header >> 0) & 0xffff;
  857. RXPRINTK("%s: SDU for %d.%d received in buffer 0x%p (data 0x%p).\n",
  858. card->name, vpi, vci, skb, skb->data);
  859. if ((vpi >= (1 << card->vpibits)) || (vci != (vci & card->vcimask))) {
  860. printk("%s: SDU received for out-of-range vc %u.%u\n",
  861. card->name, vpi, vci);
  862. recycle_rx_skb(card, skb);
  863. return;
  864. }
  865. vc = card->vcs[VPCI2VC(card, vpi, vci)];
  866. if (!vc || !test_bit(VCF_RX, &vc->flags)) {
  867. printk("%s: SDU received on non RX vc %u.%u\n",
  868. card->name, vpi, vci);
  869. recycle_rx_skb(card, skb);
  870. return;
  871. }
  872. vcc = vc->rx_vcc;
  873. dma_sync_single_for_cpu(&card->pcidev->dev, IDT77252_PRV_PADDR(skb),
  874. skb_end_pointer(skb) - skb->data,
  875. DMA_FROM_DEVICE);
  876. if ((vcc->qos.aal == ATM_AAL0) ||
  877. (vcc->qos.aal == ATM_AAL34)) {
  878. struct sk_buff *sb;
  879. unsigned char *cell;
  880. u32 aal0;
  881. cell = skb->data;
  882. for (i = (stat & SAR_RSQE_CELLCNT); i; i--) {
  883. if ((sb = dev_alloc_skb(64)) == NULL) {
  884. printk("%s: Can't allocate buffers for aal0.\n",
  885. card->name);
  886. atomic_add(i, &vcc->stats->rx_drop);
  887. break;
  888. }
  889. if (!atm_charge(vcc, sb->truesize)) {
  890. RXPRINTK("%s: atm_charge() dropped aal0 packets.\n",
  891. card->name);
  892. atomic_add(i - 1, &vcc->stats->rx_drop);
  893. dev_kfree_skb(sb);
  894. break;
  895. }
  896. aal0 = (vpi << ATM_HDR_VPI_SHIFT) |
  897. (vci << ATM_HDR_VCI_SHIFT);
  898. aal0 |= (stat & SAR_RSQE_EPDU) ? 0x00000002 : 0;
  899. aal0 |= (stat & SAR_RSQE_CLP) ? 0x00000001 : 0;
  900. *((u32 *) sb->data) = aal0;
  901. skb_put(sb, sizeof(u32));
  902. skb_put_data(sb, cell, ATM_CELL_PAYLOAD);
  903. ATM_SKB(sb)->vcc = vcc;
  904. __net_timestamp(sb);
  905. vcc->push(vcc, sb);
  906. atomic_inc(&vcc->stats->rx);
  907. cell += ATM_CELL_PAYLOAD;
  908. }
  909. recycle_rx_skb(card, skb);
  910. return;
  911. }
  912. if (vcc->qos.aal != ATM_AAL5) {
  913. printk("%s: Unexpected AAL type in dequeue_rx(): %d.\n",
  914. card->name, vcc->qos.aal);
  915. recycle_rx_skb(card, skb);
  916. return;
  917. }
  918. skb->len = (stat & SAR_RSQE_CELLCNT) * ATM_CELL_PAYLOAD;
  919. rpp = &vc->rcv.rx_pool;
  920. __skb_queue_tail(&rpp->queue, skb);
  921. rpp->len += skb->len;
  922. if (stat & SAR_RSQE_EPDU) {
  923. unsigned char *l1l2;
  924. unsigned int len;
  925. l1l2 = (unsigned char *) ((unsigned long) skb->data + skb->len - 6);
  926. len = (l1l2[0] << 8) | l1l2[1];
  927. len = len ? len : 0x10000;
  928. RXPRINTK("%s: PDU has %d bytes.\n", card->name, len);
  929. if ((len + 8 > rpp->len) || (len + (47 + 8) < rpp->len)) {
  930. RXPRINTK("%s: AAL5 PDU size mismatch: %d != %d. "
  931. "(CDC: %08x)\n",
  932. card->name, len, rpp->len, readl(SAR_REG_CDC));
  933. recycle_rx_pool_skb(card, rpp);
  934. atomic_inc(&vcc->stats->rx_err);
  935. return;
  936. }
  937. if (stat & SAR_RSQE_CRC) {
  938. RXPRINTK("%s: AAL5 CRC error.\n", card->name);
  939. recycle_rx_pool_skb(card, rpp);
  940. atomic_inc(&vcc->stats->rx_err);
  941. return;
  942. }
  943. if (skb_queue_len(&rpp->queue) > 1) {
  944. struct sk_buff *sb;
  945. skb = dev_alloc_skb(rpp->len);
  946. if (!skb) {
  947. RXPRINTK("%s: Can't alloc RX skb.\n",
  948. card->name);
  949. recycle_rx_pool_skb(card, rpp);
  950. atomic_inc(&vcc->stats->rx_err);
  951. return;
  952. }
  953. if (!atm_charge(vcc, skb->truesize)) {
  954. recycle_rx_pool_skb(card, rpp);
  955. dev_kfree_skb(skb);
  956. return;
  957. }
  958. skb_queue_walk(&rpp->queue, sb)
  959. skb_put_data(skb, sb->data, sb->len);
  960. recycle_rx_pool_skb(card, rpp);
  961. skb_trim(skb, len);
  962. ATM_SKB(skb)->vcc = vcc;
  963. __net_timestamp(skb);
  964. vcc->push(vcc, skb);
  965. atomic_inc(&vcc->stats->rx);
  966. return;
  967. }
  968. flush_rx_pool(card, rpp);
  969. if (!atm_charge(vcc, skb->truesize)) {
  970. recycle_rx_skb(card, skb);
  971. return;
  972. }
  973. dma_unmap_single(&card->pcidev->dev, IDT77252_PRV_PADDR(skb),
  974. skb_end_pointer(skb) - skb->data,
  975. DMA_FROM_DEVICE);
  976. sb_pool_remove(card, skb);
  977. skb_trim(skb, len);
  978. ATM_SKB(skb)->vcc = vcc;
  979. __net_timestamp(skb);
  980. vcc->push(vcc, skb);
  981. atomic_inc(&vcc->stats->rx);
  982. if (skb->truesize > SAR_FB_SIZE_3)
  983. add_rx_skb(card, 3, SAR_FB_SIZE_3, 1);
  984. else if (skb->truesize > SAR_FB_SIZE_2)
  985. add_rx_skb(card, 2, SAR_FB_SIZE_2, 1);
  986. else if (skb->truesize > SAR_FB_SIZE_1)
  987. add_rx_skb(card, 1, SAR_FB_SIZE_1, 1);
  988. else
  989. add_rx_skb(card, 0, SAR_FB_SIZE_0, 1);
  990. return;
  991. }
  992. }
  993. static void
  994. idt77252_rx(struct idt77252_dev *card)
  995. {
  996. struct rsq_entry *rsqe;
  997. if (card->rsq.next == card->rsq.last)
  998. rsqe = card->rsq.base;
  999. else
  1000. rsqe = card->rsq.next + 1;
  1001. if (!(le32_to_cpu(rsqe->word_4) & SAR_RSQE_VALID)) {
  1002. RXPRINTK("%s: no entry in RSQ.\n", card->name);
  1003. return;
  1004. }
  1005. do {
  1006. dequeue_rx(card, rsqe);
  1007. rsqe->word_4 = 0;
  1008. card->rsq.next = rsqe;
  1009. if (card->rsq.next == card->rsq.last)
  1010. rsqe = card->rsq.base;
  1011. else
  1012. rsqe = card->rsq.next + 1;
  1013. } while (le32_to_cpu(rsqe->word_4) & SAR_RSQE_VALID);
  1014. writel((unsigned long) card->rsq.next - (unsigned long) card->rsq.base,
  1015. SAR_REG_RSQH);
  1016. }
  1017. static void
  1018. idt77252_rx_raw(struct idt77252_dev *card)
  1019. {
  1020. struct sk_buff *queue;
  1021. u32 head, tail;
  1022. struct atm_vcc *vcc;
  1023. struct vc_map *vc;
  1024. struct sk_buff *sb;
  1025. if (card->raw_cell_head == NULL) {
  1026. u32 handle = le32_to_cpu(*(card->raw_cell_hnd + 1));
  1027. card->raw_cell_head = sb_pool_skb(card, handle);
  1028. }
  1029. queue = card->raw_cell_head;
  1030. if (!queue)
  1031. return;
  1032. head = IDT77252_PRV_PADDR(queue) + (queue->data - queue->head - 16);
  1033. tail = readl(SAR_REG_RAWCT);
  1034. dma_sync_single_for_cpu(&card->pcidev->dev, IDT77252_PRV_PADDR(queue),
  1035. skb_end_offset(queue) - 16,
  1036. DMA_FROM_DEVICE);
  1037. while (head != tail) {
  1038. unsigned int vpi, vci;
  1039. u32 header;
  1040. header = le32_to_cpu(*(u32 *) &queue->data[0]);
  1041. vpi = (header & ATM_HDR_VPI_MASK) >> ATM_HDR_VPI_SHIFT;
  1042. vci = (header & ATM_HDR_VCI_MASK) >> ATM_HDR_VCI_SHIFT;
  1043. #ifdef CONFIG_ATM_IDT77252_DEBUG
  1044. if (debug & DBG_RAW_CELL) {
  1045. int i;
  1046. printk("%s: raw cell %x.%02x.%04x.%x.%x\n",
  1047. card->name, (header >> 28) & 0x000f,
  1048. (header >> 20) & 0x00ff,
  1049. (header >> 4) & 0xffff,
  1050. (header >> 1) & 0x0007,
  1051. (header >> 0) & 0x0001);
  1052. for (i = 16; i < 64; i++)
  1053. printk(" %02x", queue->data[i]);
  1054. printk("\n");
  1055. }
  1056. #endif
  1057. if (vpi >= (1<<card->vpibits) || vci >= (1<<card->vcibits)) {
  1058. RPRINTK("%s: SDU received for out-of-range vc %u.%u\n",
  1059. card->name, vpi, vci);
  1060. goto drop;
  1061. }
  1062. vc = card->vcs[VPCI2VC(card, vpi, vci)];
  1063. if (!vc || !test_bit(VCF_RX, &vc->flags)) {
  1064. RPRINTK("%s: SDU received on non RX vc %u.%u\n",
  1065. card->name, vpi, vci);
  1066. goto drop;
  1067. }
  1068. vcc = vc->rx_vcc;
  1069. if (vcc->qos.aal != ATM_AAL0) {
  1070. RPRINTK("%s: raw cell for non AAL0 vc %u.%u\n",
  1071. card->name, vpi, vci);
  1072. atomic_inc(&vcc->stats->rx_drop);
  1073. goto drop;
  1074. }
  1075. if ((sb = dev_alloc_skb(64)) == NULL) {
  1076. printk("%s: Can't allocate buffers for AAL0.\n",
  1077. card->name);
  1078. atomic_inc(&vcc->stats->rx_err);
  1079. goto drop;
  1080. }
  1081. if (!atm_charge(vcc, sb->truesize)) {
  1082. RXPRINTK("%s: atm_charge() dropped AAL0 packets.\n",
  1083. card->name);
  1084. dev_kfree_skb(sb);
  1085. goto drop;
  1086. }
  1087. *((u32 *) sb->data) = header;
  1088. skb_put(sb, sizeof(u32));
  1089. skb_put_data(sb, &(queue->data[16]), ATM_CELL_PAYLOAD);
  1090. ATM_SKB(sb)->vcc = vcc;
  1091. __net_timestamp(sb);
  1092. vcc->push(vcc, sb);
  1093. atomic_inc(&vcc->stats->rx);
  1094. drop:
  1095. skb_pull(queue, 64);
  1096. head = IDT77252_PRV_PADDR(queue)
  1097. + (queue->data - queue->head - 16);
  1098. if (queue->len < 128) {
  1099. struct sk_buff *next;
  1100. u32 handle;
  1101. head = le32_to_cpu(*(u32 *) &queue->data[0]);
  1102. handle = le32_to_cpu(*(u32 *) &queue->data[4]);
  1103. next = sb_pool_skb(card, handle);
  1104. recycle_rx_skb(card, queue);
  1105. if (next) {
  1106. card->raw_cell_head = next;
  1107. queue = card->raw_cell_head;
  1108. dma_sync_single_for_cpu(&card->pcidev->dev,
  1109. IDT77252_PRV_PADDR(queue),
  1110. (skb_end_pointer(queue) -
  1111. queue->data),
  1112. DMA_FROM_DEVICE);
  1113. } else {
  1114. card->raw_cell_head = NULL;
  1115. printk("%s: raw cell queue overrun\n",
  1116. card->name);
  1117. break;
  1118. }
  1119. }
  1120. }
  1121. }
  1122. /*****************************************************************************/
  1123. /* */
  1124. /* TSQ Handling */
  1125. /* */
  1126. /*****************************************************************************/
  1127. static int
  1128. init_tsq(struct idt77252_dev *card)
  1129. {
  1130. struct tsq_entry *tsqe;
  1131. card->tsq.base = dma_alloc_coherent(&card->pcidev->dev, RSQSIZE,
  1132. &card->tsq.paddr, GFP_KERNEL);
  1133. if (card->tsq.base == NULL) {
  1134. printk("%s: can't allocate TSQ.\n", card->name);
  1135. return -1;
  1136. }
  1137. card->tsq.last = card->tsq.base + TSQ_NUM_ENTRIES - 1;
  1138. card->tsq.next = card->tsq.last;
  1139. for (tsqe = card->tsq.base; tsqe <= card->tsq.last; tsqe++)
  1140. tsqe->word_2 = cpu_to_le32(SAR_TSQE_INVALID);
  1141. writel(card->tsq.paddr, SAR_REG_TSQB);
  1142. writel((unsigned long) card->tsq.next - (unsigned long) card->tsq.base,
  1143. SAR_REG_TSQH);
  1144. return 0;
  1145. }
  1146. static void
  1147. deinit_tsq(struct idt77252_dev *card)
  1148. {
  1149. dma_free_coherent(&card->pcidev->dev, TSQSIZE,
  1150. card->tsq.base, card->tsq.paddr);
  1151. }
  1152. static void
  1153. idt77252_tx(struct idt77252_dev *card)
  1154. {
  1155. struct tsq_entry *tsqe;
  1156. unsigned int vpi, vci;
  1157. struct vc_map *vc;
  1158. u32 conn, stat;
  1159. if (card->tsq.next == card->tsq.last)
  1160. tsqe = card->tsq.base;
  1161. else
  1162. tsqe = card->tsq.next + 1;
  1163. TXPRINTK("idt77252_tx: tsq %p: base %p, next %p, last %p\n", tsqe,
  1164. card->tsq.base, card->tsq.next, card->tsq.last);
  1165. TXPRINTK("idt77252_tx: tsqb %08x, tsqt %08x, tsqh %08x, \n",
  1166. readl(SAR_REG_TSQB),
  1167. readl(SAR_REG_TSQT),
  1168. readl(SAR_REG_TSQH));
  1169. stat = le32_to_cpu(tsqe->word_2);
  1170. if (stat & SAR_TSQE_INVALID)
  1171. return;
  1172. do {
  1173. TXPRINTK("tsqe: 0x%p [0x%08x 0x%08x]\n", tsqe,
  1174. le32_to_cpu(tsqe->word_1),
  1175. le32_to_cpu(tsqe->word_2));
  1176. switch (stat & SAR_TSQE_TYPE) {
  1177. case SAR_TSQE_TYPE_TIMER:
  1178. TXPRINTK("%s: Timer RollOver detected.\n", card->name);
  1179. break;
  1180. case SAR_TSQE_TYPE_IDLE:
  1181. conn = le32_to_cpu(tsqe->word_1);
  1182. if (SAR_TSQE_TAG(stat) == 0x10) {
  1183. #ifdef NOTDEF
  1184. printk("%s: Connection %d halted.\n",
  1185. card->name,
  1186. le32_to_cpu(tsqe->word_1) & 0x1fff);
  1187. #endif
  1188. break;
  1189. }
  1190. vc = card->vcs[conn & 0x1fff];
  1191. if (!vc) {
  1192. printk("%s: could not find VC from conn %d\n",
  1193. card->name, conn & 0x1fff);
  1194. break;
  1195. }
  1196. printk("%s: Connection %d IDLE.\n",
  1197. card->name, vc->index);
  1198. set_bit(VCF_IDLE, &vc->flags);
  1199. break;
  1200. case SAR_TSQE_TYPE_TSR:
  1201. conn = le32_to_cpu(tsqe->word_1);
  1202. vc = card->vcs[conn & 0x1fff];
  1203. if (!vc) {
  1204. printk("%s: no VC at index %d\n",
  1205. card->name,
  1206. le32_to_cpu(tsqe->word_1) & 0x1fff);
  1207. break;
  1208. }
  1209. drain_scq(card, vc);
  1210. break;
  1211. case SAR_TSQE_TYPE_TBD_COMP:
  1212. conn = le32_to_cpu(tsqe->word_1);
  1213. vpi = (conn >> SAR_TBD_VPI_SHIFT) & 0x00ff;
  1214. vci = (conn >> SAR_TBD_VCI_SHIFT) & 0xffff;
  1215. if (vpi >= (1 << card->vpibits) ||
  1216. vci >= (1 << card->vcibits)) {
  1217. printk("%s: TBD complete: "
  1218. "out of range VPI.VCI %u.%u\n",
  1219. card->name, vpi, vci);
  1220. break;
  1221. }
  1222. vc = card->vcs[VPCI2VC(card, vpi, vci)];
  1223. if (!vc) {
  1224. printk("%s: TBD complete: "
  1225. "no VC at VPI.VCI %u.%u\n",
  1226. card->name, vpi, vci);
  1227. break;
  1228. }
  1229. drain_scq(card, vc);
  1230. break;
  1231. }
  1232. tsqe->word_2 = cpu_to_le32(SAR_TSQE_INVALID);
  1233. card->tsq.next = tsqe;
  1234. if (card->tsq.next == card->tsq.last)
  1235. tsqe = card->tsq.base;
  1236. else
  1237. tsqe = card->tsq.next + 1;
  1238. TXPRINTK("tsqe: %p: base %p, next %p, last %p\n", tsqe,
  1239. card->tsq.base, card->tsq.next, card->tsq.last);
  1240. stat = le32_to_cpu(tsqe->word_2);
  1241. } while (!(stat & SAR_TSQE_INVALID));
  1242. writel((unsigned long)card->tsq.next - (unsigned long)card->tsq.base,
  1243. SAR_REG_TSQH);
  1244. XPRINTK("idt77252_tx-after writel%d: TSQ head = 0x%x, tail = 0x%x, next = 0x%p.\n",
  1245. card->index, readl(SAR_REG_TSQH),
  1246. readl(SAR_REG_TSQT), card->tsq.next);
  1247. }
  1248. static void
  1249. tst_timer(struct timer_list *t)
  1250. {
  1251. struct idt77252_dev *card = from_timer(card, t, tst_timer);
  1252. unsigned long base, idle, jump;
  1253. unsigned long flags;
  1254. u32 pc;
  1255. int e;
  1256. spin_lock_irqsave(&card->tst_lock, flags);
  1257. base = card->tst[card->tst_index];
  1258. idle = card->tst[card->tst_index ^ 1];
  1259. if (test_bit(TST_SWITCH_WAIT, &card->tst_state)) {
  1260. jump = base + card->tst_size - 2;
  1261. pc = readl(SAR_REG_NOW) >> 2;
  1262. if ((pc ^ idle) & ~(card->tst_size - 1)) {
  1263. mod_timer(&card->tst_timer, jiffies + 1);
  1264. goto out;
  1265. }
  1266. clear_bit(TST_SWITCH_WAIT, &card->tst_state);
  1267. card->tst_index ^= 1;
  1268. write_sram(card, jump, TSTE_OPC_JMP | (base << 2));
  1269. base = card->tst[card->tst_index];
  1270. idle = card->tst[card->tst_index ^ 1];
  1271. for (e = 0; e < card->tst_size - 2; e++) {
  1272. if (card->soft_tst[e].tste & TSTE_PUSH_IDLE) {
  1273. write_sram(card, idle + e,
  1274. card->soft_tst[e].tste & TSTE_MASK);
  1275. card->soft_tst[e].tste &= ~(TSTE_PUSH_IDLE);
  1276. }
  1277. }
  1278. }
  1279. if (test_and_clear_bit(TST_SWITCH_PENDING, &card->tst_state)) {
  1280. for (e = 0; e < card->tst_size - 2; e++) {
  1281. if (card->soft_tst[e].tste & TSTE_PUSH_ACTIVE) {
  1282. write_sram(card, idle + e,
  1283. card->soft_tst[e].tste & TSTE_MASK);
  1284. card->soft_tst[e].tste &= ~(TSTE_PUSH_ACTIVE);
  1285. card->soft_tst[e].tste |= TSTE_PUSH_IDLE;
  1286. }
  1287. }
  1288. jump = base + card->tst_size - 2;
  1289. write_sram(card, jump, TSTE_OPC_NULL);
  1290. set_bit(TST_SWITCH_WAIT, &card->tst_state);
  1291. mod_timer(&card->tst_timer, jiffies + 1);
  1292. }
  1293. out:
  1294. spin_unlock_irqrestore(&card->tst_lock, flags);
  1295. }
  1296. static int
  1297. __fill_tst(struct idt77252_dev *card, struct vc_map *vc,
  1298. int n, unsigned int opc)
  1299. {
  1300. unsigned long cl, avail;
  1301. unsigned long idle;
  1302. int e, r;
  1303. u32 data;
  1304. avail = card->tst_size - 2;
  1305. for (e = 0; e < avail; e++) {
  1306. if (card->soft_tst[e].vc == NULL)
  1307. break;
  1308. }
  1309. if (e >= avail) {
  1310. printk("%s: No free TST entries found\n", card->name);
  1311. return -1;
  1312. }
  1313. NPRINTK("%s: conn %d: first TST entry at %d.\n",
  1314. card->name, vc ? vc->index : -1, e);
  1315. r = n;
  1316. cl = avail;
  1317. data = opc & TSTE_OPC_MASK;
  1318. if (vc && (opc != TSTE_OPC_NULL))
  1319. data = opc | vc->index;
  1320. idle = card->tst[card->tst_index ^ 1];
  1321. /*
  1322. * Fill Soft TST.
  1323. */
  1324. while (r > 0) {
  1325. if ((cl >= avail) && (card->soft_tst[e].vc == NULL)) {
  1326. if (vc)
  1327. card->soft_tst[e].vc = vc;
  1328. else
  1329. card->soft_tst[e].vc = (void *)-1;
  1330. card->soft_tst[e].tste = data;
  1331. if (timer_pending(&card->tst_timer))
  1332. card->soft_tst[e].tste |= TSTE_PUSH_ACTIVE;
  1333. else {
  1334. write_sram(card, idle + e, data);
  1335. card->soft_tst[e].tste |= TSTE_PUSH_IDLE;
  1336. }
  1337. cl -= card->tst_size;
  1338. r--;
  1339. }
  1340. if (++e == avail)
  1341. e = 0;
  1342. cl += n;
  1343. }
  1344. return 0;
  1345. }
  1346. static int
  1347. fill_tst(struct idt77252_dev *card, struct vc_map *vc, int n, unsigned int opc)
  1348. {
  1349. unsigned long flags;
  1350. int res;
  1351. spin_lock_irqsave(&card->tst_lock, flags);
  1352. res = __fill_tst(card, vc, n, opc);
  1353. set_bit(TST_SWITCH_PENDING, &card->tst_state);
  1354. if (!timer_pending(&card->tst_timer))
  1355. mod_timer(&card->tst_timer, jiffies + 1);
  1356. spin_unlock_irqrestore(&card->tst_lock, flags);
  1357. return res;
  1358. }
  1359. static int
  1360. __clear_tst(struct idt77252_dev *card, struct vc_map *vc)
  1361. {
  1362. unsigned long idle;
  1363. int e;
  1364. idle = card->tst[card->tst_index ^ 1];
  1365. for (e = 0; e < card->tst_size - 2; e++) {
  1366. if (card->soft_tst[e].vc == vc) {
  1367. card->soft_tst[e].vc = NULL;
  1368. card->soft_tst[e].tste = TSTE_OPC_VAR;
  1369. if (timer_pending(&card->tst_timer))
  1370. card->soft_tst[e].tste |= TSTE_PUSH_ACTIVE;
  1371. else {
  1372. write_sram(card, idle + e, TSTE_OPC_VAR);
  1373. card->soft_tst[e].tste |= TSTE_PUSH_IDLE;
  1374. }
  1375. }
  1376. }
  1377. return 0;
  1378. }
  1379. static int
  1380. clear_tst(struct idt77252_dev *card, struct vc_map *vc)
  1381. {
  1382. unsigned long flags;
  1383. int res;
  1384. spin_lock_irqsave(&card->tst_lock, flags);
  1385. res = __clear_tst(card, vc);
  1386. set_bit(TST_SWITCH_PENDING, &card->tst_state);
  1387. if (!timer_pending(&card->tst_timer))
  1388. mod_timer(&card->tst_timer, jiffies + 1);
  1389. spin_unlock_irqrestore(&card->tst_lock, flags);
  1390. return res;
  1391. }
  1392. static int
  1393. change_tst(struct idt77252_dev *card, struct vc_map *vc,
  1394. int n, unsigned int opc)
  1395. {
  1396. unsigned long flags;
  1397. int res;
  1398. spin_lock_irqsave(&card->tst_lock, flags);
  1399. __clear_tst(card, vc);
  1400. res = __fill_tst(card, vc, n, opc);
  1401. set_bit(TST_SWITCH_PENDING, &card->tst_state);
  1402. if (!timer_pending(&card->tst_timer))
  1403. mod_timer(&card->tst_timer, jiffies + 1);
  1404. spin_unlock_irqrestore(&card->tst_lock, flags);
  1405. return res;
  1406. }
  1407. static int
  1408. set_tct(struct idt77252_dev *card, struct vc_map *vc)
  1409. {
  1410. unsigned long tct;
  1411. tct = (unsigned long) (card->tct_base + vc->index * SAR_SRAM_TCT_SIZE);
  1412. switch (vc->class) {
  1413. case SCHED_CBR:
  1414. OPRINTK("%s: writing TCT at 0x%lx, SCD 0x%lx.\n",
  1415. card->name, tct, vc->scq->scd);
  1416. write_sram(card, tct + 0, TCT_CBR | vc->scq->scd);
  1417. write_sram(card, tct + 1, 0);
  1418. write_sram(card, tct + 2, 0);
  1419. write_sram(card, tct + 3, 0);
  1420. write_sram(card, tct + 4, 0);
  1421. write_sram(card, tct + 5, 0);
  1422. write_sram(card, tct + 6, 0);
  1423. write_sram(card, tct + 7, 0);
  1424. break;
  1425. case SCHED_UBR:
  1426. OPRINTK("%s: writing TCT at 0x%lx, SCD 0x%lx.\n",
  1427. card->name, tct, vc->scq->scd);
  1428. write_sram(card, tct + 0, TCT_UBR | vc->scq->scd);
  1429. write_sram(card, tct + 1, 0);
  1430. write_sram(card, tct + 2, TCT_TSIF);
  1431. write_sram(card, tct + 3, TCT_HALT | TCT_IDLE);
  1432. write_sram(card, tct + 4, 0);
  1433. write_sram(card, tct + 5, vc->init_er);
  1434. write_sram(card, tct + 6, 0);
  1435. write_sram(card, tct + 7, TCT_FLAG_UBR);
  1436. break;
  1437. case SCHED_VBR:
  1438. case SCHED_ABR:
  1439. default:
  1440. return -ENOSYS;
  1441. }
  1442. return 0;
  1443. }
  1444. /*****************************************************************************/
  1445. /* */
  1446. /* FBQ Handling */
  1447. /* */
  1448. /*****************************************************************************/
  1449. static __inline__ int
  1450. idt77252_fbq_level(struct idt77252_dev *card, int queue)
  1451. {
  1452. return (readl(SAR_REG_STAT) >> (16 + (queue << 2))) & 0x0f;
  1453. }
  1454. static __inline__ int
  1455. idt77252_fbq_full(struct idt77252_dev *card, int queue)
  1456. {
  1457. return (readl(SAR_REG_STAT) >> (16 + (queue << 2))) == 0x0f;
  1458. }
  1459. static int
  1460. push_rx_skb(struct idt77252_dev *card, struct sk_buff *skb, int queue)
  1461. {
  1462. unsigned long flags;
  1463. u32 handle;
  1464. u32 addr;
  1465. skb->data = skb->head;
  1466. skb_reset_tail_pointer(skb);
  1467. skb->len = 0;
  1468. skb_reserve(skb, 16);
  1469. switch (queue) {
  1470. case 0:
  1471. skb_put(skb, SAR_FB_SIZE_0);
  1472. break;
  1473. case 1:
  1474. skb_put(skb, SAR_FB_SIZE_1);
  1475. break;
  1476. case 2:
  1477. skb_put(skb, SAR_FB_SIZE_2);
  1478. break;
  1479. case 3:
  1480. skb_put(skb, SAR_FB_SIZE_3);
  1481. break;
  1482. default:
  1483. return -1;
  1484. }
  1485. if (idt77252_fbq_full(card, queue))
  1486. return -1;
  1487. memset(&skb->data[(skb->len & ~(0x3f)) - 64], 0, 2 * sizeof(u32));
  1488. handle = IDT77252_PRV_POOL(skb);
  1489. addr = IDT77252_PRV_PADDR(skb);
  1490. spin_lock_irqsave(&card->cmd_lock, flags);
  1491. writel(handle, card->fbq[queue]);
  1492. writel(addr, card->fbq[queue]);
  1493. spin_unlock_irqrestore(&card->cmd_lock, flags);
  1494. return 0;
  1495. }
  1496. static void
  1497. add_rx_skb(struct idt77252_dev *card, int queue,
  1498. unsigned int size, unsigned int count)
  1499. {
  1500. struct sk_buff *skb;
  1501. dma_addr_t paddr;
  1502. u32 handle;
  1503. while (count--) {
  1504. skb = dev_alloc_skb(size);
  1505. if (!skb)
  1506. return;
  1507. if (sb_pool_add(card, skb, queue)) {
  1508. printk("%s: SB POOL full\n", __func__);
  1509. goto outfree;
  1510. }
  1511. paddr = dma_map_single(&card->pcidev->dev, skb->data,
  1512. skb_end_pointer(skb) - skb->data,
  1513. DMA_FROM_DEVICE);
  1514. IDT77252_PRV_PADDR(skb) = paddr;
  1515. if (push_rx_skb(card, skb, queue)) {
  1516. printk("%s: FB QUEUE full\n", __func__);
  1517. goto outunmap;
  1518. }
  1519. }
  1520. return;
  1521. outunmap:
  1522. dma_unmap_single(&card->pcidev->dev, IDT77252_PRV_PADDR(skb),
  1523. skb_end_pointer(skb) - skb->data, DMA_FROM_DEVICE);
  1524. handle = IDT77252_PRV_POOL(skb);
  1525. card->sbpool[POOL_QUEUE(handle)].skb[POOL_INDEX(handle)] = NULL;
  1526. outfree:
  1527. dev_kfree_skb(skb);
  1528. }
  1529. static void
  1530. recycle_rx_skb(struct idt77252_dev *card, struct sk_buff *skb)
  1531. {
  1532. u32 handle = IDT77252_PRV_POOL(skb);
  1533. int err;
  1534. dma_sync_single_for_device(&card->pcidev->dev, IDT77252_PRV_PADDR(skb),
  1535. skb_end_pointer(skb) - skb->data,
  1536. DMA_FROM_DEVICE);
  1537. err = push_rx_skb(card, skb, POOL_QUEUE(handle));
  1538. if (err) {
  1539. dma_unmap_single(&card->pcidev->dev, IDT77252_PRV_PADDR(skb),
  1540. skb_end_pointer(skb) - skb->data,
  1541. DMA_FROM_DEVICE);
  1542. sb_pool_remove(card, skb);
  1543. dev_kfree_skb(skb);
  1544. }
  1545. }
  1546. static void
  1547. flush_rx_pool(struct idt77252_dev *card, struct rx_pool *rpp)
  1548. {
  1549. skb_queue_head_init(&rpp->queue);
  1550. rpp->len = 0;
  1551. }
  1552. static void
  1553. recycle_rx_pool_skb(struct idt77252_dev *card, struct rx_pool *rpp)
  1554. {
  1555. struct sk_buff *skb, *tmp;
  1556. skb_queue_walk_safe(&rpp->queue, skb, tmp)
  1557. recycle_rx_skb(card, skb);
  1558. flush_rx_pool(card, rpp);
  1559. }
  1560. /*****************************************************************************/
  1561. /* */
  1562. /* ATM Interface */
  1563. /* */
  1564. /*****************************************************************************/
  1565. static void
  1566. idt77252_phy_put(struct atm_dev *dev, unsigned char value, unsigned long addr)
  1567. {
  1568. write_utility(dev->dev_data, 0x100 + (addr & 0x1ff), value);
  1569. }
  1570. static unsigned char
  1571. idt77252_phy_get(struct atm_dev *dev, unsigned long addr)
  1572. {
  1573. return read_utility(dev->dev_data, 0x100 + (addr & 0x1ff));
  1574. }
  1575. static inline int
  1576. idt77252_send_skb(struct atm_vcc *vcc, struct sk_buff *skb, int oam)
  1577. {
  1578. struct atm_dev *dev = vcc->dev;
  1579. struct idt77252_dev *card = dev->dev_data;
  1580. struct vc_map *vc = vcc->dev_data;
  1581. int err;
  1582. if (vc == NULL) {
  1583. printk("%s: NULL connection in send().\n", card->name);
  1584. atomic_inc(&vcc->stats->tx_err);
  1585. dev_kfree_skb(skb);
  1586. return -EINVAL;
  1587. }
  1588. if (!test_bit(VCF_TX, &vc->flags)) {
  1589. printk("%s: Trying to transmit on a non-tx VC.\n", card->name);
  1590. atomic_inc(&vcc->stats->tx_err);
  1591. dev_kfree_skb(skb);
  1592. return -EINVAL;
  1593. }
  1594. switch (vcc->qos.aal) {
  1595. case ATM_AAL0:
  1596. case ATM_AAL1:
  1597. case ATM_AAL5:
  1598. break;
  1599. default:
  1600. printk("%s: Unsupported AAL: %d\n", card->name, vcc->qos.aal);
  1601. atomic_inc(&vcc->stats->tx_err);
  1602. dev_kfree_skb(skb);
  1603. return -EINVAL;
  1604. }
  1605. if (skb_shinfo(skb)->nr_frags != 0) {
  1606. printk("%s: No scatter-gather yet.\n", card->name);
  1607. atomic_inc(&vcc->stats->tx_err);
  1608. dev_kfree_skb(skb);
  1609. return -EINVAL;
  1610. }
  1611. ATM_SKB(skb)->vcc = vcc;
  1612. err = queue_skb(card, vc, skb, oam);
  1613. if (err) {
  1614. atomic_inc(&vcc->stats->tx_err);
  1615. dev_kfree_skb(skb);
  1616. return err;
  1617. }
  1618. return 0;
  1619. }
  1620. static int idt77252_send(struct atm_vcc *vcc, struct sk_buff *skb)
  1621. {
  1622. return idt77252_send_skb(vcc, skb, 0);
  1623. }
  1624. static int
  1625. idt77252_send_oam(struct atm_vcc *vcc, void *cell, int flags)
  1626. {
  1627. struct atm_dev *dev = vcc->dev;
  1628. struct idt77252_dev *card = dev->dev_data;
  1629. struct sk_buff *skb;
  1630. skb = dev_alloc_skb(64);
  1631. if (!skb) {
  1632. printk("%s: Out of memory in send_oam().\n", card->name);
  1633. atomic_inc(&vcc->stats->tx_err);
  1634. return -ENOMEM;
  1635. }
  1636. refcount_add(skb->truesize, &sk_atm(vcc)->sk_wmem_alloc);
  1637. skb_put_data(skb, cell, 52);
  1638. return idt77252_send_skb(vcc, skb, 1);
  1639. }
  1640. static __inline__ unsigned int
  1641. idt77252_fls(unsigned int x)
  1642. {
  1643. int r = 1;
  1644. if (x == 0)
  1645. return 0;
  1646. if (x & 0xffff0000) {
  1647. x >>= 16;
  1648. r += 16;
  1649. }
  1650. if (x & 0xff00) {
  1651. x >>= 8;
  1652. r += 8;
  1653. }
  1654. if (x & 0xf0) {
  1655. x >>= 4;
  1656. r += 4;
  1657. }
  1658. if (x & 0xc) {
  1659. x >>= 2;
  1660. r += 2;
  1661. }
  1662. if (x & 0x2)
  1663. r += 1;
  1664. return r;
  1665. }
  1666. static u16
  1667. idt77252_int_to_atmfp(unsigned int rate)
  1668. {
  1669. u16 m, e;
  1670. if (rate == 0)
  1671. return 0;
  1672. e = idt77252_fls(rate) - 1;
  1673. if (e < 9)
  1674. m = (rate - (1 << e)) << (9 - e);
  1675. else if (e == 9)
  1676. m = (rate - (1 << e));
  1677. else /* e > 9 */
  1678. m = (rate - (1 << e)) >> (e - 9);
  1679. return 0x4000 | (e << 9) | m;
  1680. }
  1681. static u8
  1682. idt77252_rate_logindex(struct idt77252_dev *card, int pcr)
  1683. {
  1684. u16 afp;
  1685. afp = idt77252_int_to_atmfp(pcr < 0 ? -pcr : pcr);
  1686. if (pcr < 0)
  1687. return rate_to_log[(afp >> 5) & 0x1ff];
  1688. return rate_to_log[((afp >> 5) + 1) & 0x1ff];
  1689. }
  1690. static void
  1691. idt77252_est_timer(struct timer_list *t)
  1692. {
  1693. struct rate_estimator *est = from_timer(est, t, timer);
  1694. struct vc_map *vc = est->vc;
  1695. struct idt77252_dev *card = vc->card;
  1696. unsigned long flags;
  1697. u32 rate, cps;
  1698. u64 ncells;
  1699. u8 lacr;
  1700. spin_lock_irqsave(&vc->lock, flags);
  1701. if (!vc->estimator)
  1702. goto out;
  1703. ncells = est->cells;
  1704. rate = ((u32)(ncells - est->last_cells)) << (7 - est->interval);
  1705. est->last_cells = ncells;
  1706. est->avcps += ((long)rate - (long)est->avcps) >> est->ewma_log;
  1707. est->cps = (est->avcps + 0x1f) >> 5;
  1708. cps = est->cps;
  1709. if (cps < (est->maxcps >> 4))
  1710. cps = est->maxcps >> 4;
  1711. lacr = idt77252_rate_logindex(card, cps);
  1712. if (lacr > vc->max_er)
  1713. lacr = vc->max_er;
  1714. if (lacr != vc->lacr) {
  1715. vc->lacr = lacr;
  1716. writel(TCMDQ_LACR|(vc->lacr << 16)|vc->index, SAR_REG_TCMDQ);
  1717. }
  1718. est->timer.expires = jiffies + ((HZ / 4) << est->interval);
  1719. add_timer(&est->timer);
  1720. out:
  1721. spin_unlock_irqrestore(&vc->lock, flags);
  1722. }
  1723. static struct rate_estimator *
  1724. idt77252_init_est(struct vc_map *vc, int pcr)
  1725. {
  1726. struct rate_estimator *est;
  1727. est = kzalloc(sizeof(struct rate_estimator), GFP_KERNEL);
  1728. if (!est)
  1729. return NULL;
  1730. est->maxcps = pcr < 0 ? -pcr : pcr;
  1731. est->cps = est->maxcps;
  1732. est->avcps = est->cps << 5;
  1733. est->vc = vc;
  1734. est->interval = 2; /* XXX: make this configurable */
  1735. est->ewma_log = 2; /* XXX: make this configurable */
  1736. timer_setup(&est->timer, idt77252_est_timer, 0);
  1737. mod_timer(&est->timer, jiffies + ((HZ / 4) << est->interval));
  1738. return est;
  1739. }
  1740. static int
  1741. idt77252_init_cbr(struct idt77252_dev *card, struct vc_map *vc,
  1742. struct atm_vcc *vcc, struct atm_qos *qos)
  1743. {
  1744. int tst_free, tst_used, tst_entries;
  1745. unsigned long tmpl, modl;
  1746. int tcr, tcra;
  1747. if ((qos->txtp.max_pcr == 0) &&
  1748. (qos->txtp.pcr == 0) && (qos->txtp.min_pcr == 0)) {
  1749. printk("%s: trying to open a CBR VC with cell rate = 0\n",
  1750. card->name);
  1751. return -EINVAL;
  1752. }
  1753. tst_used = 0;
  1754. tst_free = card->tst_free;
  1755. if (test_bit(VCF_TX, &vc->flags))
  1756. tst_used = vc->ntste;
  1757. tst_free += tst_used;
  1758. tcr = atm_pcr_goal(&qos->txtp);
  1759. tcra = tcr >= 0 ? tcr : -tcr;
  1760. TXPRINTK("%s: CBR target cell rate = %d\n", card->name, tcra);
  1761. tmpl = (unsigned long) tcra * ((unsigned long) card->tst_size - 2);
  1762. modl = tmpl % (unsigned long)card->utopia_pcr;
  1763. tst_entries = (int) (tmpl / card->utopia_pcr);
  1764. if (tcr > 0) {
  1765. if (modl > 0)
  1766. tst_entries++;
  1767. } else if (tcr == 0) {
  1768. tst_entries = tst_free - SAR_TST_RESERVED;
  1769. if (tst_entries <= 0) {
  1770. printk("%s: no CBR bandwidth free.\n", card->name);
  1771. return -ENOSR;
  1772. }
  1773. }
  1774. if (tst_entries == 0) {
  1775. printk("%s: selected CBR bandwidth < granularity.\n",
  1776. card->name);
  1777. return -EINVAL;
  1778. }
  1779. if (tst_entries > (tst_free - SAR_TST_RESERVED)) {
  1780. printk("%s: not enough CBR bandwidth free.\n", card->name);
  1781. return -ENOSR;
  1782. }
  1783. vc->ntste = tst_entries;
  1784. card->tst_free = tst_free - tst_entries;
  1785. if (test_bit(VCF_TX, &vc->flags)) {
  1786. if (tst_used == tst_entries)
  1787. return 0;
  1788. OPRINTK("%s: modify %d -> %d entries in TST.\n",
  1789. card->name, tst_used, tst_entries);
  1790. change_tst(card, vc, tst_entries, TSTE_OPC_CBR);
  1791. return 0;
  1792. }
  1793. OPRINTK("%s: setting %d entries in TST.\n", card->name, tst_entries);
  1794. fill_tst(card, vc, tst_entries, TSTE_OPC_CBR);
  1795. return 0;
  1796. }
  1797. static int
  1798. idt77252_init_ubr(struct idt77252_dev *card, struct vc_map *vc,
  1799. struct atm_vcc *vcc, struct atm_qos *qos)
  1800. {
  1801. struct rate_estimator *est = NULL;
  1802. unsigned long flags;
  1803. int tcr;
  1804. spin_lock_irqsave(&vc->lock, flags);
  1805. if (vc->estimator) {
  1806. est = vc->estimator;
  1807. vc->estimator = NULL;
  1808. }
  1809. spin_unlock_irqrestore(&vc->lock, flags);
  1810. if (est) {
  1811. del_timer_sync(&est->timer);
  1812. kfree(est);
  1813. }
  1814. tcr = atm_pcr_goal(&qos->txtp);
  1815. if (tcr == 0)
  1816. tcr = card->link_pcr;
  1817. vc->estimator = idt77252_init_est(vc, tcr);
  1818. vc->class = SCHED_UBR;
  1819. vc->init_er = idt77252_rate_logindex(card, tcr);
  1820. vc->lacr = vc->init_er;
  1821. if (tcr < 0)
  1822. vc->max_er = vc->init_er;
  1823. else
  1824. vc->max_er = 0xff;
  1825. return 0;
  1826. }
  1827. static int
  1828. idt77252_init_tx(struct idt77252_dev *card, struct vc_map *vc,
  1829. struct atm_vcc *vcc, struct atm_qos *qos)
  1830. {
  1831. int error;
  1832. if (test_bit(VCF_TX, &vc->flags))
  1833. return -EBUSY;
  1834. switch (qos->txtp.traffic_class) {
  1835. case ATM_CBR:
  1836. vc->class = SCHED_CBR;
  1837. break;
  1838. case ATM_UBR:
  1839. vc->class = SCHED_UBR;
  1840. break;
  1841. case ATM_VBR:
  1842. case ATM_ABR:
  1843. default:
  1844. return -EPROTONOSUPPORT;
  1845. }
  1846. vc->scq = alloc_scq(card, vc->class);
  1847. if (!vc->scq) {
  1848. printk("%s: can't get SCQ.\n", card->name);
  1849. return -ENOMEM;
  1850. }
  1851. vc->scq->scd = get_free_scd(card, vc);
  1852. if (vc->scq->scd == 0) {
  1853. printk("%s: no SCD available.\n", card->name);
  1854. free_scq(card, vc->scq);
  1855. return -ENOMEM;
  1856. }
  1857. fill_scd(card, vc->scq, vc->class);
  1858. if (set_tct(card, vc)) {
  1859. printk("%s: class %d not supported.\n",
  1860. card->name, qos->txtp.traffic_class);
  1861. card->scd2vc[vc->scd_index] = NULL;
  1862. free_scq(card, vc->scq);
  1863. return -EPROTONOSUPPORT;
  1864. }
  1865. switch (vc->class) {
  1866. case SCHED_CBR:
  1867. error = idt77252_init_cbr(card, vc, vcc, qos);
  1868. if (error) {
  1869. card->scd2vc[vc->scd_index] = NULL;
  1870. free_scq(card, vc->scq);
  1871. return error;
  1872. }
  1873. clear_bit(VCF_IDLE, &vc->flags);
  1874. writel(TCMDQ_START | vc->index, SAR_REG_TCMDQ);
  1875. break;
  1876. case SCHED_UBR:
  1877. error = idt77252_init_ubr(card, vc, vcc, qos);
  1878. if (error) {
  1879. card->scd2vc[vc->scd_index] = NULL;
  1880. free_scq(card, vc->scq);
  1881. return error;
  1882. }
  1883. set_bit(VCF_IDLE, &vc->flags);
  1884. break;
  1885. }
  1886. vc->tx_vcc = vcc;
  1887. set_bit(VCF_TX, &vc->flags);
  1888. return 0;
  1889. }
  1890. static int
  1891. idt77252_init_rx(struct idt77252_dev *card, struct vc_map *vc,
  1892. struct atm_vcc *vcc, struct atm_qos *qos)
  1893. {
  1894. unsigned long flags;
  1895. unsigned long addr;
  1896. u32 rcte = 0;
  1897. if (test_bit(VCF_RX, &vc->flags))
  1898. return -EBUSY;
  1899. vc->rx_vcc = vcc;
  1900. set_bit(VCF_RX, &vc->flags);
  1901. if ((vcc->vci == 3) || (vcc->vci == 4))
  1902. return 0;
  1903. flush_rx_pool(card, &vc->rcv.rx_pool);
  1904. rcte |= SAR_RCTE_CONNECTOPEN;
  1905. rcte |= SAR_RCTE_RAWCELLINTEN;
  1906. switch (qos->aal) {
  1907. case ATM_AAL0:
  1908. rcte |= SAR_RCTE_RCQ;
  1909. break;
  1910. case ATM_AAL1:
  1911. rcte |= SAR_RCTE_OAM; /* Let SAR drop Video */
  1912. break;
  1913. case ATM_AAL34:
  1914. rcte |= SAR_RCTE_AAL34;
  1915. break;
  1916. case ATM_AAL5:
  1917. rcte |= SAR_RCTE_AAL5;
  1918. break;
  1919. default:
  1920. rcte |= SAR_RCTE_RCQ;
  1921. break;
  1922. }
  1923. if (qos->aal != ATM_AAL5)
  1924. rcte |= SAR_RCTE_FBP_1;
  1925. else if (qos->rxtp.max_sdu > SAR_FB_SIZE_2)
  1926. rcte |= SAR_RCTE_FBP_3;
  1927. else if (qos->rxtp.max_sdu > SAR_FB_SIZE_1)
  1928. rcte |= SAR_RCTE_FBP_2;
  1929. else if (qos->rxtp.max_sdu > SAR_FB_SIZE_0)
  1930. rcte |= SAR_RCTE_FBP_1;
  1931. else
  1932. rcte |= SAR_RCTE_FBP_01;
  1933. addr = card->rct_base + (vc->index << 2);
  1934. OPRINTK("%s: writing RCT at 0x%lx\n", card->name, addr);
  1935. write_sram(card, addr, rcte);
  1936. spin_lock_irqsave(&card->cmd_lock, flags);
  1937. writel(SAR_CMD_OPEN_CONNECTION | (addr << 2), SAR_REG_CMD);
  1938. waitfor_idle(card);
  1939. spin_unlock_irqrestore(&card->cmd_lock, flags);
  1940. return 0;
  1941. }
  1942. static int
  1943. idt77252_open(struct atm_vcc *vcc)
  1944. {
  1945. struct atm_dev *dev = vcc->dev;
  1946. struct idt77252_dev *card = dev->dev_data;
  1947. struct vc_map *vc;
  1948. unsigned int index;
  1949. unsigned int inuse;
  1950. int error;
  1951. int vci = vcc->vci;
  1952. short vpi = vcc->vpi;
  1953. if (vpi == ATM_VPI_UNSPEC || vci == ATM_VCI_UNSPEC)
  1954. return 0;
  1955. if (vpi >= (1 << card->vpibits)) {
  1956. printk("%s: unsupported VPI: %d\n", card->name, vpi);
  1957. return -EINVAL;
  1958. }
  1959. if (vci >= (1 << card->vcibits)) {
  1960. printk("%s: unsupported VCI: %d\n", card->name, vci);
  1961. return -EINVAL;
  1962. }
  1963. set_bit(ATM_VF_ADDR, &vcc->flags);
  1964. mutex_lock(&card->mutex);
  1965. OPRINTK("%s: opening vpi.vci: %d.%d\n", card->name, vpi, vci);
  1966. switch (vcc->qos.aal) {
  1967. case ATM_AAL0:
  1968. case ATM_AAL1:
  1969. case ATM_AAL5:
  1970. break;
  1971. default:
  1972. printk("%s: Unsupported AAL: %d\n", card->name, vcc->qos.aal);
  1973. mutex_unlock(&card->mutex);
  1974. return -EPROTONOSUPPORT;
  1975. }
  1976. index = VPCI2VC(card, vpi, vci);
  1977. if (!card->vcs[index]) {
  1978. card->vcs[index] = kzalloc(sizeof(struct vc_map), GFP_KERNEL);
  1979. if (!card->vcs[index]) {
  1980. printk("%s: can't alloc vc in open()\n", card->name);
  1981. mutex_unlock(&card->mutex);
  1982. return -ENOMEM;
  1983. }
  1984. card->vcs[index]->card = card;
  1985. card->vcs[index]->index = index;
  1986. spin_lock_init(&card->vcs[index]->lock);
  1987. }
  1988. vc = card->vcs[index];
  1989. vcc->dev_data = vc;
  1990. IPRINTK("%s: idt77252_open: vc = %d (%d.%d) %s/%s (max RX SDU: %u)\n",
  1991. card->name, vc->index, vcc->vpi, vcc->vci,
  1992. vcc->qos.rxtp.traffic_class != ATM_NONE ? "rx" : "--",
  1993. vcc->qos.txtp.traffic_class != ATM_NONE ? "tx" : "--",
  1994. vcc->qos.rxtp.max_sdu);
  1995. inuse = 0;
  1996. if (vcc->qos.txtp.traffic_class != ATM_NONE &&
  1997. test_bit(VCF_TX, &vc->flags))
  1998. inuse = 1;
  1999. if (vcc->qos.rxtp.traffic_class != ATM_NONE &&
  2000. test_bit(VCF_RX, &vc->flags))
  2001. inuse += 2;
  2002. if (inuse) {
  2003. printk("%s: %s vci already in use.\n", card->name,
  2004. inuse == 1 ? "tx" : inuse == 2 ? "rx" : "tx and rx");
  2005. mutex_unlock(&card->mutex);
  2006. return -EADDRINUSE;
  2007. }
  2008. if (vcc->qos.txtp.traffic_class != ATM_NONE) {
  2009. error = idt77252_init_tx(card, vc, vcc, &vcc->qos);
  2010. if (error) {
  2011. mutex_unlock(&card->mutex);
  2012. return error;
  2013. }
  2014. }
  2015. if (vcc->qos.rxtp.traffic_class != ATM_NONE) {
  2016. error = idt77252_init_rx(card, vc, vcc, &vcc->qos);
  2017. if (error) {
  2018. mutex_unlock(&card->mutex);
  2019. return error;
  2020. }
  2021. }
  2022. set_bit(ATM_VF_READY, &vcc->flags);
  2023. mutex_unlock(&card->mutex);
  2024. return 0;
  2025. }
  2026. static void
  2027. idt77252_close(struct atm_vcc *vcc)
  2028. {
  2029. struct atm_dev *dev = vcc->dev;
  2030. struct idt77252_dev *card = dev->dev_data;
  2031. struct vc_map *vc = vcc->dev_data;
  2032. unsigned long flags;
  2033. unsigned long addr;
  2034. unsigned long timeout;
  2035. mutex_lock(&card->mutex);
  2036. IPRINTK("%s: idt77252_close: vc = %d (%d.%d)\n",
  2037. card->name, vc->index, vcc->vpi, vcc->vci);
  2038. clear_bit(ATM_VF_READY, &vcc->flags);
  2039. if (vcc->qos.rxtp.traffic_class != ATM_NONE) {
  2040. spin_lock_irqsave(&vc->lock, flags);
  2041. clear_bit(VCF_RX, &vc->flags);
  2042. vc->rx_vcc = NULL;
  2043. spin_unlock_irqrestore(&vc->lock, flags);
  2044. if ((vcc->vci == 3) || (vcc->vci == 4))
  2045. goto done;
  2046. addr = card->rct_base + vc->index * SAR_SRAM_RCT_SIZE;
  2047. spin_lock_irqsave(&card->cmd_lock, flags);
  2048. writel(SAR_CMD_CLOSE_CONNECTION | (addr << 2), SAR_REG_CMD);
  2049. waitfor_idle(card);
  2050. spin_unlock_irqrestore(&card->cmd_lock, flags);
  2051. if (skb_queue_len(&vc->rcv.rx_pool.queue) != 0) {
  2052. DPRINTK("%s: closing a VC with pending rx buffers.\n",
  2053. card->name);
  2054. recycle_rx_pool_skb(card, &vc->rcv.rx_pool);
  2055. }
  2056. }
  2057. done:
  2058. if (vcc->qos.txtp.traffic_class != ATM_NONE) {
  2059. spin_lock_irqsave(&vc->lock, flags);
  2060. clear_bit(VCF_TX, &vc->flags);
  2061. clear_bit(VCF_IDLE, &vc->flags);
  2062. clear_bit(VCF_RSV, &vc->flags);
  2063. vc->tx_vcc = NULL;
  2064. if (vc->estimator) {
  2065. del_timer(&vc->estimator->timer);
  2066. kfree(vc->estimator);
  2067. vc->estimator = NULL;
  2068. }
  2069. spin_unlock_irqrestore(&vc->lock, flags);
  2070. timeout = 5 * 1000;
  2071. while (atomic_read(&vc->scq->used) > 0) {
  2072. timeout = msleep_interruptible(timeout);
  2073. if (!timeout) {
  2074. pr_warn("%s: SCQ drain timeout: %u used\n",
  2075. card->name, atomic_read(&vc->scq->used));
  2076. break;
  2077. }
  2078. }
  2079. writel(TCMDQ_HALT | vc->index, SAR_REG_TCMDQ);
  2080. clear_scd(card, vc->scq, vc->class);
  2081. if (vc->class == SCHED_CBR) {
  2082. clear_tst(card, vc);
  2083. card->tst_free += vc->ntste;
  2084. vc->ntste = 0;
  2085. }
  2086. card->scd2vc[vc->scd_index] = NULL;
  2087. free_scq(card, vc->scq);
  2088. }
  2089. mutex_unlock(&card->mutex);
  2090. }
  2091. static int
  2092. idt77252_change_qos(struct atm_vcc *vcc, struct atm_qos *qos, int flags)
  2093. {
  2094. struct atm_dev *dev = vcc->dev;
  2095. struct idt77252_dev *card = dev->dev_data;
  2096. struct vc_map *vc = vcc->dev_data;
  2097. int error = 0;
  2098. mutex_lock(&card->mutex);
  2099. if (qos->txtp.traffic_class != ATM_NONE) {
  2100. if (!test_bit(VCF_TX, &vc->flags)) {
  2101. error = idt77252_init_tx(card, vc, vcc, qos);
  2102. if (error)
  2103. goto out;
  2104. } else {
  2105. switch (qos->txtp.traffic_class) {
  2106. case ATM_CBR:
  2107. error = idt77252_init_cbr(card, vc, vcc, qos);
  2108. if (error)
  2109. goto out;
  2110. break;
  2111. case ATM_UBR:
  2112. error = idt77252_init_ubr(card, vc, vcc, qos);
  2113. if (error)
  2114. goto out;
  2115. if (!test_bit(VCF_IDLE, &vc->flags)) {
  2116. writel(TCMDQ_LACR | (vc->lacr << 16) |
  2117. vc->index, SAR_REG_TCMDQ);
  2118. }
  2119. break;
  2120. case ATM_VBR:
  2121. case ATM_ABR:
  2122. error = -EOPNOTSUPP;
  2123. goto out;
  2124. }
  2125. }
  2126. }
  2127. if ((qos->rxtp.traffic_class != ATM_NONE) &&
  2128. !test_bit(VCF_RX, &vc->flags)) {
  2129. error = idt77252_init_rx(card, vc, vcc, qos);
  2130. if (error)
  2131. goto out;
  2132. }
  2133. memcpy(&vcc->qos, qos, sizeof(struct atm_qos));
  2134. set_bit(ATM_VF_HASQOS, &vcc->flags);
  2135. out:
  2136. mutex_unlock(&card->mutex);
  2137. return error;
  2138. }
  2139. static int
  2140. idt77252_proc_read(struct atm_dev *dev, loff_t * pos, char *page)
  2141. {
  2142. struct idt77252_dev *card = dev->dev_data;
  2143. int i, left;
  2144. left = (int) *pos;
  2145. if (!left--)
  2146. return sprintf(page, "IDT77252 Interrupts:\n");
  2147. if (!left--)
  2148. return sprintf(page, "TSIF: %lu\n", card->irqstat[15]);
  2149. if (!left--)
  2150. return sprintf(page, "TXICP: %lu\n", card->irqstat[14]);
  2151. if (!left--)
  2152. return sprintf(page, "TSQF: %lu\n", card->irqstat[12]);
  2153. if (!left--)
  2154. return sprintf(page, "TMROF: %lu\n", card->irqstat[11]);
  2155. if (!left--)
  2156. return sprintf(page, "PHYI: %lu\n", card->irqstat[10]);
  2157. if (!left--)
  2158. return sprintf(page, "FBQ3A: %lu\n", card->irqstat[8]);
  2159. if (!left--)
  2160. return sprintf(page, "FBQ2A: %lu\n", card->irqstat[7]);
  2161. if (!left--)
  2162. return sprintf(page, "RSQF: %lu\n", card->irqstat[6]);
  2163. if (!left--)
  2164. return sprintf(page, "EPDU: %lu\n", card->irqstat[5]);
  2165. if (!left--)
  2166. return sprintf(page, "RAWCF: %lu\n", card->irqstat[4]);
  2167. if (!left--)
  2168. return sprintf(page, "FBQ1A: %lu\n", card->irqstat[3]);
  2169. if (!left--)
  2170. return sprintf(page, "FBQ0A: %lu\n", card->irqstat[2]);
  2171. if (!left--)
  2172. return sprintf(page, "RSQAF: %lu\n", card->irqstat[1]);
  2173. if (!left--)
  2174. return sprintf(page, "IDT77252 Transmit Connection Table:\n");
  2175. for (i = 0; i < card->tct_size; i++) {
  2176. unsigned long tct;
  2177. struct atm_vcc *vcc;
  2178. struct vc_map *vc;
  2179. char *p;
  2180. vc = card->vcs[i];
  2181. if (!vc)
  2182. continue;
  2183. vcc = NULL;
  2184. if (vc->tx_vcc)
  2185. vcc = vc->tx_vcc;
  2186. if (!vcc)
  2187. continue;
  2188. if (left--)
  2189. continue;
  2190. p = page;
  2191. p += sprintf(p, " %4u: %u.%u: ", i, vcc->vpi, vcc->vci);
  2192. tct = (unsigned long) (card->tct_base + i * SAR_SRAM_TCT_SIZE);
  2193. for (i = 0; i < 8; i++)
  2194. p += sprintf(p, " %08x", read_sram(card, tct + i));
  2195. p += sprintf(p, "\n");
  2196. return p - page;
  2197. }
  2198. return 0;
  2199. }
  2200. /*****************************************************************************/
  2201. /* */
  2202. /* Interrupt handler */
  2203. /* */
  2204. /*****************************************************************************/
  2205. static void
  2206. idt77252_collect_stat(struct idt77252_dev *card)
  2207. {
  2208. (void) readl(SAR_REG_CDC);
  2209. (void) readl(SAR_REG_VPEC);
  2210. (void) readl(SAR_REG_ICC);
  2211. }
  2212. static irqreturn_t
  2213. idt77252_interrupt(int irq, void *dev_id)
  2214. {
  2215. struct idt77252_dev *card = dev_id;
  2216. u32 stat;
  2217. stat = readl(SAR_REG_STAT) & 0xffff;
  2218. if (!stat) /* no interrupt for us */
  2219. return IRQ_NONE;
  2220. if (test_and_set_bit(IDT77252_BIT_INTERRUPT, &card->flags)) {
  2221. printk("%s: Re-entering irq_handler()\n", card->name);
  2222. goto out;
  2223. }
  2224. writel(stat, SAR_REG_STAT); /* reset interrupt */
  2225. if (stat & SAR_STAT_TSIF) { /* entry written to TSQ */
  2226. INTPRINTK("%s: TSIF\n", card->name);
  2227. card->irqstat[15]++;
  2228. idt77252_tx(card);
  2229. }
  2230. if (stat & SAR_STAT_TXICP) { /* Incomplete CS-PDU has */
  2231. INTPRINTK("%s: TXICP\n", card->name);
  2232. card->irqstat[14]++;
  2233. #ifdef CONFIG_ATM_IDT77252_DEBUG
  2234. idt77252_tx_dump(card);
  2235. #endif
  2236. }
  2237. if (stat & SAR_STAT_TSQF) { /* TSQ 7/8 full */
  2238. INTPRINTK("%s: TSQF\n", card->name);
  2239. card->irqstat[12]++;
  2240. idt77252_tx(card);
  2241. }
  2242. if (stat & SAR_STAT_TMROF) { /* Timer overflow */
  2243. INTPRINTK("%s: TMROF\n", card->name);
  2244. card->irqstat[11]++;
  2245. idt77252_collect_stat(card);
  2246. }
  2247. if (stat & SAR_STAT_EPDU) { /* Got complete CS-PDU */
  2248. INTPRINTK("%s: EPDU\n", card->name);
  2249. card->irqstat[5]++;
  2250. idt77252_rx(card);
  2251. }
  2252. if (stat & SAR_STAT_RSQAF) { /* RSQ is 7/8 full */
  2253. INTPRINTK("%s: RSQAF\n", card->name);
  2254. card->irqstat[1]++;
  2255. idt77252_rx(card);
  2256. }
  2257. if (stat & SAR_STAT_RSQF) { /* RSQ is full */
  2258. INTPRINTK("%s: RSQF\n", card->name);
  2259. card->irqstat[6]++;
  2260. idt77252_rx(card);
  2261. }
  2262. if (stat & SAR_STAT_RAWCF) { /* Raw cell received */
  2263. INTPRINTK("%s: RAWCF\n", card->name);
  2264. card->irqstat[4]++;
  2265. idt77252_rx_raw(card);
  2266. }
  2267. if (stat & SAR_STAT_PHYI) { /* PHY device interrupt */
  2268. INTPRINTK("%s: PHYI", card->name);
  2269. card->irqstat[10]++;
  2270. if (card->atmdev->phy && card->atmdev->phy->interrupt)
  2271. card->atmdev->phy->interrupt(card->atmdev);
  2272. }
  2273. if (stat & (SAR_STAT_FBQ0A | SAR_STAT_FBQ1A |
  2274. SAR_STAT_FBQ2A | SAR_STAT_FBQ3A)) {
  2275. writel(readl(SAR_REG_CFG) & ~(SAR_CFG_FBIE), SAR_REG_CFG);
  2276. INTPRINTK("%s: FBQA: %04x\n", card->name, stat);
  2277. if (stat & SAR_STAT_FBQ0A)
  2278. card->irqstat[2]++;
  2279. if (stat & SAR_STAT_FBQ1A)
  2280. card->irqstat[3]++;
  2281. if (stat & SAR_STAT_FBQ2A)
  2282. card->irqstat[7]++;
  2283. if (stat & SAR_STAT_FBQ3A)
  2284. card->irqstat[8]++;
  2285. schedule_work(&card->tqueue);
  2286. }
  2287. out:
  2288. clear_bit(IDT77252_BIT_INTERRUPT, &card->flags);
  2289. return IRQ_HANDLED;
  2290. }
  2291. static void
  2292. idt77252_softint(struct work_struct *work)
  2293. {
  2294. struct idt77252_dev *card =
  2295. container_of(work, struct idt77252_dev, tqueue);
  2296. u32 stat;
  2297. int done;
  2298. for (done = 1; ; done = 1) {
  2299. stat = readl(SAR_REG_STAT) >> 16;
  2300. if ((stat & 0x0f) < SAR_FBQ0_HIGH) {
  2301. add_rx_skb(card, 0, SAR_FB_SIZE_0, 32);
  2302. done = 0;
  2303. }
  2304. stat >>= 4;
  2305. if ((stat & 0x0f) < SAR_FBQ1_HIGH) {
  2306. add_rx_skb(card, 1, SAR_FB_SIZE_1, 32);
  2307. done = 0;
  2308. }
  2309. stat >>= 4;
  2310. if ((stat & 0x0f) < SAR_FBQ2_HIGH) {
  2311. add_rx_skb(card, 2, SAR_FB_SIZE_2, 32);
  2312. done = 0;
  2313. }
  2314. stat >>= 4;
  2315. if ((stat & 0x0f) < SAR_FBQ3_HIGH) {
  2316. add_rx_skb(card, 3, SAR_FB_SIZE_3, 32);
  2317. done = 0;
  2318. }
  2319. if (done)
  2320. break;
  2321. }
  2322. writel(readl(SAR_REG_CFG) | SAR_CFG_FBIE, SAR_REG_CFG);
  2323. }
  2324. static int
  2325. open_card_oam(struct idt77252_dev *card)
  2326. {
  2327. unsigned long flags;
  2328. unsigned long addr;
  2329. struct vc_map *vc;
  2330. int vpi, vci;
  2331. int index;
  2332. u32 rcte;
  2333. for (vpi = 0; vpi < (1 << card->vpibits); vpi++) {
  2334. for (vci = 3; vci < 5; vci++) {
  2335. index = VPCI2VC(card, vpi, vci);
  2336. vc = kzalloc(sizeof(struct vc_map), GFP_KERNEL);
  2337. if (!vc) {
  2338. printk("%s: can't alloc vc\n", card->name);
  2339. return -ENOMEM;
  2340. }
  2341. vc->index = index;
  2342. card->vcs[index] = vc;
  2343. flush_rx_pool(card, &vc->rcv.rx_pool);
  2344. rcte = SAR_RCTE_CONNECTOPEN |
  2345. SAR_RCTE_RAWCELLINTEN |
  2346. SAR_RCTE_RCQ |
  2347. SAR_RCTE_FBP_1;
  2348. addr = card->rct_base + (vc->index << 2);
  2349. write_sram(card, addr, rcte);
  2350. spin_lock_irqsave(&card->cmd_lock, flags);
  2351. writel(SAR_CMD_OPEN_CONNECTION | (addr << 2),
  2352. SAR_REG_CMD);
  2353. waitfor_idle(card);
  2354. spin_unlock_irqrestore(&card->cmd_lock, flags);
  2355. }
  2356. }
  2357. return 0;
  2358. }
  2359. static void
  2360. close_card_oam(struct idt77252_dev *card)
  2361. {
  2362. unsigned long flags;
  2363. unsigned long addr;
  2364. struct vc_map *vc;
  2365. int vpi, vci;
  2366. int index;
  2367. for (vpi = 0; vpi < (1 << card->vpibits); vpi++) {
  2368. for (vci = 3; vci < 5; vci++) {
  2369. index = VPCI2VC(card, vpi, vci);
  2370. vc = card->vcs[index];
  2371. addr = card->rct_base + vc->index * SAR_SRAM_RCT_SIZE;
  2372. spin_lock_irqsave(&card->cmd_lock, flags);
  2373. writel(SAR_CMD_CLOSE_CONNECTION | (addr << 2),
  2374. SAR_REG_CMD);
  2375. waitfor_idle(card);
  2376. spin_unlock_irqrestore(&card->cmd_lock, flags);
  2377. if (skb_queue_len(&vc->rcv.rx_pool.queue) != 0) {
  2378. DPRINTK("%s: closing a VC "
  2379. "with pending rx buffers.\n",
  2380. card->name);
  2381. recycle_rx_pool_skb(card, &vc->rcv.rx_pool);
  2382. }
  2383. }
  2384. }
  2385. }
  2386. static int
  2387. open_card_ubr0(struct idt77252_dev *card)
  2388. {
  2389. struct vc_map *vc;
  2390. vc = kzalloc(sizeof(struct vc_map), GFP_KERNEL);
  2391. if (!vc) {
  2392. printk("%s: can't alloc vc\n", card->name);
  2393. return -ENOMEM;
  2394. }
  2395. card->vcs[0] = vc;
  2396. vc->class = SCHED_UBR0;
  2397. vc->scq = alloc_scq(card, vc->class);
  2398. if (!vc->scq) {
  2399. printk("%s: can't get SCQ.\n", card->name);
  2400. return -ENOMEM;
  2401. }
  2402. card->scd2vc[0] = vc;
  2403. vc->scd_index = 0;
  2404. vc->scq->scd = card->scd_base;
  2405. fill_scd(card, vc->scq, vc->class);
  2406. write_sram(card, card->tct_base + 0, TCT_UBR | card->scd_base);
  2407. write_sram(card, card->tct_base + 1, 0);
  2408. write_sram(card, card->tct_base + 2, 0);
  2409. write_sram(card, card->tct_base + 3, 0);
  2410. write_sram(card, card->tct_base + 4, 0);
  2411. write_sram(card, card->tct_base + 5, 0);
  2412. write_sram(card, card->tct_base + 6, 0);
  2413. write_sram(card, card->tct_base + 7, TCT_FLAG_UBR);
  2414. clear_bit(VCF_IDLE, &vc->flags);
  2415. writel(TCMDQ_START | 0, SAR_REG_TCMDQ);
  2416. return 0;
  2417. }
  2418. static int
  2419. idt77252_dev_open(struct idt77252_dev *card)
  2420. {
  2421. u32 conf;
  2422. if (!test_bit(IDT77252_BIT_INIT, &card->flags)) {
  2423. printk("%s: SAR not yet initialized.\n", card->name);
  2424. return -1;
  2425. }
  2426. conf = SAR_CFG_RXPTH| /* enable receive path */
  2427. SAR_RX_DELAY | /* interrupt on complete PDU */
  2428. SAR_CFG_RAWIE | /* interrupt enable on raw cells */
  2429. SAR_CFG_RQFIE | /* interrupt on RSQ almost full */
  2430. SAR_CFG_TMOIE | /* interrupt on timer overflow */
  2431. SAR_CFG_FBIE | /* interrupt on low free buffers */
  2432. SAR_CFG_TXEN | /* transmit operation enable */
  2433. SAR_CFG_TXINT | /* interrupt on transmit status */
  2434. SAR_CFG_TXUIE | /* interrupt on transmit underrun */
  2435. SAR_CFG_TXSFI | /* interrupt on TSQ almost full */
  2436. SAR_CFG_PHYIE /* enable PHY interrupts */
  2437. ;
  2438. #ifdef CONFIG_ATM_IDT77252_RCV_ALL
  2439. /* Test RAW cell receive. */
  2440. conf |= SAR_CFG_VPECA;
  2441. #endif
  2442. writel(readl(SAR_REG_CFG) | conf, SAR_REG_CFG);
  2443. if (open_card_oam(card)) {
  2444. printk("%s: Error initializing OAM.\n", card->name);
  2445. return -1;
  2446. }
  2447. if (open_card_ubr0(card)) {
  2448. printk("%s: Error initializing UBR0.\n", card->name);
  2449. return -1;
  2450. }
  2451. IPRINTK("%s: opened IDT77252 ABR SAR.\n", card->name);
  2452. return 0;
  2453. }
  2454. static void idt77252_dev_close(struct atm_dev *dev)
  2455. {
  2456. struct idt77252_dev *card = dev->dev_data;
  2457. u32 conf;
  2458. close_card_oam(card);
  2459. conf = SAR_CFG_RXPTH | /* enable receive path */
  2460. SAR_RX_DELAY | /* interrupt on complete PDU */
  2461. SAR_CFG_RAWIE | /* interrupt enable on raw cells */
  2462. SAR_CFG_RQFIE | /* interrupt on RSQ almost full */
  2463. SAR_CFG_TMOIE | /* interrupt on timer overflow */
  2464. SAR_CFG_FBIE | /* interrupt on low free buffers */
  2465. SAR_CFG_TXEN | /* transmit operation enable */
  2466. SAR_CFG_TXINT | /* interrupt on transmit status */
  2467. SAR_CFG_TXUIE | /* interrupt on xmit underrun */
  2468. SAR_CFG_TXSFI /* interrupt on TSQ almost full */
  2469. ;
  2470. writel(readl(SAR_REG_CFG) & ~(conf), SAR_REG_CFG);
  2471. DIPRINTK("%s: closed IDT77252 ABR SAR.\n", card->name);
  2472. }
  2473. /*****************************************************************************/
  2474. /* */
  2475. /* Initialisation and Deinitialization of IDT77252 */
  2476. /* */
  2477. /*****************************************************************************/
  2478. static void
  2479. deinit_card(struct idt77252_dev *card)
  2480. {
  2481. struct sk_buff *skb;
  2482. int i, j;
  2483. if (!test_bit(IDT77252_BIT_INIT, &card->flags)) {
  2484. printk("%s: SAR not yet initialized.\n", card->name);
  2485. return;
  2486. }
  2487. DIPRINTK("idt77252: deinitialize card %u\n", card->index);
  2488. writel(0, SAR_REG_CFG);
  2489. if (card->atmdev)
  2490. atm_dev_deregister(card->atmdev);
  2491. for (i = 0; i < 4; i++) {
  2492. for (j = 0; j < FBQ_SIZE; j++) {
  2493. skb = card->sbpool[i].skb[j];
  2494. if (skb) {
  2495. dma_unmap_single(&card->pcidev->dev,
  2496. IDT77252_PRV_PADDR(skb),
  2497. (skb_end_pointer(skb) -
  2498. skb->data),
  2499. DMA_FROM_DEVICE);
  2500. card->sbpool[i].skb[j] = NULL;
  2501. dev_kfree_skb(skb);
  2502. }
  2503. }
  2504. }
  2505. vfree(card->soft_tst);
  2506. vfree(card->scd2vc);
  2507. vfree(card->vcs);
  2508. if (card->raw_cell_hnd) {
  2509. dma_free_coherent(&card->pcidev->dev, 2 * sizeof(u32),
  2510. card->raw_cell_hnd, card->raw_cell_paddr);
  2511. }
  2512. if (card->rsq.base) {
  2513. DIPRINTK("%s: Release RSQ ...\n", card->name);
  2514. deinit_rsq(card);
  2515. }
  2516. if (card->tsq.base) {
  2517. DIPRINTK("%s: Release TSQ ...\n", card->name);
  2518. deinit_tsq(card);
  2519. }
  2520. DIPRINTK("idt77252: Release IRQ.\n");
  2521. free_irq(card->pcidev->irq, card);
  2522. for (i = 0; i < 4; i++) {
  2523. if (card->fbq[i])
  2524. iounmap(card->fbq[i]);
  2525. }
  2526. if (card->membase)
  2527. iounmap(card->membase);
  2528. clear_bit(IDT77252_BIT_INIT, &card->flags);
  2529. DIPRINTK("%s: Card deinitialized.\n", card->name);
  2530. }
  2531. static void init_sram(struct idt77252_dev *card)
  2532. {
  2533. int i;
  2534. for (i = 0; i < card->sramsize; i += 4)
  2535. write_sram(card, (i >> 2), 0);
  2536. /* set SRAM layout for THIS card */
  2537. if (card->sramsize == (512 * 1024)) {
  2538. card->tct_base = SAR_SRAM_TCT_128_BASE;
  2539. card->tct_size = (SAR_SRAM_TCT_128_TOP - card->tct_base + 1)
  2540. / SAR_SRAM_TCT_SIZE;
  2541. card->rct_base = SAR_SRAM_RCT_128_BASE;
  2542. card->rct_size = (SAR_SRAM_RCT_128_TOP - card->rct_base + 1)
  2543. / SAR_SRAM_RCT_SIZE;
  2544. card->rt_base = SAR_SRAM_RT_128_BASE;
  2545. card->scd_base = SAR_SRAM_SCD_128_BASE;
  2546. card->scd_size = (SAR_SRAM_SCD_128_TOP - card->scd_base + 1)
  2547. / SAR_SRAM_SCD_SIZE;
  2548. card->tst[0] = SAR_SRAM_TST1_128_BASE;
  2549. card->tst[1] = SAR_SRAM_TST2_128_BASE;
  2550. card->tst_size = SAR_SRAM_TST1_128_TOP - card->tst[0] + 1;
  2551. card->abrst_base = SAR_SRAM_ABRSTD_128_BASE;
  2552. card->abrst_size = SAR_ABRSTD_SIZE_8K;
  2553. card->fifo_base = SAR_SRAM_FIFO_128_BASE;
  2554. card->fifo_size = SAR_RXFD_SIZE_32K;
  2555. } else {
  2556. card->tct_base = SAR_SRAM_TCT_32_BASE;
  2557. card->tct_size = (SAR_SRAM_TCT_32_TOP - card->tct_base + 1)
  2558. / SAR_SRAM_TCT_SIZE;
  2559. card->rct_base = SAR_SRAM_RCT_32_BASE;
  2560. card->rct_size = (SAR_SRAM_RCT_32_TOP - card->rct_base + 1)
  2561. / SAR_SRAM_RCT_SIZE;
  2562. card->rt_base = SAR_SRAM_RT_32_BASE;
  2563. card->scd_base = SAR_SRAM_SCD_32_BASE;
  2564. card->scd_size = (SAR_SRAM_SCD_32_TOP - card->scd_base + 1)
  2565. / SAR_SRAM_SCD_SIZE;
  2566. card->tst[0] = SAR_SRAM_TST1_32_BASE;
  2567. card->tst[1] = SAR_SRAM_TST2_32_BASE;
  2568. card->tst_size = (SAR_SRAM_TST1_32_TOP - card->tst[0] + 1);
  2569. card->abrst_base = SAR_SRAM_ABRSTD_32_BASE;
  2570. card->abrst_size = SAR_ABRSTD_SIZE_1K;
  2571. card->fifo_base = SAR_SRAM_FIFO_32_BASE;
  2572. card->fifo_size = SAR_RXFD_SIZE_4K;
  2573. }
  2574. /* Initialize TCT */
  2575. for (i = 0; i < card->tct_size; i++) {
  2576. write_sram(card, i * SAR_SRAM_TCT_SIZE + 0, 0);
  2577. write_sram(card, i * SAR_SRAM_TCT_SIZE + 1, 0);
  2578. write_sram(card, i * SAR_SRAM_TCT_SIZE + 2, 0);
  2579. write_sram(card, i * SAR_SRAM_TCT_SIZE + 3, 0);
  2580. write_sram(card, i * SAR_SRAM_TCT_SIZE + 4, 0);
  2581. write_sram(card, i * SAR_SRAM_TCT_SIZE + 5, 0);
  2582. write_sram(card, i * SAR_SRAM_TCT_SIZE + 6, 0);
  2583. write_sram(card, i * SAR_SRAM_TCT_SIZE + 7, 0);
  2584. }
  2585. /* Initialize RCT */
  2586. for (i = 0; i < card->rct_size; i++) {
  2587. write_sram(card, card->rct_base + i * SAR_SRAM_RCT_SIZE,
  2588. (u32) SAR_RCTE_RAWCELLINTEN);
  2589. write_sram(card, card->rct_base + i * SAR_SRAM_RCT_SIZE + 1,
  2590. (u32) 0);
  2591. write_sram(card, card->rct_base + i * SAR_SRAM_RCT_SIZE + 2,
  2592. (u32) 0);
  2593. write_sram(card, card->rct_base + i * SAR_SRAM_RCT_SIZE + 3,
  2594. (u32) 0xffffffff);
  2595. }
  2596. writel((SAR_FBQ0_LOW << 28) | (SAR_FB_SIZE_0 / 48), SAR_REG_FBQS0);
  2597. writel((SAR_FBQ1_LOW << 28) | (SAR_FB_SIZE_1 / 48), SAR_REG_FBQS1);
  2598. writel((SAR_FBQ2_LOW << 28) | (SAR_FB_SIZE_2 / 48), SAR_REG_FBQS2);
  2599. writel((SAR_FBQ3_LOW << 28) | (SAR_FB_SIZE_3 / 48), SAR_REG_FBQS3);
  2600. /* Initialize rate table */
  2601. for (i = 0; i < 256; i++) {
  2602. write_sram(card, card->rt_base + i, log_to_rate[i]);
  2603. }
  2604. for (i = 0; i < 128; i++) {
  2605. unsigned int tmp;
  2606. tmp = rate_to_log[(i << 2) + 0] << 0;
  2607. tmp |= rate_to_log[(i << 2) + 1] << 8;
  2608. tmp |= rate_to_log[(i << 2) + 2] << 16;
  2609. tmp |= rate_to_log[(i << 2) + 3] << 24;
  2610. write_sram(card, card->rt_base + 256 + i, tmp);
  2611. }
  2612. #if 0 /* Fill RDF and AIR tables. */
  2613. for (i = 0; i < 128; i++) {
  2614. unsigned int tmp;
  2615. tmp = RDF[0][(i << 1) + 0] << 16;
  2616. tmp |= RDF[0][(i << 1) + 1] << 0;
  2617. write_sram(card, card->rt_base + 512 + i, tmp);
  2618. }
  2619. for (i = 0; i < 128; i++) {
  2620. unsigned int tmp;
  2621. tmp = AIR[0][(i << 1) + 0] << 16;
  2622. tmp |= AIR[0][(i << 1) + 1] << 0;
  2623. write_sram(card, card->rt_base + 640 + i, tmp);
  2624. }
  2625. #endif
  2626. IPRINTK("%s: initialize rate table ...\n", card->name);
  2627. writel(card->rt_base << 2, SAR_REG_RTBL);
  2628. /* Initialize TSTs */
  2629. IPRINTK("%s: initialize TST ...\n", card->name);
  2630. card->tst_free = card->tst_size - 2; /* last two are jumps */
  2631. for (i = card->tst[0]; i < card->tst[0] + card->tst_size - 2; i++)
  2632. write_sram(card, i, TSTE_OPC_VAR);
  2633. write_sram(card, i++, TSTE_OPC_JMP | (card->tst[0] << 2));
  2634. idt77252_sram_write_errors = 1;
  2635. write_sram(card, i++, TSTE_OPC_JMP | (card->tst[1] << 2));
  2636. idt77252_sram_write_errors = 0;
  2637. for (i = card->tst[1]; i < card->tst[1] + card->tst_size - 2; i++)
  2638. write_sram(card, i, TSTE_OPC_VAR);
  2639. write_sram(card, i++, TSTE_OPC_JMP | (card->tst[1] << 2));
  2640. idt77252_sram_write_errors = 1;
  2641. write_sram(card, i++, TSTE_OPC_JMP | (card->tst[0] << 2));
  2642. idt77252_sram_write_errors = 0;
  2643. card->tst_index = 0;
  2644. writel(card->tst[0] << 2, SAR_REG_TSTB);
  2645. /* Initialize ABRSTD and Receive FIFO */
  2646. IPRINTK("%s: initialize ABRSTD ...\n", card->name);
  2647. writel(card->abrst_size | (card->abrst_base << 2),
  2648. SAR_REG_ABRSTD);
  2649. IPRINTK("%s: initialize receive fifo ...\n", card->name);
  2650. writel(card->fifo_size | (card->fifo_base << 2),
  2651. SAR_REG_RXFD);
  2652. IPRINTK("%s: SRAM initialization complete.\n", card->name);
  2653. }
  2654. static int init_card(struct atm_dev *dev)
  2655. {
  2656. struct idt77252_dev *card = dev->dev_data;
  2657. struct pci_dev *pcidev = card->pcidev;
  2658. unsigned long tmpl, modl;
  2659. unsigned int linkrate, rsvdcr;
  2660. unsigned int tst_entries;
  2661. struct net_device *tmp;
  2662. char tname[10];
  2663. u32 size;
  2664. u_char pci_byte;
  2665. u32 conf;
  2666. int i, k;
  2667. if (test_bit(IDT77252_BIT_INIT, &card->flags)) {
  2668. printk("Error: SAR already initialized.\n");
  2669. return -1;
  2670. }
  2671. /*****************************************************************/
  2672. /* P C I C O N F I G U R A T I O N */
  2673. /*****************************************************************/
  2674. /* Set PCI Retry-Timeout and TRDY timeout */
  2675. IPRINTK("%s: Checking PCI retries.\n", card->name);
  2676. if (pci_read_config_byte(pcidev, 0x40, &pci_byte) != 0) {
  2677. printk("%s: can't read PCI retry timeout.\n", card->name);
  2678. deinit_card(card);
  2679. return -1;
  2680. }
  2681. if (pci_byte != 0) {
  2682. IPRINTK("%s: PCI retry timeout: %d, set to 0.\n",
  2683. card->name, pci_byte);
  2684. if (pci_write_config_byte(pcidev, 0x40, 0) != 0) {
  2685. printk("%s: can't set PCI retry timeout.\n",
  2686. card->name);
  2687. deinit_card(card);
  2688. return -1;
  2689. }
  2690. }
  2691. IPRINTK("%s: Checking PCI TRDY.\n", card->name);
  2692. if (pci_read_config_byte(pcidev, 0x41, &pci_byte) != 0) {
  2693. printk("%s: can't read PCI TRDY timeout.\n", card->name);
  2694. deinit_card(card);
  2695. return -1;
  2696. }
  2697. if (pci_byte != 0) {
  2698. IPRINTK("%s: PCI TRDY timeout: %d, set to 0.\n",
  2699. card->name, pci_byte);
  2700. if (pci_write_config_byte(pcidev, 0x41, 0) != 0) {
  2701. printk("%s: can't set PCI TRDY timeout.\n", card->name);
  2702. deinit_card(card);
  2703. return -1;
  2704. }
  2705. }
  2706. /* Reset Timer register */
  2707. if (readl(SAR_REG_STAT) & SAR_STAT_TMROF) {
  2708. printk("%s: resetting timer overflow.\n", card->name);
  2709. writel(SAR_STAT_TMROF, SAR_REG_STAT);
  2710. }
  2711. IPRINTK("%s: Request IRQ ... ", card->name);
  2712. if (request_irq(pcidev->irq, idt77252_interrupt, IRQF_SHARED,
  2713. card->name, card) != 0) {
  2714. printk("%s: can't allocate IRQ.\n", card->name);
  2715. deinit_card(card);
  2716. return -1;
  2717. }
  2718. IPRINTK("got %d.\n", pcidev->irq);
  2719. /*****************************************************************/
  2720. /* C H E C K A N D I N I T S R A M */
  2721. /*****************************************************************/
  2722. IPRINTK("%s: Initializing SRAM\n", card->name);
  2723. /* preset size of connecton table, so that init_sram() knows about it */
  2724. conf = SAR_CFG_TX_FIFO_SIZE_9 | /* Use maximum fifo size */
  2725. SAR_CFG_RXSTQ_SIZE_8k | /* Receive Status Queue is 8k */
  2726. SAR_CFG_IDLE_CLP | /* Set CLP on idle cells */
  2727. #ifndef ATM_IDT77252_SEND_IDLE
  2728. SAR_CFG_NO_IDLE | /* Do not send idle cells */
  2729. #endif
  2730. 0;
  2731. if (card->sramsize == (512 * 1024))
  2732. conf |= SAR_CFG_CNTBL_1k;
  2733. else
  2734. conf |= SAR_CFG_CNTBL_512;
  2735. switch (vpibits) {
  2736. case 0:
  2737. conf |= SAR_CFG_VPVCS_0;
  2738. break;
  2739. default:
  2740. case 1:
  2741. conf |= SAR_CFG_VPVCS_1;
  2742. break;
  2743. case 2:
  2744. conf |= SAR_CFG_VPVCS_2;
  2745. break;
  2746. case 8:
  2747. conf |= SAR_CFG_VPVCS_8;
  2748. break;
  2749. }
  2750. writel(readl(SAR_REG_CFG) | conf, SAR_REG_CFG);
  2751. init_sram(card);
  2752. /********************************************************************/
  2753. /* A L L O C R A M A N D S E T V A R I O U S T H I N G S */
  2754. /********************************************************************/
  2755. /* Initialize TSQ */
  2756. if (0 != init_tsq(card)) {
  2757. deinit_card(card);
  2758. return -1;
  2759. }
  2760. /* Initialize RSQ */
  2761. if (0 != init_rsq(card)) {
  2762. deinit_card(card);
  2763. return -1;
  2764. }
  2765. card->vpibits = vpibits;
  2766. if (card->sramsize == (512 * 1024)) {
  2767. card->vcibits = 10 - card->vpibits;
  2768. } else {
  2769. card->vcibits = 9 - card->vpibits;
  2770. }
  2771. card->vcimask = 0;
  2772. for (k = 0, i = 1; k < card->vcibits; k++) {
  2773. card->vcimask |= i;
  2774. i <<= 1;
  2775. }
  2776. IPRINTK("%s: Setting VPI/VCI mask to zero.\n", card->name);
  2777. writel(0, SAR_REG_VPM);
  2778. /* Little Endian Order */
  2779. writel(0, SAR_REG_GP);
  2780. /* Initialize RAW Cell Handle Register */
  2781. card->raw_cell_hnd = dma_alloc_coherent(&card->pcidev->dev,
  2782. 2 * sizeof(u32),
  2783. &card->raw_cell_paddr,
  2784. GFP_KERNEL);
  2785. if (!card->raw_cell_hnd) {
  2786. printk("%s: memory allocation failure.\n", card->name);
  2787. deinit_card(card);
  2788. return -1;
  2789. }
  2790. writel(card->raw_cell_paddr, SAR_REG_RAWHND);
  2791. IPRINTK("%s: raw cell handle is at 0x%p.\n", card->name,
  2792. card->raw_cell_hnd);
  2793. size = sizeof(struct vc_map *) * card->tct_size;
  2794. IPRINTK("%s: allocate %d byte for VC map.\n", card->name, size);
  2795. card->vcs = vzalloc(size);
  2796. if (!card->vcs) {
  2797. printk("%s: memory allocation failure.\n", card->name);
  2798. deinit_card(card);
  2799. return -1;
  2800. }
  2801. size = sizeof(struct vc_map *) * card->scd_size;
  2802. IPRINTK("%s: allocate %d byte for SCD to VC mapping.\n",
  2803. card->name, size);
  2804. card->scd2vc = vzalloc(size);
  2805. if (!card->scd2vc) {
  2806. printk("%s: memory allocation failure.\n", card->name);
  2807. deinit_card(card);
  2808. return -1;
  2809. }
  2810. size = sizeof(struct tst_info) * (card->tst_size - 2);
  2811. IPRINTK("%s: allocate %d byte for TST to VC mapping.\n",
  2812. card->name, size);
  2813. card->soft_tst = vmalloc(size);
  2814. if (!card->soft_tst) {
  2815. printk("%s: memory allocation failure.\n", card->name);
  2816. deinit_card(card);
  2817. return -1;
  2818. }
  2819. for (i = 0; i < card->tst_size - 2; i++) {
  2820. card->soft_tst[i].tste = TSTE_OPC_VAR;
  2821. card->soft_tst[i].vc = NULL;
  2822. }
  2823. if (dev->phy == NULL) {
  2824. printk("%s: No LT device defined.\n", card->name);
  2825. deinit_card(card);
  2826. return -1;
  2827. }
  2828. if (dev->phy->ioctl == NULL) {
  2829. printk("%s: LT had no IOCTL function defined.\n", card->name);
  2830. deinit_card(card);
  2831. return -1;
  2832. }
  2833. #ifdef CONFIG_ATM_IDT77252_USE_SUNI
  2834. /*
  2835. * this is a jhs hack to get around special functionality in the
  2836. * phy driver for the atecom hardware; the functionality doesn't
  2837. * exist in the linux atm suni driver
  2838. *
  2839. * it isn't the right way to do things, but as the guy from NIST
  2840. * said, talking about their measurement of the fine structure
  2841. * constant, "it's good enough for government work."
  2842. */
  2843. linkrate = 149760000;
  2844. #endif
  2845. card->link_pcr = (linkrate / 8 / 53);
  2846. printk("%s: Linkrate on ATM line : %u bit/s, %u cell/s.\n",
  2847. card->name, linkrate, card->link_pcr);
  2848. #ifdef ATM_IDT77252_SEND_IDLE
  2849. card->utopia_pcr = card->link_pcr;
  2850. #else
  2851. card->utopia_pcr = (160000000 / 8 / 54);
  2852. #endif
  2853. rsvdcr = 0;
  2854. if (card->utopia_pcr > card->link_pcr)
  2855. rsvdcr = card->utopia_pcr - card->link_pcr;
  2856. tmpl = (unsigned long) rsvdcr * ((unsigned long) card->tst_size - 2);
  2857. modl = tmpl % (unsigned long)card->utopia_pcr;
  2858. tst_entries = (int) (tmpl / (unsigned long)card->utopia_pcr);
  2859. if (modl)
  2860. tst_entries++;
  2861. card->tst_free -= tst_entries;
  2862. fill_tst(card, NULL, tst_entries, TSTE_OPC_NULL);
  2863. #ifdef HAVE_EEPROM
  2864. idt77252_eeprom_init(card);
  2865. printk("%s: EEPROM: %02x:", card->name,
  2866. idt77252_eeprom_read_status(card));
  2867. for (i = 0; i < 0x80; i++) {
  2868. printk(" %02x",
  2869. idt77252_eeprom_read_byte(card, i)
  2870. );
  2871. }
  2872. printk("\n");
  2873. #endif /* HAVE_EEPROM */
  2874. /*
  2875. * XXX: <hack>
  2876. */
  2877. sprintf(tname, "eth%d", card->index);
  2878. tmp = dev_get_by_name(&init_net, tname); /* jhs: was "tmp = dev_get(tname);" */
  2879. if (tmp) {
  2880. memcpy(card->atmdev->esi, tmp->dev_addr, 6);
  2881. dev_put(tmp);
  2882. printk("%s: ESI %pM\n", card->name, card->atmdev->esi);
  2883. }
  2884. /*
  2885. * XXX: </hack>
  2886. */
  2887. /* Set Maximum Deficit Count for now. */
  2888. writel(0xffff, SAR_REG_MDFCT);
  2889. set_bit(IDT77252_BIT_INIT, &card->flags);
  2890. XPRINTK("%s: IDT77252 ABR SAR initialization complete.\n", card->name);
  2891. return 0;
  2892. }
  2893. /*****************************************************************************/
  2894. /* */
  2895. /* Probing of IDT77252 ABR SAR */
  2896. /* */
  2897. /*****************************************************************************/
  2898. static int idt77252_preset(struct idt77252_dev *card)
  2899. {
  2900. u16 pci_command;
  2901. /*****************************************************************/
  2902. /* P C I C O N F I G U R A T I O N */
  2903. /*****************************************************************/
  2904. XPRINTK("%s: Enable PCI master and memory access for SAR.\n",
  2905. card->name);
  2906. if (pci_read_config_word(card->pcidev, PCI_COMMAND, &pci_command)) {
  2907. printk("%s: can't read PCI_COMMAND.\n", card->name);
  2908. deinit_card(card);
  2909. return -1;
  2910. }
  2911. if (!(pci_command & PCI_COMMAND_IO)) {
  2912. printk("%s: PCI_COMMAND: %04x (???)\n",
  2913. card->name, pci_command);
  2914. deinit_card(card);
  2915. return (-1);
  2916. }
  2917. pci_command |= (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
  2918. if (pci_write_config_word(card->pcidev, PCI_COMMAND, pci_command)) {
  2919. printk("%s: can't write PCI_COMMAND.\n", card->name);
  2920. deinit_card(card);
  2921. return -1;
  2922. }
  2923. /*****************************************************************/
  2924. /* G E N E R I C R E S E T */
  2925. /*****************************************************************/
  2926. /* Software reset */
  2927. writel(SAR_CFG_SWRST, SAR_REG_CFG);
  2928. mdelay(1);
  2929. writel(0, SAR_REG_CFG);
  2930. IPRINTK("%s: Software resetted.\n", card->name);
  2931. return 0;
  2932. }
  2933. static unsigned long probe_sram(struct idt77252_dev *card)
  2934. {
  2935. u32 data, addr;
  2936. writel(0, SAR_REG_DR0);
  2937. writel(SAR_CMD_WRITE_SRAM | (0 << 2), SAR_REG_CMD);
  2938. for (addr = 0x4000; addr < 0x80000; addr += 0x4000) {
  2939. writel(ATM_POISON, SAR_REG_DR0);
  2940. writel(SAR_CMD_WRITE_SRAM | (addr << 2), SAR_REG_CMD);
  2941. writel(SAR_CMD_READ_SRAM | (0 << 2), SAR_REG_CMD);
  2942. data = readl(SAR_REG_DR0);
  2943. if (data != 0)
  2944. break;
  2945. }
  2946. return addr * sizeof(u32);
  2947. }
  2948. static int idt77252_init_one(struct pci_dev *pcidev,
  2949. const struct pci_device_id *id)
  2950. {
  2951. static struct idt77252_dev **last = &idt77252_chain;
  2952. static int index = 0;
  2953. unsigned long membase, srambase;
  2954. struct idt77252_dev *card;
  2955. struct atm_dev *dev;
  2956. int i, err;
  2957. if ((err = pci_enable_device(pcidev))) {
  2958. printk("idt77252: can't enable PCI device at %s\n", pci_name(pcidev));
  2959. return err;
  2960. }
  2961. if ((err = dma_set_mask_and_coherent(&pcidev->dev, DMA_BIT_MASK(32)))) {
  2962. printk("idt77252: can't enable DMA for PCI device at %s\n", pci_name(pcidev));
  2963. goto err_out_disable_pdev;
  2964. }
  2965. card = kzalloc(sizeof(struct idt77252_dev), GFP_KERNEL);
  2966. if (!card) {
  2967. printk("idt77252-%d: can't allocate private data\n", index);
  2968. err = -ENOMEM;
  2969. goto err_out_disable_pdev;
  2970. }
  2971. card->revision = pcidev->revision;
  2972. card->index = index;
  2973. card->pcidev = pcidev;
  2974. sprintf(card->name, "idt77252-%d", card->index);
  2975. INIT_WORK(&card->tqueue, idt77252_softint);
  2976. membase = pci_resource_start(pcidev, 1);
  2977. srambase = pci_resource_start(pcidev, 2);
  2978. mutex_init(&card->mutex);
  2979. spin_lock_init(&card->cmd_lock);
  2980. spin_lock_init(&card->tst_lock);
  2981. timer_setup(&card->tst_timer, tst_timer, 0);
  2982. /* Do the I/O remapping... */
  2983. card->membase = ioremap(membase, 1024);
  2984. if (!card->membase) {
  2985. printk("%s: can't ioremap() membase\n", card->name);
  2986. err = -EIO;
  2987. goto err_out_free_card;
  2988. }
  2989. if (idt77252_preset(card)) {
  2990. printk("%s: preset failed\n", card->name);
  2991. err = -EIO;
  2992. goto err_out_iounmap;
  2993. }
  2994. dev = atm_dev_register("idt77252", &pcidev->dev, &idt77252_ops, -1,
  2995. NULL);
  2996. if (!dev) {
  2997. printk("%s: can't register atm device\n", card->name);
  2998. err = -EIO;
  2999. goto err_out_iounmap;
  3000. }
  3001. dev->dev_data = card;
  3002. card->atmdev = dev;
  3003. #ifdef CONFIG_ATM_IDT77252_USE_SUNI
  3004. suni_init(dev);
  3005. if (!dev->phy) {
  3006. printk("%s: can't init SUNI\n", card->name);
  3007. err = -EIO;
  3008. goto err_out_deinit_card;
  3009. }
  3010. #endif /* CONFIG_ATM_IDT77252_USE_SUNI */
  3011. card->sramsize = probe_sram(card);
  3012. for (i = 0; i < 4; i++) {
  3013. card->fbq[i] = ioremap(srambase | 0x200000 | (i << 18), 4);
  3014. if (!card->fbq[i]) {
  3015. printk("%s: can't ioremap() FBQ%d\n", card->name, i);
  3016. err = -EIO;
  3017. goto err_out_deinit_card;
  3018. }
  3019. }
  3020. printk("%s: ABR SAR (Rev %c): MEM %08lx SRAM %08lx [%u KB]\n",
  3021. card->name, ((card->revision > 1) && (card->revision < 25)) ?
  3022. 'A' + card->revision - 1 : '?', membase, srambase,
  3023. card->sramsize / 1024);
  3024. if (init_card(dev)) {
  3025. printk("%s: init_card failed\n", card->name);
  3026. err = -EIO;
  3027. goto err_out_deinit_card;
  3028. }
  3029. dev->ci_range.vpi_bits = card->vpibits;
  3030. dev->ci_range.vci_bits = card->vcibits;
  3031. dev->link_rate = card->link_pcr;
  3032. if (dev->phy->start)
  3033. dev->phy->start(dev);
  3034. if (idt77252_dev_open(card)) {
  3035. printk("%s: dev_open failed\n", card->name);
  3036. err = -EIO;
  3037. goto err_out_stop;
  3038. }
  3039. *last = card;
  3040. last = &card->next;
  3041. index++;
  3042. return 0;
  3043. err_out_stop:
  3044. if (dev->phy->stop)
  3045. dev->phy->stop(dev);
  3046. err_out_deinit_card:
  3047. deinit_card(card);
  3048. err_out_iounmap:
  3049. iounmap(card->membase);
  3050. err_out_free_card:
  3051. kfree(card);
  3052. err_out_disable_pdev:
  3053. pci_disable_device(pcidev);
  3054. return err;
  3055. }
  3056. static const struct pci_device_id idt77252_pci_tbl[] =
  3057. {
  3058. { PCI_VDEVICE(IDT, PCI_DEVICE_ID_IDT_IDT77252), 0 },
  3059. { 0, }
  3060. };
  3061. MODULE_DEVICE_TABLE(pci, idt77252_pci_tbl);
  3062. static struct pci_driver idt77252_driver = {
  3063. .name = "idt77252",
  3064. .id_table = idt77252_pci_tbl,
  3065. .probe = idt77252_init_one,
  3066. };
  3067. static int __init idt77252_init(void)
  3068. {
  3069. struct sk_buff *skb;
  3070. printk("%s: at %p\n", __func__, idt77252_init);
  3071. if (sizeof(skb->cb) < sizeof(struct atm_skb_data) +
  3072. sizeof(struct idt77252_skb_prv)) {
  3073. printk(KERN_ERR "%s: skb->cb is too small (%lu < %lu)\n",
  3074. __func__, (unsigned long) sizeof(skb->cb),
  3075. (unsigned long) sizeof(struct atm_skb_data) +
  3076. sizeof(struct idt77252_skb_prv));
  3077. return -EIO;
  3078. }
  3079. return pci_register_driver(&idt77252_driver);
  3080. }
  3081. static void __exit idt77252_exit(void)
  3082. {
  3083. struct idt77252_dev *card;
  3084. struct atm_dev *dev;
  3085. pci_unregister_driver(&idt77252_driver);
  3086. while (idt77252_chain) {
  3087. card = idt77252_chain;
  3088. dev = card->atmdev;
  3089. idt77252_chain = card->next;
  3090. if (dev->phy->stop)
  3091. dev->phy->stop(dev);
  3092. deinit_card(card);
  3093. pci_disable_device(card->pcidev);
  3094. kfree(card);
  3095. }
  3096. DIPRINTK("idt77252: finished cleanup-module().\n");
  3097. }
  3098. module_init(idt77252_init);
  3099. module_exit(idt77252_exit);
  3100. MODULE_LICENSE("GPL");
  3101. module_param(vpibits, uint, 0);
  3102. MODULE_PARM_DESC(vpibits, "number of VPI bits supported (0, 1, or 2)");
  3103. #ifdef CONFIG_ATM_IDT77252_DEBUG
  3104. module_param(debug, ulong, 0644);
  3105. MODULE_PARM_DESC(debug, "debug bitmap, see drivers/atm/idt77252.h");
  3106. #endif
  3107. MODULE_AUTHOR("Eddie C. Dost <ecd@atecom.com>");
  3108. MODULE_DESCRIPTION("IDT77252 ABR SAR Driver");