horizon.c 81 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. Madge Horizon ATM Adapter driver.
  4. Copyright (C) 1995-1999 Madge Networks Ltd.
  5. */
  6. /*
  7. IMPORTANT NOTE: Madge Networks no longer makes the adapters
  8. supported by this driver and makes no commitment to maintain it.
  9. */
  10. #include <linux/module.h>
  11. #include <linux/kernel.h>
  12. #include <linux/sched/signal.h>
  13. #include <linux/mm.h>
  14. #include <linux/pci.h>
  15. #include <linux/errno.h>
  16. #include <linux/atm.h>
  17. #include <linux/atmdev.h>
  18. #include <linux/sonet.h>
  19. #include <linux/skbuff.h>
  20. #include <linux/time.h>
  21. #include <linux/delay.h>
  22. #include <linux/uio.h>
  23. #include <linux/init.h>
  24. #include <linux/interrupt.h>
  25. #include <linux/ioport.h>
  26. #include <linux/wait.h>
  27. #include <linux/slab.h>
  28. #include <asm/io.h>
  29. #include <linux/atomic.h>
  30. #include <linux/uaccess.h>
  31. #include <asm/string.h>
  32. #include <asm/byteorder.h>
  33. #include "horizon.h"
  34. #define maintainer_string "Giuliano Procida at Madge Networks <gprocida@madge.com>"
  35. #define description_string "Madge ATM Horizon [Ultra] driver"
  36. #define version_string "1.2.1"
  37. static inline void __init show_version (void) {
  38. printk ("%s version %s\n", description_string, version_string);
  39. }
  40. /*
  41. CREDITS
  42. Driver and documentation by:
  43. Chris Aston Madge Networks
  44. Giuliano Procida Madge Networks
  45. Simon Benham Madge Networks
  46. Simon Johnson Madge Networks
  47. Various Others Madge Networks
  48. Some inspiration taken from other drivers by:
  49. Alexandru Cucos UTBv
  50. Kari Mettinen University of Helsinki
  51. Werner Almesberger EPFL LRC
  52. Theory of Operation
  53. I Hardware, detection, initialisation and shutdown.
  54. 1. Supported Hardware
  55. This driver should handle all variants of the PCI Madge ATM adapters
  56. with the Horizon chipset. These are all PCI cards supporting PIO, BM
  57. DMA and a form of MMIO (registers only, not internal RAM).
  58. The driver is only known to work with SONET and UTP Horizon Ultra
  59. cards at 155Mb/s. However, code is in place to deal with both the
  60. original Horizon and 25Mb/s operation.
  61. There are two revisions of the Horizon ASIC: the original and the
  62. Ultra. Details of hardware bugs are in section III.
  63. The ASIC version can be distinguished by chip markings but is NOT
  64. indicated by the PCI revision (all adapters seem to have PCI rev 1).
  65. I believe that:
  66. Horizon => Collage 25 PCI Adapter (UTP and STP)
  67. Horizon Ultra => Collage 155 PCI Client (UTP or SONET)
  68. Ambassador x => Collage 155 PCI Server (completely different)
  69. Horizon (25Mb/s) is fitted with UTP and STP connectors. It seems to
  70. have a Madge B154 plus glue logic serializer. I have also found a
  71. really ancient version of this with slightly different glue. It
  72. comes with the revision 0 (140-025-01) ASIC.
  73. Horizon Ultra (155Mb/s) is fitted with either a Pulse Medialink
  74. output (UTP) or an HP HFBR 5205 output (SONET). It has either
  75. Madge's SAMBA framer or a SUNI-lite device (early versions). It
  76. comes with the revision 1 (140-027-01) ASIC.
  77. 2. Detection
  78. All Horizon-based cards present with the same PCI Vendor and Device
  79. IDs. The standard Linux 2.2 PCI API is used to locate any cards and
  80. to enable bus-mastering (with appropriate latency).
  81. ATM_LAYER_STATUS in the control register distinguishes between the
  82. two possible physical layers (25 and 155). It is not clear whether
  83. the 155 cards can also operate at 25Mbps. We rely on the fact that a
  84. card operates at 155 if and only if it has the newer Horizon Ultra
  85. ASIC.
  86. For 155 cards the two possible framers are probed for and then set
  87. up for loop-timing.
  88. 3. Initialisation
  89. The card is reset and then put into a known state. The physical
  90. layer is configured for normal operation at the appropriate speed;
  91. in the case of the 155 cards, the framer is initialised with
  92. line-based timing; the internal RAM is zeroed and the allocation of
  93. buffers for RX and TX is made; the Burnt In Address is read and
  94. copied to the ATM ESI; various policy settings for RX (VPI bits,
  95. unknown VCs, oam cells) are made. Ideally all policy items should be
  96. configurable at module load (if not actually on-demand), however,
  97. only the vpi vs vci bit allocation can be specified at insmod.
  98. 4. Shutdown
  99. This is in response to module_cleaup. No VCs are in use and the card
  100. should be idle; it is reset.
  101. II Driver software (as it should be)
  102. 0. Traffic Parameters
  103. The traffic classes (not an enumeration) are currently: ATM_NONE (no
  104. traffic), ATM_UBR, ATM_CBR, ATM_VBR and ATM_ABR, ATM_ANYCLASS
  105. (compatible with everything). Together with (perhaps only some of)
  106. the following items they make up the traffic specification.
  107. struct atm_trafprm {
  108. unsigned char traffic_class; traffic class (ATM_UBR, ...)
  109. int max_pcr; maximum PCR in cells per second
  110. int pcr; desired PCR in cells per second
  111. int min_pcr; minimum PCR in cells per second
  112. int max_cdv; maximum CDV in microseconds
  113. int max_sdu; maximum SDU in bytes
  114. };
  115. Note that these denote bandwidth available not bandwidth used; the
  116. possibilities according to ATMF are:
  117. Real Time (cdv and max CDT given)
  118. CBR(pcr) pcr bandwidth always available
  119. rtVBR(pcr,scr,mbs) scr bandwidth always available, up to pcr at mbs too
  120. Non Real Time
  121. nrtVBR(pcr,scr,mbs) scr bandwidth always available, up to pcr at mbs too
  122. UBR()
  123. ABR(mcr,pcr) mcr bandwidth always available, up to pcr (depending) too
  124. mbs is max burst size (bucket)
  125. pcr and scr have associated cdvt values
  126. mcr is like scr but has no cdtv
  127. cdtv may differ at each hop
  128. Some of the above items are qos items (as opposed to traffic
  129. parameters). We have nothing to do with qos. All except ABR can have
  130. their traffic parameters converted to GCRA parameters. The GCRA may
  131. be implemented as a (real-number) leaky bucket. The GCRA can be used
  132. in complicated ways by switches and in simpler ways by end-stations.
  133. It can be used both to filter incoming cells and shape out-going
  134. cells.
  135. ATM Linux actually supports:
  136. ATM_NONE() (no traffic in this direction)
  137. ATM_UBR(max_frame_size)
  138. ATM_CBR(max/min_pcr, max_cdv, max_frame_size)
  139. 0 or ATM_MAX_PCR are used to indicate maximum available PCR
  140. A traffic specification consists of the AAL type and separate
  141. traffic specifications for either direction. In ATM Linux it is:
  142. struct atm_qos {
  143. struct atm_trafprm txtp;
  144. struct atm_trafprm rxtp;
  145. unsigned char aal;
  146. };
  147. AAL types are:
  148. ATM_NO_AAL AAL not specified
  149. ATM_AAL0 "raw" ATM cells
  150. ATM_AAL1 AAL1 (CBR)
  151. ATM_AAL2 AAL2 (VBR)
  152. ATM_AAL34 AAL3/4 (data)
  153. ATM_AAL5 AAL5 (data)
  154. ATM_SAAL signaling AAL
  155. The Horizon has support for AAL frame types: 0, 3/4 and 5. However,
  156. it does not implement AAL 3/4 SAR and it has a different notion of
  157. "raw cell" to ATM Linux's (48 bytes vs. 52 bytes) so neither are
  158. supported by this driver.
  159. The Horizon has limited support for ABR (including UBR), VBR and
  160. CBR. Each TX channel has a bucket (containing up to 31 cell units)
  161. and two timers (PCR and SCR) associated with it that can be used to
  162. govern cell emissions and host notification (in the case of ABR this
  163. is presumably so that RM cells may be emitted at appropriate times).
  164. The timers may either be disabled or may be set to any of 240 values
  165. (determined by the clock crystal, a fixed (?) per-device divider, a
  166. configurable divider and a configurable timer preload value).
  167. At the moment only UBR and CBR are supported by the driver. VBR will
  168. be supported as soon as ATM for Linux supports it. ABR support is
  169. very unlikely as RM cell handling is completely up to the driver.
  170. 1. TX (TX channel setup and TX transfer)
  171. The TX half of the driver owns the TX Horizon registers. The TX
  172. component in the IRQ handler is the BM completion handler. This can
  173. only be entered when tx_busy is true (enforced by hardware). The
  174. other TX component can only be entered when tx_busy is false
  175. (enforced by driver). So TX is single-threaded.
  176. Apart from a minor optimisation to not re-select the last channel,
  177. the TX send component works as follows:
  178. Atomic test and set tx_busy until we succeed; we should implement
  179. some sort of timeout so that tx_busy will never be stuck at true.
  180. If no TX channel is set up for this VC we wait for an idle one (if
  181. necessary) and set it up.
  182. At this point we have a TX channel ready for use. We wait for enough
  183. buffers to become available then start a TX transmit (set the TX
  184. descriptor, schedule transfer, exit).
  185. The IRQ component handles TX completion (stats, free buffer, tx_busy
  186. unset, exit). We also re-schedule further transfers for the same
  187. frame if needed.
  188. TX setup in more detail:
  189. TX open is a nop, the relevant information is held in the hrz_vcc
  190. (vcc->dev_data) structure and is "cached" on the card.
  191. TX close gets the TX lock and clears the channel from the "cache".
  192. 2. RX (Data Available and RX transfer)
  193. The RX half of the driver owns the RX registers. There are two RX
  194. components in the IRQ handler: the data available handler deals with
  195. fresh data that has arrived on the card, the BM completion handler
  196. is very similar to the TX completion handler. The data available
  197. handler grabs the rx_lock and it is only released once the data has
  198. been discarded or completely transferred to the host. The BM
  199. completion handler only runs when the lock is held; the data
  200. available handler is locked out over the same period.
  201. Data available on the card triggers an interrupt. If the data is not
  202. suitable for our existing RX channels or we cannot allocate a buffer
  203. it is flushed. Otherwise an RX receive is scheduled. Multiple RX
  204. transfers may be scheduled for the same frame.
  205. RX setup in more detail:
  206. RX open...
  207. RX close...
  208. III Hardware Bugs
  209. 0. Byte vs Word addressing of adapter RAM.
  210. A design feature; see the .h file (especially the memory map).
  211. 1. Bus Master Data Transfers (original Horizon only, fixed in Ultra)
  212. The host must not start a transmit direction transfer at a
  213. non-four-byte boundary in host memory. Instead the host should
  214. perform a byte, or a two byte, or one byte followed by two byte
  215. transfer in order to start the rest of the transfer on a four byte
  216. boundary. RX is OK.
  217. Simultaneous transmit and receive direction bus master transfers are
  218. not allowed.
  219. The simplest solution to these two is to always do PIO (never DMA)
  220. in the TX direction on the original Horizon. More complicated
  221. solutions are likely to hurt my brain.
  222. 2. Loss of buffer on close VC
  223. When a VC is being closed, the buffer associated with it is not
  224. returned to the pool. The host must store the reference to this
  225. buffer and when opening a new VC then give it to that new VC.
  226. The host intervention currently consists of stacking such a buffer
  227. pointer at VC close and checking the stack at VC open.
  228. 3. Failure to close a VC
  229. If a VC is currently receiving a frame then closing the VC may fail
  230. and the frame continues to be received.
  231. The solution is to make sure any received frames are flushed when
  232. ready. This is currently done just before the solution to 2.
  233. 4. PCI bus (original Horizon only, fixed in Ultra)
  234. Reading from the data port prior to initialisation will hang the PCI
  235. bus. Just don't do that then! We don't.
  236. IV To Do List
  237. . Timer code may be broken.
  238. . Allow users to specify buffer allocation split for TX and RX.
  239. . Deal once and for all with buggy VC close.
  240. . Handle interrupted and/or non-blocking operations.
  241. . Change some macros to functions and move from .h to .c.
  242. . Try to limit the number of TX frames each VC may have queued, in
  243. order to reduce the chances of TX buffer exhaustion.
  244. . Implement VBR (bucket and timers not understood) and ABR (need to
  245. do RM cells manually); also no Linux support for either.
  246. . Implement QoS changes on open VCs (involves extracting parts of VC open
  247. and close into separate functions and using them to make changes).
  248. */
  249. /********** globals **********/
  250. static void do_housekeeping (struct timer_list *t);
  251. static unsigned short debug = 0;
  252. static unsigned short vpi_bits = 0;
  253. static int max_tx_size = 9000;
  254. static int max_rx_size = 9000;
  255. static unsigned char pci_lat = 0;
  256. /********** access functions **********/
  257. /* Read / Write Horizon registers */
  258. static inline void wr_regl (const hrz_dev * dev, unsigned char reg, u32 data) {
  259. outl (cpu_to_le32 (data), dev->iobase + reg);
  260. }
  261. static inline u32 rd_regl (const hrz_dev * dev, unsigned char reg) {
  262. return le32_to_cpu (inl (dev->iobase + reg));
  263. }
  264. static inline void wr_regw (const hrz_dev * dev, unsigned char reg, u16 data) {
  265. outw (cpu_to_le16 (data), dev->iobase + reg);
  266. }
  267. static inline u16 rd_regw (const hrz_dev * dev, unsigned char reg) {
  268. return le16_to_cpu (inw (dev->iobase + reg));
  269. }
  270. static inline void wrs_regb (const hrz_dev * dev, unsigned char reg, void * addr, u32 len) {
  271. outsb (dev->iobase + reg, addr, len);
  272. }
  273. static inline void rds_regb (const hrz_dev * dev, unsigned char reg, void * addr, u32 len) {
  274. insb (dev->iobase + reg, addr, len);
  275. }
  276. /* Read / Write to a given address in Horizon buffer memory.
  277. Interrupts must be disabled between the address register and data
  278. port accesses as these must form an atomic operation. */
  279. static inline void wr_mem (const hrz_dev * dev, HDW * addr, u32 data) {
  280. // wr_regl (dev, MEM_WR_ADDR_REG_OFF, (u32) addr);
  281. wr_regl (dev, MEM_WR_ADDR_REG_OFF, (addr - (HDW *) 0) * sizeof(HDW));
  282. wr_regl (dev, MEMORY_PORT_OFF, data);
  283. }
  284. static inline u32 rd_mem (const hrz_dev * dev, HDW * addr) {
  285. // wr_regl (dev, MEM_RD_ADDR_REG_OFF, (u32) addr);
  286. wr_regl (dev, MEM_RD_ADDR_REG_OFF, (addr - (HDW *) 0) * sizeof(HDW));
  287. return rd_regl (dev, MEMORY_PORT_OFF);
  288. }
  289. static inline void wr_framer (const hrz_dev * dev, u32 addr, u32 data) {
  290. wr_regl (dev, MEM_WR_ADDR_REG_OFF, (u32) addr | 0x80000000);
  291. wr_regl (dev, MEMORY_PORT_OFF, data);
  292. }
  293. static inline u32 rd_framer (const hrz_dev * dev, u32 addr) {
  294. wr_regl (dev, MEM_RD_ADDR_REG_OFF, (u32) addr | 0x80000000);
  295. return rd_regl (dev, MEMORY_PORT_OFF);
  296. }
  297. /********** specialised access functions **********/
  298. /* RX */
  299. static inline void FLUSH_RX_CHANNEL (hrz_dev * dev, u16 channel) {
  300. wr_regw (dev, RX_CHANNEL_PORT_OFF, FLUSH_CHANNEL | channel);
  301. return;
  302. }
  303. static void WAIT_FLUSH_RX_COMPLETE (hrz_dev * dev) {
  304. while (rd_regw (dev, RX_CHANNEL_PORT_OFF) & FLUSH_CHANNEL)
  305. ;
  306. return;
  307. }
  308. static inline void SELECT_RX_CHANNEL (hrz_dev * dev, u16 channel) {
  309. wr_regw (dev, RX_CHANNEL_PORT_OFF, channel);
  310. return;
  311. }
  312. static void WAIT_UPDATE_COMPLETE (hrz_dev * dev) {
  313. while (rd_regw (dev, RX_CHANNEL_PORT_OFF) & RX_CHANNEL_UPDATE_IN_PROGRESS)
  314. ;
  315. return;
  316. }
  317. /* TX */
  318. static inline void SELECT_TX_CHANNEL (hrz_dev * dev, u16 tx_channel) {
  319. wr_regl (dev, TX_CHANNEL_PORT_OFF, tx_channel);
  320. return;
  321. }
  322. /* Update or query one configuration parameter of a particular channel. */
  323. static inline void update_tx_channel_config (hrz_dev * dev, short chan, u8 mode, u16 value) {
  324. wr_regw (dev, TX_CHANNEL_CONFIG_COMMAND_OFF,
  325. chan * TX_CHANNEL_CONFIG_MULT | mode);
  326. wr_regw (dev, TX_CHANNEL_CONFIG_DATA_OFF, value);
  327. return;
  328. }
  329. /********** dump functions **********/
  330. static inline void dump_skb (char * prefix, unsigned int vc, struct sk_buff * skb) {
  331. #ifdef DEBUG_HORIZON
  332. unsigned int i;
  333. unsigned char * data = skb->data;
  334. PRINTDB (DBG_DATA, "%s(%u) ", prefix, vc);
  335. for (i=0; i<skb->len && i < 256;i++)
  336. PRINTDM (DBG_DATA, "%02x ", data[i]);
  337. PRINTDE (DBG_DATA,"");
  338. #else
  339. (void) prefix;
  340. (void) vc;
  341. (void) skb;
  342. #endif
  343. return;
  344. }
  345. static inline void dump_regs (hrz_dev * dev) {
  346. #ifdef DEBUG_HORIZON
  347. PRINTD (DBG_REGS, "CONTROL 0: %#x", rd_regl (dev, CONTROL_0_REG));
  348. PRINTD (DBG_REGS, "RX CONFIG: %#x", rd_regw (dev, RX_CONFIG_OFF));
  349. PRINTD (DBG_REGS, "TX CONFIG: %#x", rd_regw (dev, TX_CONFIG_OFF));
  350. PRINTD (DBG_REGS, "TX STATUS: %#x", rd_regw (dev, TX_STATUS_OFF));
  351. PRINTD (DBG_REGS, "IRQ ENBLE: %#x", rd_regl (dev, INT_ENABLE_REG_OFF));
  352. PRINTD (DBG_REGS, "IRQ SORCE: %#x", rd_regl (dev, INT_SOURCE_REG_OFF));
  353. #else
  354. (void) dev;
  355. #endif
  356. return;
  357. }
  358. static inline void dump_framer (hrz_dev * dev) {
  359. #ifdef DEBUG_HORIZON
  360. unsigned int i;
  361. PRINTDB (DBG_REGS, "framer registers:");
  362. for (i = 0; i < 0x10; ++i)
  363. PRINTDM (DBG_REGS, " %02x", rd_framer (dev, i));
  364. PRINTDE (DBG_REGS,"");
  365. #else
  366. (void) dev;
  367. #endif
  368. return;
  369. }
  370. /********** VPI/VCI <-> (RX) channel conversions **********/
  371. /* RX channels are 10 bit integers, these fns are quite paranoid */
  372. static inline int vpivci_to_channel (u16 * channel, const short vpi, const int vci) {
  373. unsigned short vci_bits = 10 - vpi_bits;
  374. if (0 <= vpi && vpi < 1<<vpi_bits && 0 <= vci && vci < 1<<vci_bits) {
  375. *channel = vpi<<vci_bits | vci;
  376. return *channel ? 0 : -EINVAL;
  377. }
  378. return -EINVAL;
  379. }
  380. /********** decode RX queue entries **********/
  381. static inline u16 rx_q_entry_to_length (u32 x) {
  382. return x & RX_Q_ENTRY_LENGTH_MASK;
  383. }
  384. static inline u16 rx_q_entry_to_rx_channel (u32 x) {
  385. return (x>>RX_Q_ENTRY_CHANNEL_SHIFT) & RX_CHANNEL_MASK;
  386. }
  387. /* Cell Transmit Rate Values
  388. *
  389. * the cell transmit rate (cells per sec) can be set to a variety of
  390. * different values by specifying two parameters: a timer preload from
  391. * 1 to 16 (stored as 0 to 15) and a clock divider (2 to the power of
  392. * an exponent from 0 to 14; the special value 15 disables the timer).
  393. *
  394. * cellrate = baserate / (preload * 2^divider)
  395. *
  396. * The maximum cell rate that can be specified is therefore just the
  397. * base rate. Halving the preload is equivalent to adding 1 to the
  398. * divider and so values 1 to 8 of the preload are redundant except
  399. * in the case of a maximal divider (14).
  400. *
  401. * Given a desired cell rate, an algorithm to determine the preload
  402. * and divider is:
  403. *
  404. * a) x = baserate / cellrate, want p * 2^d = x (as far as possible)
  405. * b) if x > 16 * 2^14 then set p = 16, d = 14 (min rate), done
  406. * if x <= 16 then set p = x, d = 0 (high rates), done
  407. * c) now have 16 < x <= 2^18, or 1 < x/16 <= 2^14 and we want to
  408. * know n such that 2^(n-1) < x/16 <= 2^n, so slide a bit until
  409. * we find the range (n will be between 1 and 14), set d = n
  410. * d) Also have 8 < x/2^n <= 16, so set p nearest x/2^n
  411. *
  412. * The algorithm used below is a minor variant of the above.
  413. *
  414. * The base rate is derived from the oscillator frequency (Hz) using a
  415. * fixed divider:
  416. *
  417. * baserate = freq / 32 in the case of some Unknown Card
  418. * baserate = freq / 8 in the case of the Horizon 25
  419. * baserate = freq / 8 in the case of the Horizon Ultra 155
  420. *
  421. * The Horizon cards have oscillators and base rates as follows:
  422. *
  423. * Card Oscillator Base Rate
  424. * Unknown Card 33 MHz 1.03125 MHz (33 MHz = PCI freq)
  425. * Horizon 25 32 MHz 4 MHz
  426. * Horizon Ultra 155 40 MHz 5 MHz
  427. *
  428. * The following defines give the base rates in Hz. These were
  429. * previously a factor of 100 larger, no doubt someone was using
  430. * cps*100.
  431. */
  432. #define BR_UKN 1031250l
  433. #define BR_HRZ 4000000l
  434. #define BR_ULT 5000000l
  435. // d is an exponent
  436. #define CR_MIND 0
  437. #define CR_MAXD 14
  438. // p ranges from 1 to a power of 2
  439. #define CR_MAXPEXP 4
  440. static int make_rate (const hrz_dev * dev, u32 c, rounding r,
  441. u16 * bits, unsigned int * actual)
  442. {
  443. // note: rounding the rate down means rounding 'p' up
  444. const unsigned long br = test_bit(ultra, &dev->flags) ? BR_ULT : BR_HRZ;
  445. u32 div = CR_MIND;
  446. u32 pre;
  447. // br_exp and br_man are used to avoid overflowing (c*maxp*2^d) in
  448. // the tests below. We could think harder about exact possibilities
  449. // of failure...
  450. unsigned long br_man = br;
  451. unsigned int br_exp = 0;
  452. PRINTD (DBG_QOS|DBG_FLOW, "make_rate b=%lu, c=%u, %s", br, c,
  453. r == round_up ? "up" : r == round_down ? "down" : "nearest");
  454. // avoid div by zero
  455. if (!c) {
  456. PRINTD (DBG_QOS|DBG_ERR, "zero rate is not allowed!");
  457. return -EINVAL;
  458. }
  459. while (br_exp < CR_MAXPEXP + CR_MIND && (br_man % 2 == 0)) {
  460. br_man = br_man >> 1;
  461. ++br_exp;
  462. }
  463. // (br >>br_exp) <<br_exp == br and
  464. // br_exp <= CR_MAXPEXP+CR_MIND
  465. if (br_man <= (c << (CR_MAXPEXP+CR_MIND-br_exp))) {
  466. // Equivalent to: B <= (c << (MAXPEXP+MIND))
  467. // take care of rounding
  468. switch (r) {
  469. case round_down:
  470. pre = DIV_ROUND_UP(br, c<<div);
  471. // but p must be non-zero
  472. if (!pre)
  473. pre = 1;
  474. break;
  475. case round_nearest:
  476. pre = DIV_ROUND_CLOSEST(br, c<<div);
  477. // but p must be non-zero
  478. if (!pre)
  479. pre = 1;
  480. break;
  481. default: /* round_up */
  482. pre = br/(c<<div);
  483. // but p must be non-zero
  484. if (!pre)
  485. return -EINVAL;
  486. }
  487. PRINTD (DBG_QOS, "A: p=%u, d=%u", pre, div);
  488. goto got_it;
  489. }
  490. // at this point we have
  491. // d == MIND and (c << (MAXPEXP+MIND)) < B
  492. while (div < CR_MAXD) {
  493. div++;
  494. if (br_man <= (c << (CR_MAXPEXP+div-br_exp))) {
  495. // Equivalent to: B <= (c << (MAXPEXP+d))
  496. // c << (MAXPEXP+d-1) < B <= c << (MAXPEXP+d)
  497. // 1 << (MAXPEXP-1) < B/2^d/c <= 1 << MAXPEXP
  498. // MAXP/2 < B/c2^d <= MAXP
  499. // take care of rounding
  500. switch (r) {
  501. case round_down:
  502. pre = DIV_ROUND_UP(br, c<<div);
  503. break;
  504. case round_nearest:
  505. pre = DIV_ROUND_CLOSEST(br, c<<div);
  506. break;
  507. default: /* round_up */
  508. pre = br/(c<<div);
  509. }
  510. PRINTD (DBG_QOS, "B: p=%u, d=%u", pre, div);
  511. goto got_it;
  512. }
  513. }
  514. // at this point we have
  515. // d == MAXD and (c << (MAXPEXP+MAXD)) < B
  516. // but we cannot go any higher
  517. // take care of rounding
  518. if (r == round_down)
  519. return -EINVAL;
  520. pre = 1 << CR_MAXPEXP;
  521. PRINTD (DBG_QOS, "C: p=%u, d=%u", pre, div);
  522. got_it:
  523. // paranoia
  524. if (div > CR_MAXD || (!pre) || pre > 1<<CR_MAXPEXP) {
  525. PRINTD (DBG_QOS, "set_cr internal failure: d=%u p=%u",
  526. div, pre);
  527. return -EINVAL;
  528. } else {
  529. if (bits)
  530. *bits = (div<<CLOCK_SELECT_SHIFT) | (pre-1);
  531. if (actual) {
  532. *actual = DIV_ROUND_UP(br, pre<<div);
  533. PRINTD (DBG_QOS, "actual rate: %u", *actual);
  534. }
  535. return 0;
  536. }
  537. }
  538. static int make_rate_with_tolerance (const hrz_dev * dev, u32 c, rounding r, unsigned int tol,
  539. u16 * bit_pattern, unsigned int * actual) {
  540. unsigned int my_actual;
  541. PRINTD (DBG_QOS|DBG_FLOW, "make_rate_with_tolerance c=%u, %s, tol=%u",
  542. c, (r == round_up) ? "up" : (r == round_down) ? "down" : "nearest", tol);
  543. if (!actual)
  544. // actual rate is not returned
  545. actual = &my_actual;
  546. if (make_rate (dev, c, round_nearest, bit_pattern, actual))
  547. // should never happen as round_nearest always succeeds
  548. return -1;
  549. if (c - tol <= *actual && *actual <= c + tol)
  550. // within tolerance
  551. return 0;
  552. else
  553. // intolerant, try rounding instead
  554. return make_rate (dev, c, r, bit_pattern, actual);
  555. }
  556. /********** Listen on a VC **********/
  557. static int hrz_open_rx (hrz_dev * dev, u16 channel) {
  558. // is there any guarantee that we don't get two simulataneous
  559. // identical calls of this function from different processes? yes
  560. // rate_lock
  561. unsigned long flags;
  562. u32 channel_type; // u16?
  563. u16 buf_ptr = RX_CHANNEL_IDLE;
  564. rx_ch_desc * rx_desc = &memmap->rx_descs[channel];
  565. PRINTD (DBG_FLOW, "hrz_open_rx %x", channel);
  566. spin_lock_irqsave (&dev->mem_lock, flags);
  567. channel_type = rd_mem (dev, &rx_desc->wr_buf_type) & BUFFER_PTR_MASK;
  568. spin_unlock_irqrestore (&dev->mem_lock, flags);
  569. // very serious error, should never occur
  570. if (channel_type != RX_CHANNEL_DISABLED) {
  571. PRINTD (DBG_ERR|DBG_VCC, "RX channel for VC already open");
  572. return -EBUSY; // clean up?
  573. }
  574. // Give back spare buffer
  575. if (dev->noof_spare_buffers) {
  576. buf_ptr = dev->spare_buffers[--dev->noof_spare_buffers];
  577. PRINTD (DBG_VCC, "using a spare buffer: %u", buf_ptr);
  578. // should never occur
  579. if (buf_ptr == RX_CHANNEL_DISABLED || buf_ptr == RX_CHANNEL_IDLE) {
  580. // but easy to recover from
  581. PRINTD (DBG_ERR|DBG_VCC, "bad spare buffer pointer, using IDLE");
  582. buf_ptr = RX_CHANNEL_IDLE;
  583. }
  584. } else {
  585. PRINTD (DBG_VCC, "using IDLE buffer pointer");
  586. }
  587. // Channel is currently disabled so change its status to idle
  588. // do we really need to save the flags again?
  589. spin_lock_irqsave (&dev->mem_lock, flags);
  590. wr_mem (dev, &rx_desc->wr_buf_type,
  591. buf_ptr | CHANNEL_TYPE_AAL5 | FIRST_CELL_OF_AAL5_FRAME);
  592. if (buf_ptr != RX_CHANNEL_IDLE)
  593. wr_mem (dev, &rx_desc->rd_buf_type, buf_ptr);
  594. spin_unlock_irqrestore (&dev->mem_lock, flags);
  595. // rxer->rate = make_rate (qos->peak_cells);
  596. PRINTD (DBG_FLOW, "hrz_open_rx ok");
  597. return 0;
  598. }
  599. #if 0
  600. /********** change vc rate for a given vc **********/
  601. static void hrz_change_vc_qos (ATM_RXER * rxer, MAAL_QOS * qos) {
  602. rxer->rate = make_rate (qos->peak_cells);
  603. }
  604. #endif
  605. /********** free an skb (as per ATM device driver documentation) **********/
  606. static void hrz_kfree_skb (struct sk_buff * skb) {
  607. if (ATM_SKB(skb)->vcc->pop) {
  608. ATM_SKB(skb)->vcc->pop (ATM_SKB(skb)->vcc, skb);
  609. } else {
  610. dev_kfree_skb_any (skb);
  611. }
  612. }
  613. /********** cancel listen on a VC **********/
  614. static void hrz_close_rx (hrz_dev * dev, u16 vc) {
  615. unsigned long flags;
  616. u32 value;
  617. u32 r1, r2;
  618. rx_ch_desc * rx_desc = &memmap->rx_descs[vc];
  619. int was_idle = 0;
  620. spin_lock_irqsave (&dev->mem_lock, flags);
  621. value = rd_mem (dev, &rx_desc->wr_buf_type) & BUFFER_PTR_MASK;
  622. spin_unlock_irqrestore (&dev->mem_lock, flags);
  623. if (value == RX_CHANNEL_DISABLED) {
  624. // I suppose this could happen once we deal with _NONE traffic properly
  625. PRINTD (DBG_VCC, "closing VC: RX channel %u already disabled", vc);
  626. return;
  627. }
  628. if (value == RX_CHANNEL_IDLE)
  629. was_idle = 1;
  630. spin_lock_irqsave (&dev->mem_lock, flags);
  631. for (;;) {
  632. wr_mem (dev, &rx_desc->wr_buf_type, RX_CHANNEL_DISABLED);
  633. if ((rd_mem (dev, &rx_desc->wr_buf_type) & BUFFER_PTR_MASK) == RX_CHANNEL_DISABLED)
  634. break;
  635. was_idle = 0;
  636. }
  637. if (was_idle) {
  638. spin_unlock_irqrestore (&dev->mem_lock, flags);
  639. return;
  640. }
  641. WAIT_FLUSH_RX_COMPLETE(dev);
  642. // XXX Is this all really necessary? We can rely on the rx_data_av
  643. // handler to discard frames that remain queued for delivery. If the
  644. // worry is that immediately reopening the channel (perhaps by a
  645. // different process) may cause some data to be mis-delivered then
  646. // there may still be a simpler solution (such as busy-waiting on
  647. // rx_busy once the channel is disabled or before a new one is
  648. // opened - does this leave any holes?). Arguably setting up and
  649. // tearing down the TX and RX halves of each virtual circuit could
  650. // most safely be done within ?x_busy protected regions.
  651. // OK, current changes are that Simon's marker is disabled and we DO
  652. // look for NULL rxer elsewhere. The code here seems flush frames
  653. // and then remember the last dead cell belonging to the channel
  654. // just disabled - the cell gets relinked at the next vc_open.
  655. // However, when all VCs are closed or only a few opened there are a
  656. // handful of buffers that are unusable.
  657. // Does anyone feel like documenting spare_buffers properly?
  658. // Does anyone feel like fixing this in a nicer way?
  659. // Flush any data which is left in the channel
  660. for (;;) {
  661. // Change the rx channel port to something different to the RX
  662. // channel we are trying to close to force Horizon to flush the rx
  663. // channel read and write pointers.
  664. u16 other = vc^(RX_CHANS/2);
  665. SELECT_RX_CHANNEL (dev, other);
  666. WAIT_UPDATE_COMPLETE (dev);
  667. r1 = rd_mem (dev, &rx_desc->rd_buf_type);
  668. // Select this RX channel. Flush doesn't seem to work unless we
  669. // select an RX channel before hand
  670. SELECT_RX_CHANNEL (dev, vc);
  671. WAIT_UPDATE_COMPLETE (dev);
  672. // Attempt to flush a frame on this RX channel
  673. FLUSH_RX_CHANNEL (dev, vc);
  674. WAIT_FLUSH_RX_COMPLETE (dev);
  675. // Force Horizon to flush rx channel read and write pointers as before
  676. SELECT_RX_CHANNEL (dev, other);
  677. WAIT_UPDATE_COMPLETE (dev);
  678. r2 = rd_mem (dev, &rx_desc->rd_buf_type);
  679. PRINTD (DBG_VCC|DBG_RX, "r1 = %u, r2 = %u", r1, r2);
  680. if (r1 == r2) {
  681. dev->spare_buffers[dev->noof_spare_buffers++] = (u16)r1;
  682. break;
  683. }
  684. }
  685. #if 0
  686. {
  687. rx_q_entry * wr_ptr = &memmap->rx_q_entries[rd_regw (dev, RX_QUEUE_WR_PTR_OFF)];
  688. rx_q_entry * rd_ptr = dev->rx_q_entry;
  689. PRINTD (DBG_VCC|DBG_RX, "rd_ptr = %u, wr_ptr = %u", rd_ptr, wr_ptr);
  690. while (rd_ptr != wr_ptr) {
  691. u32 x = rd_mem (dev, (HDW *) rd_ptr);
  692. if (vc == rx_q_entry_to_rx_channel (x)) {
  693. x |= SIMONS_DODGEY_MARKER;
  694. PRINTD (DBG_RX|DBG_VCC|DBG_WARN, "marking a frame as dodgey");
  695. wr_mem (dev, (HDW *) rd_ptr, x);
  696. }
  697. if (rd_ptr == dev->rx_q_wrap)
  698. rd_ptr = dev->rx_q_reset;
  699. else
  700. rd_ptr++;
  701. }
  702. }
  703. #endif
  704. spin_unlock_irqrestore (&dev->mem_lock, flags);
  705. return;
  706. }
  707. /********** schedule RX transfers **********/
  708. // Note on tail recursion: a GCC developer said that it is not likely
  709. // to be fixed soon, so do not define TAILRECUSRIONWORKS unless you
  710. // are sure it does as you may otherwise overflow the kernel stack.
  711. // giving this fn a return value would help GCC, allegedly
  712. static void rx_schedule (hrz_dev * dev, int irq) {
  713. unsigned int rx_bytes;
  714. int pio_instead = 0;
  715. #ifndef TAILRECURSIONWORKS
  716. pio_instead = 1;
  717. while (pio_instead) {
  718. #endif
  719. // bytes waiting for RX transfer
  720. rx_bytes = dev->rx_bytes;
  721. #if 0
  722. spin_count = 0;
  723. while (rd_regl (dev, MASTER_RX_COUNT_REG_OFF)) {
  724. PRINTD (DBG_RX|DBG_WARN, "RX error: other PCI Bus Master RX still in progress!");
  725. if (++spin_count > 10) {
  726. PRINTD (DBG_RX|DBG_ERR, "spun out waiting PCI Bus Master RX completion");
  727. wr_regl (dev, MASTER_RX_COUNT_REG_OFF, 0);
  728. clear_bit (rx_busy, &dev->flags);
  729. hrz_kfree_skb (dev->rx_skb);
  730. return;
  731. }
  732. }
  733. #endif
  734. // this code follows the TX code but (at the moment) there is only
  735. // one region - the skb itself. I don't know if this will change,
  736. // but it doesn't hurt to have the code here, disabled.
  737. if (rx_bytes) {
  738. // start next transfer within same region
  739. if (rx_bytes <= MAX_PIO_COUNT) {
  740. PRINTD (DBG_RX|DBG_BUS, "(pio)");
  741. pio_instead = 1;
  742. }
  743. if (rx_bytes <= MAX_TRANSFER_COUNT) {
  744. PRINTD (DBG_RX|DBG_BUS, "(simple or last multi)");
  745. dev->rx_bytes = 0;
  746. } else {
  747. PRINTD (DBG_RX|DBG_BUS, "(continuing multi)");
  748. dev->rx_bytes = rx_bytes - MAX_TRANSFER_COUNT;
  749. rx_bytes = MAX_TRANSFER_COUNT;
  750. }
  751. } else {
  752. // rx_bytes == 0 -- we're between regions
  753. // regions remaining to transfer
  754. #if 0
  755. unsigned int rx_regions = dev->rx_regions;
  756. #else
  757. unsigned int rx_regions = 0;
  758. #endif
  759. if (rx_regions) {
  760. #if 0
  761. // start a new region
  762. dev->rx_addr = dev->rx_iovec->iov_base;
  763. rx_bytes = dev->rx_iovec->iov_len;
  764. ++dev->rx_iovec;
  765. dev->rx_regions = rx_regions - 1;
  766. if (rx_bytes <= MAX_PIO_COUNT) {
  767. PRINTD (DBG_RX|DBG_BUS, "(pio)");
  768. pio_instead = 1;
  769. }
  770. if (rx_bytes <= MAX_TRANSFER_COUNT) {
  771. PRINTD (DBG_RX|DBG_BUS, "(full region)");
  772. dev->rx_bytes = 0;
  773. } else {
  774. PRINTD (DBG_RX|DBG_BUS, "(start multi region)");
  775. dev->rx_bytes = rx_bytes - MAX_TRANSFER_COUNT;
  776. rx_bytes = MAX_TRANSFER_COUNT;
  777. }
  778. #endif
  779. } else {
  780. // rx_regions == 0
  781. // that's all folks - end of frame
  782. struct sk_buff * skb = dev->rx_skb;
  783. // dev->rx_iovec = 0;
  784. FLUSH_RX_CHANNEL (dev, dev->rx_channel);
  785. dump_skb ("<<<", dev->rx_channel, skb);
  786. PRINTD (DBG_RX|DBG_SKB, "push %p %u", skb->data, skb->len);
  787. {
  788. struct atm_vcc * vcc = ATM_SKB(skb)->vcc;
  789. // VC layer stats
  790. atomic_inc(&vcc->stats->rx);
  791. __net_timestamp(skb);
  792. // end of our responsibility
  793. vcc->push (vcc, skb);
  794. }
  795. }
  796. }
  797. // note: writing RX_COUNT clears any interrupt condition
  798. if (rx_bytes) {
  799. if (pio_instead) {
  800. if (irq)
  801. wr_regl (dev, MASTER_RX_COUNT_REG_OFF, 0);
  802. rds_regb (dev, DATA_PORT_OFF, dev->rx_addr, rx_bytes);
  803. } else {
  804. wr_regl (dev, MASTER_RX_ADDR_REG_OFF, virt_to_bus (dev->rx_addr));
  805. wr_regl (dev, MASTER_RX_COUNT_REG_OFF, rx_bytes);
  806. }
  807. dev->rx_addr += rx_bytes;
  808. } else {
  809. if (irq)
  810. wr_regl (dev, MASTER_RX_COUNT_REG_OFF, 0);
  811. // allow another RX thread to start
  812. YELLOW_LED_ON(dev);
  813. clear_bit (rx_busy, &dev->flags);
  814. PRINTD (DBG_RX, "cleared rx_busy for dev %p", dev);
  815. }
  816. #ifdef TAILRECURSIONWORKS
  817. // and we all bless optimised tail calls
  818. if (pio_instead)
  819. return rx_schedule (dev, 0);
  820. return;
  821. #else
  822. // grrrrrrr!
  823. irq = 0;
  824. }
  825. return;
  826. #endif
  827. }
  828. /********** handle RX bus master complete events **********/
  829. static void rx_bus_master_complete_handler (hrz_dev * dev) {
  830. if (test_bit (rx_busy, &dev->flags)) {
  831. rx_schedule (dev, 1);
  832. } else {
  833. PRINTD (DBG_RX|DBG_ERR, "unexpected RX bus master completion");
  834. // clear interrupt condition on adapter
  835. wr_regl (dev, MASTER_RX_COUNT_REG_OFF, 0);
  836. }
  837. return;
  838. }
  839. /********** (queue to) become the next TX thread **********/
  840. static int tx_hold (hrz_dev * dev) {
  841. PRINTD (DBG_TX, "sleeping at tx lock %p %lu", dev, dev->flags);
  842. wait_event_interruptible(dev->tx_queue, (!test_and_set_bit(tx_busy, &dev->flags)));
  843. PRINTD (DBG_TX, "woken at tx lock %p %lu", dev, dev->flags);
  844. if (signal_pending (current))
  845. return -1;
  846. PRINTD (DBG_TX, "set tx_busy for dev %p", dev);
  847. return 0;
  848. }
  849. /********** allow another TX thread to start **********/
  850. static inline void tx_release (hrz_dev * dev) {
  851. clear_bit (tx_busy, &dev->flags);
  852. PRINTD (DBG_TX, "cleared tx_busy for dev %p", dev);
  853. wake_up_interruptible (&dev->tx_queue);
  854. }
  855. /********** schedule TX transfers **********/
  856. static void tx_schedule (hrz_dev * const dev, int irq) {
  857. unsigned int tx_bytes;
  858. int append_desc = 0;
  859. int pio_instead = 0;
  860. #ifndef TAILRECURSIONWORKS
  861. pio_instead = 1;
  862. while (pio_instead) {
  863. #endif
  864. // bytes in current region waiting for TX transfer
  865. tx_bytes = dev->tx_bytes;
  866. #if 0
  867. spin_count = 0;
  868. while (rd_regl (dev, MASTER_TX_COUNT_REG_OFF)) {
  869. PRINTD (DBG_TX|DBG_WARN, "TX error: other PCI Bus Master TX still in progress!");
  870. if (++spin_count > 10) {
  871. PRINTD (DBG_TX|DBG_ERR, "spun out waiting PCI Bus Master TX completion");
  872. wr_regl (dev, MASTER_TX_COUNT_REG_OFF, 0);
  873. tx_release (dev);
  874. hrz_kfree_skb (dev->tx_skb);
  875. return;
  876. }
  877. }
  878. #endif
  879. if (tx_bytes) {
  880. // start next transfer within same region
  881. if (!test_bit (ultra, &dev->flags) || tx_bytes <= MAX_PIO_COUNT) {
  882. PRINTD (DBG_TX|DBG_BUS, "(pio)");
  883. pio_instead = 1;
  884. }
  885. if (tx_bytes <= MAX_TRANSFER_COUNT) {
  886. PRINTD (DBG_TX|DBG_BUS, "(simple or last multi)");
  887. if (!dev->tx_iovec) {
  888. // end of last region
  889. append_desc = 1;
  890. }
  891. dev->tx_bytes = 0;
  892. } else {
  893. PRINTD (DBG_TX|DBG_BUS, "(continuing multi)");
  894. dev->tx_bytes = tx_bytes - MAX_TRANSFER_COUNT;
  895. tx_bytes = MAX_TRANSFER_COUNT;
  896. }
  897. } else {
  898. // tx_bytes == 0 -- we're between regions
  899. // regions remaining to transfer
  900. unsigned int tx_regions = dev->tx_regions;
  901. if (tx_regions) {
  902. // start a new region
  903. dev->tx_addr = dev->tx_iovec->iov_base;
  904. tx_bytes = dev->tx_iovec->iov_len;
  905. ++dev->tx_iovec;
  906. dev->tx_regions = tx_regions - 1;
  907. if (!test_bit (ultra, &dev->flags) || tx_bytes <= MAX_PIO_COUNT) {
  908. PRINTD (DBG_TX|DBG_BUS, "(pio)");
  909. pio_instead = 1;
  910. }
  911. if (tx_bytes <= MAX_TRANSFER_COUNT) {
  912. PRINTD (DBG_TX|DBG_BUS, "(full region)");
  913. dev->tx_bytes = 0;
  914. } else {
  915. PRINTD (DBG_TX|DBG_BUS, "(start multi region)");
  916. dev->tx_bytes = tx_bytes - MAX_TRANSFER_COUNT;
  917. tx_bytes = MAX_TRANSFER_COUNT;
  918. }
  919. } else {
  920. // tx_regions == 0
  921. // that's all folks - end of frame
  922. struct sk_buff * skb = dev->tx_skb;
  923. dev->tx_iovec = NULL;
  924. // VC layer stats
  925. atomic_inc(&ATM_SKB(skb)->vcc->stats->tx);
  926. // free the skb
  927. hrz_kfree_skb (skb);
  928. }
  929. }
  930. // note: writing TX_COUNT clears any interrupt condition
  931. if (tx_bytes) {
  932. if (pio_instead) {
  933. if (irq)
  934. wr_regl (dev, MASTER_TX_COUNT_REG_OFF, 0);
  935. wrs_regb (dev, DATA_PORT_OFF, dev->tx_addr, tx_bytes);
  936. if (append_desc)
  937. wr_regl (dev, TX_DESCRIPTOR_PORT_OFF, cpu_to_be32 (dev->tx_skb->len));
  938. } else {
  939. wr_regl (dev, MASTER_TX_ADDR_REG_OFF, virt_to_bus (dev->tx_addr));
  940. if (append_desc)
  941. wr_regl (dev, TX_DESCRIPTOR_REG_OFF, cpu_to_be32 (dev->tx_skb->len));
  942. wr_regl (dev, MASTER_TX_COUNT_REG_OFF,
  943. append_desc
  944. ? tx_bytes | MASTER_TX_AUTO_APPEND_DESC
  945. : tx_bytes);
  946. }
  947. dev->tx_addr += tx_bytes;
  948. } else {
  949. if (irq)
  950. wr_regl (dev, MASTER_TX_COUNT_REG_OFF, 0);
  951. YELLOW_LED_ON(dev);
  952. tx_release (dev);
  953. }
  954. #ifdef TAILRECURSIONWORKS
  955. // and we all bless optimised tail calls
  956. if (pio_instead)
  957. return tx_schedule (dev, 0);
  958. return;
  959. #else
  960. // grrrrrrr!
  961. irq = 0;
  962. }
  963. return;
  964. #endif
  965. }
  966. /********** handle TX bus master complete events **********/
  967. static void tx_bus_master_complete_handler (hrz_dev * dev) {
  968. if (test_bit (tx_busy, &dev->flags)) {
  969. tx_schedule (dev, 1);
  970. } else {
  971. PRINTD (DBG_TX|DBG_ERR, "unexpected TX bus master completion");
  972. // clear interrupt condition on adapter
  973. wr_regl (dev, MASTER_TX_COUNT_REG_OFF, 0);
  974. }
  975. return;
  976. }
  977. /********** move RX Q pointer to next item in circular buffer **********/
  978. // called only from IRQ sub-handler
  979. static u32 rx_queue_entry_next (hrz_dev * dev) {
  980. u32 rx_queue_entry;
  981. spin_lock (&dev->mem_lock);
  982. rx_queue_entry = rd_mem (dev, &dev->rx_q_entry->entry);
  983. if (dev->rx_q_entry == dev->rx_q_wrap)
  984. dev->rx_q_entry = dev->rx_q_reset;
  985. else
  986. dev->rx_q_entry++;
  987. wr_regw (dev, RX_QUEUE_RD_PTR_OFF, dev->rx_q_entry - dev->rx_q_reset);
  988. spin_unlock (&dev->mem_lock);
  989. return rx_queue_entry;
  990. }
  991. /********** handle RX data received by device **********/
  992. // called from IRQ handler
  993. static void rx_data_av_handler (hrz_dev * dev) {
  994. u32 rx_queue_entry;
  995. u32 rx_queue_entry_flags;
  996. u16 rx_len;
  997. u16 rx_channel;
  998. PRINTD (DBG_FLOW, "hrz_data_av_handler");
  999. // try to grab rx lock (not possible during RX bus mastering)
  1000. if (test_and_set_bit (rx_busy, &dev->flags)) {
  1001. PRINTD (DBG_RX, "locked out of rx lock");
  1002. return;
  1003. }
  1004. PRINTD (DBG_RX, "set rx_busy for dev %p", dev);
  1005. // lock is cleared if we fail now, o/w after bus master completion
  1006. YELLOW_LED_OFF(dev);
  1007. rx_queue_entry = rx_queue_entry_next (dev);
  1008. rx_len = rx_q_entry_to_length (rx_queue_entry);
  1009. rx_channel = rx_q_entry_to_rx_channel (rx_queue_entry);
  1010. WAIT_FLUSH_RX_COMPLETE (dev);
  1011. SELECT_RX_CHANNEL (dev, rx_channel);
  1012. PRINTD (DBG_RX, "rx_queue_entry is: %#x", rx_queue_entry);
  1013. rx_queue_entry_flags = rx_queue_entry & (RX_CRC_32_OK|RX_COMPLETE_FRAME|SIMONS_DODGEY_MARKER);
  1014. if (!rx_len) {
  1015. // (at least) bus-mastering breaks if we try to handle a
  1016. // zero-length frame, besides AAL5 does not support them
  1017. PRINTK (KERN_ERR, "zero-length frame!");
  1018. rx_queue_entry_flags &= ~RX_COMPLETE_FRAME;
  1019. }
  1020. if (rx_queue_entry_flags & SIMONS_DODGEY_MARKER) {
  1021. PRINTD (DBG_RX|DBG_ERR, "Simon's marker detected!");
  1022. }
  1023. if (rx_queue_entry_flags == (RX_CRC_32_OK | RX_COMPLETE_FRAME)) {
  1024. struct atm_vcc * atm_vcc;
  1025. PRINTD (DBG_RX, "got a frame on rx_channel %x len %u", rx_channel, rx_len);
  1026. atm_vcc = dev->rxer[rx_channel];
  1027. // if no vcc is assigned to this channel, we should drop the frame
  1028. // (is this what SIMONS etc. was trying to achieve?)
  1029. if (atm_vcc) {
  1030. if (atm_vcc->qos.rxtp.traffic_class != ATM_NONE) {
  1031. if (rx_len <= atm_vcc->qos.rxtp.max_sdu) {
  1032. struct sk_buff * skb = atm_alloc_charge (atm_vcc, rx_len, GFP_ATOMIC);
  1033. if (skb) {
  1034. // remember this so we can push it later
  1035. dev->rx_skb = skb;
  1036. // remember this so we can flush it later
  1037. dev->rx_channel = rx_channel;
  1038. // prepare socket buffer
  1039. skb_put (skb, rx_len);
  1040. ATM_SKB(skb)->vcc = atm_vcc;
  1041. // simple transfer
  1042. // dev->rx_regions = 0;
  1043. // dev->rx_iovec = 0;
  1044. dev->rx_bytes = rx_len;
  1045. dev->rx_addr = skb->data;
  1046. PRINTD (DBG_RX, "RX start simple transfer (addr %p, len %d)",
  1047. skb->data, rx_len);
  1048. // do the business
  1049. rx_schedule (dev, 0);
  1050. return;
  1051. } else {
  1052. PRINTD (DBG_SKB|DBG_WARN, "failed to get skb");
  1053. }
  1054. } else {
  1055. PRINTK (KERN_INFO, "frame received on TX-only VC %x", rx_channel);
  1056. // do we count this?
  1057. }
  1058. } else {
  1059. PRINTK (KERN_WARNING, "dropped over-size frame");
  1060. // do we count this?
  1061. }
  1062. } else {
  1063. PRINTD (DBG_WARN|DBG_VCC|DBG_RX, "no VCC for this frame (VC closed)");
  1064. // do we count this?
  1065. }
  1066. } else {
  1067. // Wait update complete ? SPONG
  1068. }
  1069. // RX was aborted
  1070. YELLOW_LED_ON(dev);
  1071. FLUSH_RX_CHANNEL (dev,rx_channel);
  1072. clear_bit (rx_busy, &dev->flags);
  1073. return;
  1074. }
  1075. /********** interrupt handler **********/
  1076. static irqreturn_t interrupt_handler(int irq, void *dev_id)
  1077. {
  1078. hrz_dev *dev = dev_id;
  1079. u32 int_source;
  1080. unsigned int irq_ok;
  1081. PRINTD (DBG_FLOW, "interrupt_handler: %p", dev_id);
  1082. // definitely for us
  1083. irq_ok = 0;
  1084. while ((int_source = rd_regl (dev, INT_SOURCE_REG_OFF)
  1085. & INTERESTING_INTERRUPTS)) {
  1086. // In the interests of fairness, the handlers below are
  1087. // called in sequence and without immediate return to the head of
  1088. // the while loop. This is only of issue for slow hosts (or when
  1089. // debugging messages are on). Really slow hosts may find a fast
  1090. // sender keeps them permanently in the IRQ handler. :(
  1091. // (only an issue for slow hosts) RX completion goes before
  1092. // rx_data_av as the former implies rx_busy and so the latter
  1093. // would just abort. If it reschedules another transfer
  1094. // (continuing the same frame) then it will not clear rx_busy.
  1095. // (only an issue for slow hosts) TX completion goes before RX
  1096. // data available as it is a much shorter routine - there is the
  1097. // chance that any further transfers it schedules will be complete
  1098. // by the time of the return to the head of the while loop
  1099. if (int_source & RX_BUS_MASTER_COMPLETE) {
  1100. ++irq_ok;
  1101. PRINTD (DBG_IRQ|DBG_BUS|DBG_RX, "rx_bus_master_complete asserted");
  1102. rx_bus_master_complete_handler (dev);
  1103. }
  1104. if (int_source & TX_BUS_MASTER_COMPLETE) {
  1105. ++irq_ok;
  1106. PRINTD (DBG_IRQ|DBG_BUS|DBG_TX, "tx_bus_master_complete asserted");
  1107. tx_bus_master_complete_handler (dev);
  1108. }
  1109. if (int_source & RX_DATA_AV) {
  1110. ++irq_ok;
  1111. PRINTD (DBG_IRQ|DBG_RX, "rx_data_av asserted");
  1112. rx_data_av_handler (dev);
  1113. }
  1114. }
  1115. if (irq_ok) {
  1116. PRINTD (DBG_IRQ, "work done: %u", irq_ok);
  1117. } else {
  1118. PRINTD (DBG_IRQ|DBG_WARN, "spurious interrupt source: %#x", int_source);
  1119. }
  1120. PRINTD (DBG_IRQ|DBG_FLOW, "interrupt_handler done: %p", dev_id);
  1121. if (irq_ok)
  1122. return IRQ_HANDLED;
  1123. return IRQ_NONE;
  1124. }
  1125. /********** housekeeping **********/
  1126. static void do_housekeeping (struct timer_list *t) {
  1127. // just stats at the moment
  1128. hrz_dev * dev = from_timer(dev, t, housekeeping);
  1129. // collect device-specific (not driver/atm-linux) stats here
  1130. dev->tx_cell_count += rd_regw (dev, TX_CELL_COUNT_OFF);
  1131. dev->rx_cell_count += rd_regw (dev, RX_CELL_COUNT_OFF);
  1132. dev->hec_error_count += rd_regw (dev, HEC_ERROR_COUNT_OFF);
  1133. dev->unassigned_cell_count += rd_regw (dev, UNASSIGNED_CELL_COUNT_OFF);
  1134. mod_timer (&dev->housekeeping, jiffies + HZ/10);
  1135. return;
  1136. }
  1137. /********** find an idle channel for TX and set it up **********/
  1138. // called with tx_busy set
  1139. static short setup_idle_tx_channel (hrz_dev * dev, hrz_vcc * vcc) {
  1140. unsigned short idle_channels;
  1141. short tx_channel = -1;
  1142. unsigned int spin_count;
  1143. PRINTD (DBG_FLOW|DBG_TX, "setup_idle_tx_channel %p", dev);
  1144. // better would be to fail immediately, the caller can then decide whether
  1145. // to wait or drop (depending on whether this is UBR etc.)
  1146. spin_count = 0;
  1147. while (!(idle_channels = rd_regw (dev, TX_STATUS_OFF) & IDLE_CHANNELS_MASK)) {
  1148. PRINTD (DBG_TX|DBG_WARN, "waiting for idle TX channel");
  1149. // delay a bit here
  1150. if (++spin_count > 100) {
  1151. PRINTD (DBG_TX|DBG_ERR, "spun out waiting for idle TX channel");
  1152. return -EBUSY;
  1153. }
  1154. }
  1155. // got an idle channel
  1156. {
  1157. // tx_idle ensures we look for idle channels in RR order
  1158. int chan = dev->tx_idle;
  1159. int keep_going = 1;
  1160. while (keep_going) {
  1161. if (idle_channels & (1<<chan)) {
  1162. tx_channel = chan;
  1163. keep_going = 0;
  1164. }
  1165. ++chan;
  1166. if (chan == TX_CHANS)
  1167. chan = 0;
  1168. }
  1169. dev->tx_idle = chan;
  1170. }
  1171. // set up the channel we found
  1172. {
  1173. // Initialise the cell header in the transmit channel descriptor
  1174. // a.k.a. prepare the channel and remember that we have done so.
  1175. tx_ch_desc * tx_desc = &memmap->tx_descs[tx_channel];
  1176. u32 rd_ptr;
  1177. u32 wr_ptr;
  1178. u16 channel = vcc->channel;
  1179. unsigned long flags;
  1180. spin_lock_irqsave (&dev->mem_lock, flags);
  1181. // Update the transmit channel record.
  1182. dev->tx_channel_record[tx_channel] = channel;
  1183. // xBR channel
  1184. update_tx_channel_config (dev, tx_channel, RATE_TYPE_ACCESS,
  1185. vcc->tx_xbr_bits);
  1186. // Update the PCR counter preload value etc.
  1187. update_tx_channel_config (dev, tx_channel, PCR_TIMER_ACCESS,
  1188. vcc->tx_pcr_bits);
  1189. #if 0
  1190. if (vcc->tx_xbr_bits == VBR_RATE_TYPE) {
  1191. // SCR timer
  1192. update_tx_channel_config (dev, tx_channel, SCR_TIMER_ACCESS,
  1193. vcc->tx_scr_bits);
  1194. // Bucket size...
  1195. update_tx_channel_config (dev, tx_channel, BUCKET_CAPACITY_ACCESS,
  1196. vcc->tx_bucket_bits);
  1197. // ... and fullness
  1198. update_tx_channel_config (dev, tx_channel, BUCKET_FULLNESS_ACCESS,
  1199. vcc->tx_bucket_bits);
  1200. }
  1201. #endif
  1202. // Initialise the read and write buffer pointers
  1203. rd_ptr = rd_mem (dev, &tx_desc->rd_buf_type) & BUFFER_PTR_MASK;
  1204. wr_ptr = rd_mem (dev, &tx_desc->wr_buf_type) & BUFFER_PTR_MASK;
  1205. // idle TX channels should have identical pointers
  1206. if (rd_ptr != wr_ptr) {
  1207. PRINTD (DBG_TX|DBG_ERR, "TX buffer pointers are broken!");
  1208. // spin_unlock... return -E...
  1209. // I wonder if gcc would get rid of one of the pointer aliases
  1210. }
  1211. PRINTD (DBG_TX, "TX buffer pointers are: rd %x, wr %x.",
  1212. rd_ptr, wr_ptr);
  1213. switch (vcc->aal) {
  1214. case aal0:
  1215. PRINTD (DBG_QOS|DBG_TX, "tx_channel: aal0");
  1216. rd_ptr |= CHANNEL_TYPE_RAW_CELLS;
  1217. wr_ptr |= CHANNEL_TYPE_RAW_CELLS;
  1218. break;
  1219. case aal34:
  1220. PRINTD (DBG_QOS|DBG_TX, "tx_channel: aal34");
  1221. rd_ptr |= CHANNEL_TYPE_AAL3_4;
  1222. wr_ptr |= CHANNEL_TYPE_AAL3_4;
  1223. break;
  1224. case aal5:
  1225. rd_ptr |= CHANNEL_TYPE_AAL5;
  1226. wr_ptr |= CHANNEL_TYPE_AAL5;
  1227. // Initialise the CRC
  1228. wr_mem (dev, &tx_desc->partial_crc, INITIAL_CRC);
  1229. break;
  1230. }
  1231. wr_mem (dev, &tx_desc->rd_buf_type, rd_ptr);
  1232. wr_mem (dev, &tx_desc->wr_buf_type, wr_ptr);
  1233. // Write the Cell Header
  1234. // Payload Type, CLP and GFC would go here if non-zero
  1235. wr_mem (dev, &tx_desc->cell_header, channel);
  1236. spin_unlock_irqrestore (&dev->mem_lock, flags);
  1237. }
  1238. return tx_channel;
  1239. }
  1240. /********** send a frame **********/
  1241. static int hrz_send (struct atm_vcc * atm_vcc, struct sk_buff * skb) {
  1242. unsigned int spin_count;
  1243. int free_buffers;
  1244. hrz_dev * dev = HRZ_DEV(atm_vcc->dev);
  1245. hrz_vcc * vcc = HRZ_VCC(atm_vcc);
  1246. u16 channel = vcc->channel;
  1247. u32 buffers_required;
  1248. /* signed for error return */
  1249. short tx_channel;
  1250. PRINTD (DBG_FLOW|DBG_TX, "hrz_send vc %x data %p len %u",
  1251. channel, skb->data, skb->len);
  1252. dump_skb (">>>", channel, skb);
  1253. if (atm_vcc->qos.txtp.traffic_class == ATM_NONE) {
  1254. PRINTK (KERN_ERR, "attempt to send on RX-only VC %x", channel);
  1255. hrz_kfree_skb (skb);
  1256. return -EIO;
  1257. }
  1258. // don't understand this
  1259. ATM_SKB(skb)->vcc = atm_vcc;
  1260. if (skb->len > atm_vcc->qos.txtp.max_sdu) {
  1261. PRINTK (KERN_ERR, "sk_buff length greater than agreed max_sdu, dropping...");
  1262. hrz_kfree_skb (skb);
  1263. return -EIO;
  1264. }
  1265. if (!channel) {
  1266. PRINTD (DBG_ERR|DBG_TX, "attempt to transmit on zero (rx_)channel");
  1267. hrz_kfree_skb (skb);
  1268. return -EIO;
  1269. }
  1270. #if 0
  1271. {
  1272. // where would be a better place for this? housekeeping?
  1273. u16 status;
  1274. pci_read_config_word (dev->pci_dev, PCI_STATUS, &status);
  1275. if (status & PCI_STATUS_REC_MASTER_ABORT) {
  1276. PRINTD (DBG_BUS|DBG_ERR, "Clearing PCI Master Abort (and cleaning up)");
  1277. status &= ~PCI_STATUS_REC_MASTER_ABORT;
  1278. pci_write_config_word (dev->pci_dev, PCI_STATUS, status);
  1279. if (test_bit (tx_busy, &dev->flags)) {
  1280. hrz_kfree_skb (dev->tx_skb);
  1281. tx_release (dev);
  1282. }
  1283. }
  1284. }
  1285. #endif
  1286. #ifdef DEBUG_HORIZON
  1287. /* wey-hey! */
  1288. if (channel == 1023) {
  1289. unsigned int i;
  1290. unsigned short d = 0;
  1291. char * s = skb->data;
  1292. if (*s++ == 'D') {
  1293. for (i = 0; i < 4; ++i)
  1294. d = (d << 4) | hex_to_bin(*s++);
  1295. PRINTK (KERN_INFO, "debug bitmap is now %hx", debug = d);
  1296. }
  1297. }
  1298. #endif
  1299. // wait until TX is free and grab lock
  1300. if (tx_hold (dev)) {
  1301. hrz_kfree_skb (skb);
  1302. return -ERESTARTSYS;
  1303. }
  1304. // Wait for enough space to be available in transmit buffer memory.
  1305. // should be number of cells needed + 2 (according to hardware docs)
  1306. // = ((framelen+8)+47) / 48 + 2
  1307. // = (framelen+7) / 48 + 3, hmm... faster to put addition inside XXX
  1308. buffers_required = (skb->len+(ATM_AAL5_TRAILER-1)) / ATM_CELL_PAYLOAD + 3;
  1309. // replace with timer and sleep, add dev->tx_buffers_queue (max 1 entry)
  1310. spin_count = 0;
  1311. while ((free_buffers = rd_regw (dev, TX_FREE_BUFFER_COUNT_OFF)) < buffers_required) {
  1312. PRINTD (DBG_TX, "waiting for free TX buffers, got %d of %d",
  1313. free_buffers, buffers_required);
  1314. // what is the appropriate delay? implement a timeout? (depending on line speed?)
  1315. // mdelay (1);
  1316. // what happens if we kill (current_pid, SIGKILL) ?
  1317. schedule();
  1318. if (++spin_count > 1000) {
  1319. PRINTD (DBG_TX|DBG_ERR, "spun out waiting for tx buffers, got %d of %d",
  1320. free_buffers, buffers_required);
  1321. tx_release (dev);
  1322. hrz_kfree_skb (skb);
  1323. return -ERESTARTSYS;
  1324. }
  1325. }
  1326. // Select a channel to transmit the frame on.
  1327. if (channel == dev->last_vc) {
  1328. PRINTD (DBG_TX, "last vc hack: hit");
  1329. tx_channel = dev->tx_last;
  1330. } else {
  1331. PRINTD (DBG_TX, "last vc hack: miss");
  1332. // Are we currently transmitting this VC on one of the channels?
  1333. for (tx_channel = 0; tx_channel < TX_CHANS; ++tx_channel)
  1334. if (dev->tx_channel_record[tx_channel] == channel) {
  1335. PRINTD (DBG_TX, "vc already on channel: hit");
  1336. break;
  1337. }
  1338. if (tx_channel == TX_CHANS) {
  1339. PRINTD (DBG_TX, "vc already on channel: miss");
  1340. // Find and set up an idle channel.
  1341. tx_channel = setup_idle_tx_channel (dev, vcc);
  1342. if (tx_channel < 0) {
  1343. PRINTD (DBG_TX|DBG_ERR, "failed to get channel");
  1344. tx_release (dev);
  1345. return tx_channel;
  1346. }
  1347. }
  1348. PRINTD (DBG_TX, "got channel");
  1349. SELECT_TX_CHANNEL(dev, tx_channel);
  1350. dev->last_vc = channel;
  1351. dev->tx_last = tx_channel;
  1352. }
  1353. PRINTD (DBG_TX, "using channel %u", tx_channel);
  1354. YELLOW_LED_OFF(dev);
  1355. // TX start transfer
  1356. {
  1357. unsigned int tx_len = skb->len;
  1358. unsigned int tx_iovcnt = skb_shinfo(skb)->nr_frags;
  1359. // remember this so we can free it later
  1360. dev->tx_skb = skb;
  1361. if (tx_iovcnt) {
  1362. // scatter gather transfer
  1363. dev->tx_regions = tx_iovcnt;
  1364. dev->tx_iovec = NULL; /* @@@ needs rewritten */
  1365. dev->tx_bytes = 0;
  1366. PRINTD (DBG_TX|DBG_BUS, "TX start scatter-gather transfer (iovec %p, len %d)",
  1367. skb->data, tx_len);
  1368. tx_release (dev);
  1369. hrz_kfree_skb (skb);
  1370. return -EIO;
  1371. } else {
  1372. // simple transfer
  1373. dev->tx_regions = 0;
  1374. dev->tx_iovec = NULL;
  1375. dev->tx_bytes = tx_len;
  1376. dev->tx_addr = skb->data;
  1377. PRINTD (DBG_TX|DBG_BUS, "TX start simple transfer (addr %p, len %d)",
  1378. skb->data, tx_len);
  1379. }
  1380. // and do the business
  1381. tx_schedule (dev, 0);
  1382. }
  1383. return 0;
  1384. }
  1385. /********** reset a card **********/
  1386. static void hrz_reset (const hrz_dev * dev) {
  1387. u32 control_0_reg = rd_regl (dev, CONTROL_0_REG);
  1388. // why not set RESET_HORIZON to one and wait for the card to
  1389. // reassert that bit as zero? Like so:
  1390. control_0_reg = control_0_reg & RESET_HORIZON;
  1391. wr_regl (dev, CONTROL_0_REG, control_0_reg);
  1392. while (control_0_reg & RESET_HORIZON)
  1393. control_0_reg = rd_regl (dev, CONTROL_0_REG);
  1394. // old reset code retained:
  1395. wr_regl (dev, CONTROL_0_REG, control_0_reg |
  1396. RESET_ATM | RESET_RX | RESET_TX | RESET_HOST);
  1397. // just guessing here
  1398. udelay (1000);
  1399. wr_regl (dev, CONTROL_0_REG, control_0_reg);
  1400. }
  1401. /********** read the burnt in address **********/
  1402. static void WRITE_IT_WAIT (const hrz_dev *dev, u32 ctrl)
  1403. {
  1404. wr_regl (dev, CONTROL_0_REG, ctrl);
  1405. udelay (5);
  1406. }
  1407. static void CLOCK_IT (const hrz_dev *dev, u32 ctrl)
  1408. {
  1409. // DI must be valid around rising SK edge
  1410. WRITE_IT_WAIT(dev, ctrl & ~SEEPROM_SK);
  1411. WRITE_IT_WAIT(dev, ctrl | SEEPROM_SK);
  1412. }
  1413. static u16 read_bia(const hrz_dev *dev, u16 addr)
  1414. {
  1415. u32 ctrl = rd_regl (dev, CONTROL_0_REG);
  1416. const unsigned int addr_bits = 6;
  1417. const unsigned int data_bits = 16;
  1418. unsigned int i;
  1419. u16 res;
  1420. ctrl &= ~(SEEPROM_CS | SEEPROM_SK | SEEPROM_DI);
  1421. WRITE_IT_WAIT(dev, ctrl);
  1422. // wake Serial EEPROM and send 110 (READ) command
  1423. ctrl |= (SEEPROM_CS | SEEPROM_DI);
  1424. CLOCK_IT(dev, ctrl);
  1425. ctrl |= SEEPROM_DI;
  1426. CLOCK_IT(dev, ctrl);
  1427. ctrl &= ~SEEPROM_DI;
  1428. CLOCK_IT(dev, ctrl);
  1429. for (i=0; i<addr_bits; i++) {
  1430. if (addr & (1 << (addr_bits-1)))
  1431. ctrl |= SEEPROM_DI;
  1432. else
  1433. ctrl &= ~SEEPROM_DI;
  1434. CLOCK_IT(dev, ctrl);
  1435. addr = addr << 1;
  1436. }
  1437. // we could check that we have DO = 0 here
  1438. ctrl &= ~SEEPROM_DI;
  1439. res = 0;
  1440. for (i=0;i<data_bits;i++) {
  1441. res = res >> 1;
  1442. CLOCK_IT(dev, ctrl);
  1443. if (rd_regl (dev, CONTROL_0_REG) & SEEPROM_DO)
  1444. res |= (1 << (data_bits-1));
  1445. }
  1446. ctrl &= ~(SEEPROM_SK | SEEPROM_CS);
  1447. WRITE_IT_WAIT(dev, ctrl);
  1448. return res;
  1449. }
  1450. /********** initialise a card **********/
  1451. static int hrz_init(hrz_dev *dev)
  1452. {
  1453. int onefivefive;
  1454. u16 chan;
  1455. int buff_count;
  1456. HDW * mem;
  1457. cell_buf * tx_desc;
  1458. cell_buf * rx_desc;
  1459. u32 ctrl;
  1460. ctrl = rd_regl (dev, CONTROL_0_REG);
  1461. PRINTD (DBG_INFO, "ctrl0reg is %#x", ctrl);
  1462. onefivefive = ctrl & ATM_LAYER_STATUS;
  1463. if (onefivefive)
  1464. printk (DEV_LABEL ": Horizon Ultra (at 155.52 MBps)");
  1465. else
  1466. printk (DEV_LABEL ": Horizon (at 25 MBps)");
  1467. printk (":");
  1468. // Reset the card to get everything in a known state
  1469. printk (" reset");
  1470. hrz_reset (dev);
  1471. // Clear all the buffer memory
  1472. printk (" clearing memory");
  1473. for (mem = (HDW *) memmap; mem < (HDW *) (memmap + 1); ++mem)
  1474. wr_mem (dev, mem, 0);
  1475. printk (" tx channels");
  1476. // All transmit eight channels are set up as AAL5 ABR channels with
  1477. // a 16us cell spacing. Why?
  1478. // Channel 0 gets the free buffer at 100h, channel 1 gets the free
  1479. // buffer at 110h etc.
  1480. for (chan = 0; chan < TX_CHANS; ++chan) {
  1481. tx_ch_desc * tx_desc = &memmap->tx_descs[chan];
  1482. cell_buf * buf = &memmap->inittxbufs[chan];
  1483. // initialise the read and write buffer pointers
  1484. wr_mem (dev, &tx_desc->rd_buf_type, BUF_PTR(buf));
  1485. wr_mem (dev, &tx_desc->wr_buf_type, BUF_PTR(buf));
  1486. // set the status of the initial buffers to empty
  1487. wr_mem (dev, &buf->next, BUFF_STATUS_EMPTY);
  1488. }
  1489. // Use space bufn3 at the moment for tx buffers
  1490. printk (" tx buffers");
  1491. tx_desc = memmap->bufn3;
  1492. wr_mem (dev, &memmap->txfreebufstart.next, BUF_PTR(tx_desc) | BUFF_STATUS_EMPTY);
  1493. for (buff_count = 0; buff_count < BUFN3_SIZE-1; buff_count++) {
  1494. wr_mem (dev, &tx_desc->next, BUF_PTR(tx_desc+1) | BUFF_STATUS_EMPTY);
  1495. tx_desc++;
  1496. }
  1497. wr_mem (dev, &tx_desc->next, BUF_PTR(&memmap->txfreebufend) | BUFF_STATUS_EMPTY);
  1498. // Initialise the transmit free buffer count
  1499. wr_regw (dev, TX_FREE_BUFFER_COUNT_OFF, BUFN3_SIZE);
  1500. printk (" rx channels");
  1501. // Initialise all of the receive channels to be AAL5 disabled with
  1502. // an interrupt threshold of 0
  1503. for (chan = 0; chan < RX_CHANS; ++chan) {
  1504. rx_ch_desc * rx_desc = &memmap->rx_descs[chan];
  1505. wr_mem (dev, &rx_desc->wr_buf_type, CHANNEL_TYPE_AAL5 | RX_CHANNEL_DISABLED);
  1506. }
  1507. printk (" rx buffers");
  1508. // Use space bufn4 at the moment for rx buffers
  1509. rx_desc = memmap->bufn4;
  1510. wr_mem (dev, &memmap->rxfreebufstart.next, BUF_PTR(rx_desc) | BUFF_STATUS_EMPTY);
  1511. for (buff_count = 0; buff_count < BUFN4_SIZE-1; buff_count++) {
  1512. wr_mem (dev, &rx_desc->next, BUF_PTR(rx_desc+1) | BUFF_STATUS_EMPTY);
  1513. rx_desc++;
  1514. }
  1515. wr_mem (dev, &rx_desc->next, BUF_PTR(&memmap->rxfreebufend) | BUFF_STATUS_EMPTY);
  1516. // Initialise the receive free buffer count
  1517. wr_regw (dev, RX_FREE_BUFFER_COUNT_OFF, BUFN4_SIZE);
  1518. // Initialize Horizons registers
  1519. // TX config
  1520. wr_regw (dev, TX_CONFIG_OFF,
  1521. ABR_ROUND_ROBIN | TX_NORMAL_OPERATION | DRVR_DRVRBAR_ENABLE);
  1522. // RX config. Use 10-x VC bits, x VP bits, non user cells in channel 0.
  1523. wr_regw (dev, RX_CONFIG_OFF,
  1524. DISCARD_UNUSED_VPI_VCI_BITS_SET | NON_USER_CELLS_IN_ONE_CHANNEL | vpi_bits);
  1525. // RX line config
  1526. wr_regw (dev, RX_LINE_CONFIG_OFF,
  1527. LOCK_DETECT_ENABLE | FREQUENCY_DETECT_ENABLE | GXTALOUT_SELECT_DIV4);
  1528. // Set the max AAL5 cell count to be just enough to contain the
  1529. // largest AAL5 frame that the user wants to receive
  1530. wr_regw (dev, MAX_AAL5_CELL_COUNT_OFF,
  1531. DIV_ROUND_UP(max_rx_size + ATM_AAL5_TRAILER, ATM_CELL_PAYLOAD));
  1532. // Enable receive
  1533. wr_regw (dev, RX_CONFIG_OFF, rd_regw (dev, RX_CONFIG_OFF) | RX_ENABLE);
  1534. printk (" control");
  1535. // Drive the OE of the LEDs then turn the green LED on
  1536. ctrl |= GREEN_LED_OE | YELLOW_LED_OE | GREEN_LED | YELLOW_LED;
  1537. wr_regl (dev, CONTROL_0_REG, ctrl);
  1538. // Test for a 155-capable card
  1539. if (onefivefive) {
  1540. // Select 155 mode... make this a choice (or: how do we detect
  1541. // external line speed and switch?)
  1542. ctrl |= ATM_LAYER_SELECT;
  1543. wr_regl (dev, CONTROL_0_REG, ctrl);
  1544. // test SUNI-lite vs SAMBA
  1545. // Register 0x00 in the SUNI will have some of bits 3-7 set, and
  1546. // they will always be zero for the SAMBA. Ha! Bloody hardware
  1547. // engineers. It'll never work.
  1548. if (rd_framer (dev, 0) & 0x00f0) {
  1549. // SUNI
  1550. printk (" SUNI");
  1551. // Reset, just in case
  1552. wr_framer (dev, 0x00, 0x0080);
  1553. wr_framer (dev, 0x00, 0x0000);
  1554. // Configure transmit FIFO
  1555. wr_framer (dev, 0x63, rd_framer (dev, 0x63) | 0x0002);
  1556. // Set line timed mode
  1557. wr_framer (dev, 0x05, rd_framer (dev, 0x05) | 0x0001);
  1558. } else {
  1559. // SAMBA
  1560. printk (" SAMBA");
  1561. // Reset, just in case
  1562. wr_framer (dev, 0, rd_framer (dev, 0) | 0x0001);
  1563. wr_framer (dev, 0, rd_framer (dev, 0) &~ 0x0001);
  1564. // Turn off diagnostic loopback and enable line-timed mode
  1565. wr_framer (dev, 0, 0x0002);
  1566. // Turn on transmit outputs
  1567. wr_framer (dev, 2, 0x0B80);
  1568. }
  1569. } else {
  1570. // Select 25 mode
  1571. ctrl &= ~ATM_LAYER_SELECT;
  1572. // Madge B154 setup
  1573. // none required?
  1574. }
  1575. printk (" LEDs");
  1576. GREEN_LED_ON(dev);
  1577. YELLOW_LED_ON(dev);
  1578. printk (" ESI=");
  1579. {
  1580. u16 b = 0;
  1581. int i;
  1582. u8 * esi = dev->atm_dev->esi;
  1583. // in the card I have, EEPROM
  1584. // addresses 0, 1, 2 contain 0
  1585. // addresess 5, 6 etc. contain ffff
  1586. // NB: Madge prefix is 00 00 f6 (which is 00 00 6f in Ethernet bit order)
  1587. // the read_bia routine gets the BIA in Ethernet bit order
  1588. for (i=0; i < ESI_LEN; ++i) {
  1589. if (i % 2 == 0)
  1590. b = read_bia (dev, i/2 + 2);
  1591. else
  1592. b = b >> 8;
  1593. esi[i] = b & 0xFF;
  1594. printk ("%02x", esi[i]);
  1595. }
  1596. }
  1597. // Enable RX_Q and ?X_COMPLETE interrupts only
  1598. wr_regl (dev, INT_ENABLE_REG_OFF, INTERESTING_INTERRUPTS);
  1599. printk (" IRQ on");
  1600. printk (".\n");
  1601. return onefivefive;
  1602. }
  1603. /********** check max_sdu **********/
  1604. static int check_max_sdu (hrz_aal aal, struct atm_trafprm * tp, unsigned int max_frame_size) {
  1605. PRINTD (DBG_FLOW|DBG_QOS, "check_max_sdu");
  1606. switch (aal) {
  1607. case aal0:
  1608. if (!(tp->max_sdu)) {
  1609. PRINTD (DBG_QOS, "defaulting max_sdu");
  1610. tp->max_sdu = ATM_AAL0_SDU;
  1611. } else if (tp->max_sdu != ATM_AAL0_SDU) {
  1612. PRINTD (DBG_QOS|DBG_ERR, "rejecting max_sdu");
  1613. return -EINVAL;
  1614. }
  1615. break;
  1616. case aal34:
  1617. if (tp->max_sdu == 0 || tp->max_sdu > ATM_MAX_AAL34_PDU) {
  1618. PRINTD (DBG_QOS, "%sing max_sdu", tp->max_sdu ? "capp" : "default");
  1619. tp->max_sdu = ATM_MAX_AAL34_PDU;
  1620. }
  1621. break;
  1622. case aal5:
  1623. if (tp->max_sdu == 0 || tp->max_sdu > max_frame_size) {
  1624. PRINTD (DBG_QOS, "%sing max_sdu", tp->max_sdu ? "capp" : "default");
  1625. tp->max_sdu = max_frame_size;
  1626. }
  1627. break;
  1628. }
  1629. return 0;
  1630. }
  1631. /********** check pcr **********/
  1632. // something like this should be part of ATM Linux
  1633. static int atm_pcr_check (struct atm_trafprm * tp, unsigned int pcr) {
  1634. // we are assuming non-UBR, and non-special values of pcr
  1635. if (tp->min_pcr == ATM_MAX_PCR)
  1636. PRINTD (DBG_QOS, "luser gave min_pcr = ATM_MAX_PCR");
  1637. else if (tp->min_pcr < 0)
  1638. PRINTD (DBG_QOS, "luser gave negative min_pcr");
  1639. else if (tp->min_pcr && tp->min_pcr > pcr)
  1640. PRINTD (DBG_QOS, "pcr less than min_pcr");
  1641. else
  1642. // !! max_pcr = UNSPEC (0) is equivalent to max_pcr = MAX (-1)
  1643. // easier to #define ATM_MAX_PCR 0 and have all rates unsigned?
  1644. // [this would get rid of next two conditionals]
  1645. if ((0) && tp->max_pcr == ATM_MAX_PCR)
  1646. PRINTD (DBG_QOS, "luser gave max_pcr = ATM_MAX_PCR");
  1647. else if ((tp->max_pcr != ATM_MAX_PCR) && tp->max_pcr < 0)
  1648. PRINTD (DBG_QOS, "luser gave negative max_pcr");
  1649. else if (tp->max_pcr && tp->max_pcr != ATM_MAX_PCR && tp->max_pcr < pcr)
  1650. PRINTD (DBG_QOS, "pcr greater than max_pcr");
  1651. else {
  1652. // each limit unspecified or not violated
  1653. PRINTD (DBG_QOS, "xBR(pcr) OK");
  1654. return 0;
  1655. }
  1656. PRINTD (DBG_QOS, "pcr=%u, tp: min_pcr=%d, pcr=%d, max_pcr=%d",
  1657. pcr, tp->min_pcr, tp->pcr, tp->max_pcr);
  1658. return -EINVAL;
  1659. }
  1660. /********** open VC **********/
  1661. static int hrz_open (struct atm_vcc *atm_vcc)
  1662. {
  1663. int error;
  1664. u16 channel;
  1665. struct atm_qos * qos;
  1666. struct atm_trafprm * txtp;
  1667. struct atm_trafprm * rxtp;
  1668. hrz_dev * dev = HRZ_DEV(atm_vcc->dev);
  1669. hrz_vcc vcc;
  1670. hrz_vcc * vccp; // allocated late
  1671. short vpi = atm_vcc->vpi;
  1672. int vci = atm_vcc->vci;
  1673. PRINTD (DBG_FLOW|DBG_VCC, "hrz_open %x %x", vpi, vci);
  1674. #ifdef ATM_VPI_UNSPEC
  1675. // UNSPEC is deprecated, remove this code eventually
  1676. if (vpi == ATM_VPI_UNSPEC || vci == ATM_VCI_UNSPEC) {
  1677. PRINTK (KERN_WARNING, "rejecting open with unspecified VPI/VCI (deprecated)");
  1678. return -EINVAL;
  1679. }
  1680. #endif
  1681. error = vpivci_to_channel (&channel, vpi, vci);
  1682. if (error) {
  1683. PRINTD (DBG_WARN|DBG_VCC, "VPI/VCI out of range: %hd/%d", vpi, vci);
  1684. return error;
  1685. }
  1686. vcc.channel = channel;
  1687. // max speed for the moment
  1688. vcc.tx_rate = 0x0;
  1689. qos = &atm_vcc->qos;
  1690. // check AAL and remember it
  1691. switch (qos->aal) {
  1692. case ATM_AAL0:
  1693. // we would if it were 48 bytes and not 52!
  1694. PRINTD (DBG_QOS|DBG_VCC, "AAL0");
  1695. vcc.aal = aal0;
  1696. break;
  1697. case ATM_AAL34:
  1698. // we would if I knew how do the SAR!
  1699. PRINTD (DBG_QOS|DBG_VCC, "AAL3/4");
  1700. vcc.aal = aal34;
  1701. break;
  1702. case ATM_AAL5:
  1703. PRINTD (DBG_QOS|DBG_VCC, "AAL5");
  1704. vcc.aal = aal5;
  1705. break;
  1706. default:
  1707. PRINTD (DBG_QOS|DBG_VCC, "Bad AAL!");
  1708. return -EINVAL;
  1709. }
  1710. // TX traffic parameters
  1711. // there are two, interrelated problems here: 1. the reservation of
  1712. // PCR is not a binary choice, we are given bounds and/or a
  1713. // desirable value; 2. the device is only capable of certain values,
  1714. // most of which are not integers. It is almost certainly acceptable
  1715. // to be off by a maximum of 1 to 10 cps.
  1716. // Pragmatic choice: always store an integral PCR as that which has
  1717. // been allocated, even if we allocate a little (or a lot) less,
  1718. // after rounding. The actual allocation depends on what we can
  1719. // manage with our rate selection algorithm. The rate selection
  1720. // algorithm is given an integral PCR and a tolerance and told
  1721. // whether it should round the value up or down if the tolerance is
  1722. // exceeded; it returns: a) the actual rate selected (rounded up to
  1723. // the nearest integer), b) a bit pattern to feed to the timer
  1724. // register, and c) a failure value if no applicable rate exists.
  1725. // Part of the job is done by atm_pcr_goal which gives us a PCR
  1726. // specification which says: EITHER grab the maximum available PCR
  1727. // (and perhaps a lower bound which we musn't pass), OR grab this
  1728. // amount, rounding down if you have to (and perhaps a lower bound
  1729. // which we musn't pass) OR grab this amount, rounding up if you
  1730. // have to (and perhaps an upper bound which we musn't pass). If any
  1731. // bounds ARE passed we fail. Note that rounding is only rounding to
  1732. // match device limitations, we do not round down to satisfy
  1733. // bandwidth availability even if this would not violate any given
  1734. // lower bound.
  1735. // Note: telephony = 64kb/s = 48 byte cell payload @ 500/3 cells/s
  1736. // (say) so this is not even a binary fixpoint cell rate (but this
  1737. // device can do it). To avoid this sort of hassle we use a
  1738. // tolerance parameter (currently fixed at 10 cps).
  1739. PRINTD (DBG_QOS, "TX:");
  1740. txtp = &qos->txtp;
  1741. // set up defaults for no traffic
  1742. vcc.tx_rate = 0;
  1743. // who knows what would actually happen if you try and send on this?
  1744. vcc.tx_xbr_bits = IDLE_RATE_TYPE;
  1745. vcc.tx_pcr_bits = CLOCK_DISABLE;
  1746. #if 0
  1747. vcc.tx_scr_bits = CLOCK_DISABLE;
  1748. vcc.tx_bucket_bits = 0;
  1749. #endif
  1750. if (txtp->traffic_class != ATM_NONE) {
  1751. error = check_max_sdu (vcc.aal, txtp, max_tx_size);
  1752. if (error) {
  1753. PRINTD (DBG_QOS, "TX max_sdu check failed");
  1754. return error;
  1755. }
  1756. switch (txtp->traffic_class) {
  1757. case ATM_UBR: {
  1758. // we take "the PCR" as a rate-cap
  1759. // not reserved
  1760. vcc.tx_rate = 0;
  1761. make_rate (dev, 1<<30, round_nearest, &vcc.tx_pcr_bits, NULL);
  1762. vcc.tx_xbr_bits = ABR_RATE_TYPE;
  1763. break;
  1764. }
  1765. #if 0
  1766. case ATM_ABR: {
  1767. // reserve min, allow up to max
  1768. vcc.tx_rate = 0; // ?
  1769. make_rate (dev, 1<<30, round_nearest, &vcc.tx_pcr_bits, 0);
  1770. vcc.tx_xbr_bits = ABR_RATE_TYPE;
  1771. break;
  1772. }
  1773. #endif
  1774. case ATM_CBR: {
  1775. int pcr = atm_pcr_goal (txtp);
  1776. rounding r;
  1777. if (!pcr) {
  1778. // down vs. up, remaining bandwidth vs. unlimited bandwidth!!
  1779. // should really have: once someone gets unlimited bandwidth
  1780. // that no more non-UBR channels can be opened until the
  1781. // unlimited one closes?? For the moment, round_down means
  1782. // greedy people actually get something and not nothing
  1783. r = round_down;
  1784. // slight race (no locking) here so we may get -EAGAIN
  1785. // later; the greedy bastards would deserve it :)
  1786. PRINTD (DBG_QOS, "snatching all remaining TX bandwidth");
  1787. pcr = dev->tx_avail;
  1788. } else if (pcr < 0) {
  1789. r = round_down;
  1790. pcr = -pcr;
  1791. } else {
  1792. r = round_up;
  1793. }
  1794. error = make_rate_with_tolerance (dev, pcr, r, 10,
  1795. &vcc.tx_pcr_bits, &vcc.tx_rate);
  1796. if (error) {
  1797. PRINTD (DBG_QOS, "could not make rate from TX PCR");
  1798. return error;
  1799. }
  1800. // not really clear what further checking is needed
  1801. error = atm_pcr_check (txtp, vcc.tx_rate);
  1802. if (error) {
  1803. PRINTD (DBG_QOS, "TX PCR failed consistency check");
  1804. return error;
  1805. }
  1806. vcc.tx_xbr_bits = CBR_RATE_TYPE;
  1807. break;
  1808. }
  1809. #if 0
  1810. case ATM_VBR: {
  1811. int pcr = atm_pcr_goal (txtp);
  1812. // int scr = atm_scr_goal (txtp);
  1813. int scr = pcr/2; // just for fun
  1814. unsigned int mbs = 60; // just for fun
  1815. rounding pr;
  1816. rounding sr;
  1817. unsigned int bucket;
  1818. if (!pcr) {
  1819. pr = round_nearest;
  1820. pcr = 1<<30;
  1821. } else if (pcr < 0) {
  1822. pr = round_down;
  1823. pcr = -pcr;
  1824. } else {
  1825. pr = round_up;
  1826. }
  1827. error = make_rate_with_tolerance (dev, pcr, pr, 10,
  1828. &vcc.tx_pcr_bits, 0);
  1829. if (!scr) {
  1830. // see comments for PCR with CBR above
  1831. sr = round_down;
  1832. // slight race (no locking) here so we may get -EAGAIN
  1833. // later; the greedy bastards would deserve it :)
  1834. PRINTD (DBG_QOS, "snatching all remaining TX bandwidth");
  1835. scr = dev->tx_avail;
  1836. } else if (scr < 0) {
  1837. sr = round_down;
  1838. scr = -scr;
  1839. } else {
  1840. sr = round_up;
  1841. }
  1842. error = make_rate_with_tolerance (dev, scr, sr, 10,
  1843. &vcc.tx_scr_bits, &vcc.tx_rate);
  1844. if (error) {
  1845. PRINTD (DBG_QOS, "could not make rate from TX SCR");
  1846. return error;
  1847. }
  1848. // not really clear what further checking is needed
  1849. // error = atm_scr_check (txtp, vcc.tx_rate);
  1850. if (error) {
  1851. PRINTD (DBG_QOS, "TX SCR failed consistency check");
  1852. return error;
  1853. }
  1854. // bucket calculations (from a piece of paper...) cell bucket
  1855. // capacity must be largest integer smaller than m(p-s)/p + 1
  1856. // where m = max burst size, p = pcr, s = scr
  1857. bucket = mbs*(pcr-scr)/pcr;
  1858. if (bucket*pcr != mbs*(pcr-scr))
  1859. bucket += 1;
  1860. if (bucket > BUCKET_MAX_SIZE) {
  1861. PRINTD (DBG_QOS, "shrinking bucket from %u to %u",
  1862. bucket, BUCKET_MAX_SIZE);
  1863. bucket = BUCKET_MAX_SIZE;
  1864. }
  1865. vcc.tx_xbr_bits = VBR_RATE_TYPE;
  1866. vcc.tx_bucket_bits = bucket;
  1867. break;
  1868. }
  1869. #endif
  1870. default: {
  1871. PRINTD (DBG_QOS, "unsupported TX traffic class");
  1872. return -EINVAL;
  1873. }
  1874. }
  1875. }
  1876. // RX traffic parameters
  1877. PRINTD (DBG_QOS, "RX:");
  1878. rxtp = &qos->rxtp;
  1879. // set up defaults for no traffic
  1880. vcc.rx_rate = 0;
  1881. if (rxtp->traffic_class != ATM_NONE) {
  1882. error = check_max_sdu (vcc.aal, rxtp, max_rx_size);
  1883. if (error) {
  1884. PRINTD (DBG_QOS, "RX max_sdu check failed");
  1885. return error;
  1886. }
  1887. switch (rxtp->traffic_class) {
  1888. case ATM_UBR: {
  1889. // not reserved
  1890. break;
  1891. }
  1892. #if 0
  1893. case ATM_ABR: {
  1894. // reserve min
  1895. vcc.rx_rate = 0; // ?
  1896. break;
  1897. }
  1898. #endif
  1899. case ATM_CBR: {
  1900. int pcr = atm_pcr_goal (rxtp);
  1901. if (!pcr) {
  1902. // slight race (no locking) here so we may get -EAGAIN
  1903. // later; the greedy bastards would deserve it :)
  1904. PRINTD (DBG_QOS, "snatching all remaining RX bandwidth");
  1905. pcr = dev->rx_avail;
  1906. } else if (pcr < 0) {
  1907. pcr = -pcr;
  1908. }
  1909. vcc.rx_rate = pcr;
  1910. // not really clear what further checking is needed
  1911. error = atm_pcr_check (rxtp, vcc.rx_rate);
  1912. if (error) {
  1913. PRINTD (DBG_QOS, "RX PCR failed consistency check");
  1914. return error;
  1915. }
  1916. break;
  1917. }
  1918. #if 0
  1919. case ATM_VBR: {
  1920. // int scr = atm_scr_goal (rxtp);
  1921. int scr = 1<<16; // just for fun
  1922. if (!scr) {
  1923. // slight race (no locking) here so we may get -EAGAIN
  1924. // later; the greedy bastards would deserve it :)
  1925. PRINTD (DBG_QOS, "snatching all remaining RX bandwidth");
  1926. scr = dev->rx_avail;
  1927. } else if (scr < 0) {
  1928. scr = -scr;
  1929. }
  1930. vcc.rx_rate = scr;
  1931. // not really clear what further checking is needed
  1932. // error = atm_scr_check (rxtp, vcc.rx_rate);
  1933. if (error) {
  1934. PRINTD (DBG_QOS, "RX SCR failed consistency check");
  1935. return error;
  1936. }
  1937. break;
  1938. }
  1939. #endif
  1940. default: {
  1941. PRINTD (DBG_QOS, "unsupported RX traffic class");
  1942. return -EINVAL;
  1943. }
  1944. }
  1945. }
  1946. // late abort useful for diagnostics
  1947. if (vcc.aal != aal5) {
  1948. PRINTD (DBG_QOS, "AAL not supported");
  1949. return -EINVAL;
  1950. }
  1951. // get space for our vcc stuff and copy parameters into it
  1952. vccp = kmalloc (sizeof(hrz_vcc), GFP_KERNEL);
  1953. if (!vccp) {
  1954. PRINTK (KERN_ERR, "out of memory!");
  1955. return -ENOMEM;
  1956. }
  1957. *vccp = vcc;
  1958. // clear error and grab cell rate resource lock
  1959. error = 0;
  1960. spin_lock (&dev->rate_lock);
  1961. if (vcc.tx_rate > dev->tx_avail) {
  1962. PRINTD (DBG_QOS, "not enough TX PCR left");
  1963. error = -EAGAIN;
  1964. }
  1965. if (vcc.rx_rate > dev->rx_avail) {
  1966. PRINTD (DBG_QOS, "not enough RX PCR left");
  1967. error = -EAGAIN;
  1968. }
  1969. if (!error) {
  1970. // really consume cell rates
  1971. dev->tx_avail -= vcc.tx_rate;
  1972. dev->rx_avail -= vcc.rx_rate;
  1973. PRINTD (DBG_QOS|DBG_VCC, "reserving %u TX PCR and %u RX PCR",
  1974. vcc.tx_rate, vcc.rx_rate);
  1975. }
  1976. // release lock and exit on error
  1977. spin_unlock (&dev->rate_lock);
  1978. if (error) {
  1979. PRINTD (DBG_QOS|DBG_VCC, "insufficient cell rate resources");
  1980. kfree (vccp);
  1981. return error;
  1982. }
  1983. // this is "immediately before allocating the connection identifier
  1984. // in hardware" - so long as the next call does not fail :)
  1985. set_bit(ATM_VF_ADDR,&atm_vcc->flags);
  1986. // any errors here are very serious and should never occur
  1987. if (rxtp->traffic_class != ATM_NONE) {
  1988. if (dev->rxer[channel]) {
  1989. PRINTD (DBG_ERR|DBG_VCC, "VC already open for RX");
  1990. error = -EBUSY;
  1991. }
  1992. if (!error)
  1993. error = hrz_open_rx (dev, channel);
  1994. if (error) {
  1995. kfree (vccp);
  1996. return error;
  1997. }
  1998. // this link allows RX frames through
  1999. dev->rxer[channel] = atm_vcc;
  2000. }
  2001. // success, set elements of atm_vcc
  2002. atm_vcc->dev_data = (void *) vccp;
  2003. // indicate readiness
  2004. set_bit(ATM_VF_READY,&atm_vcc->flags);
  2005. return 0;
  2006. }
  2007. /********** close VC **********/
  2008. static void hrz_close (struct atm_vcc * atm_vcc) {
  2009. hrz_dev * dev = HRZ_DEV(atm_vcc->dev);
  2010. hrz_vcc * vcc = HRZ_VCC(atm_vcc);
  2011. u16 channel = vcc->channel;
  2012. PRINTD (DBG_VCC|DBG_FLOW, "hrz_close");
  2013. // indicate unreadiness
  2014. clear_bit(ATM_VF_READY,&atm_vcc->flags);
  2015. if (atm_vcc->qos.txtp.traffic_class != ATM_NONE) {
  2016. unsigned int i;
  2017. // let any TX on this channel that has started complete
  2018. // no restart, just keep trying
  2019. while (tx_hold (dev))
  2020. ;
  2021. // remove record of any tx_channel having been setup for this channel
  2022. for (i = 0; i < TX_CHANS; ++i)
  2023. if (dev->tx_channel_record[i] == channel) {
  2024. dev->tx_channel_record[i] = -1;
  2025. break;
  2026. }
  2027. if (dev->last_vc == channel)
  2028. dev->tx_last = -1;
  2029. tx_release (dev);
  2030. }
  2031. if (atm_vcc->qos.rxtp.traffic_class != ATM_NONE) {
  2032. // disable RXing - it tries quite hard
  2033. hrz_close_rx (dev, channel);
  2034. // forget the vcc - no more skbs will be pushed
  2035. if (atm_vcc != dev->rxer[channel])
  2036. PRINTK (KERN_ERR, "%s atm_vcc=%p rxer[channel]=%p",
  2037. "arghhh! we're going to die!",
  2038. atm_vcc, dev->rxer[channel]);
  2039. dev->rxer[channel] = NULL;
  2040. }
  2041. // atomically release our rate reservation
  2042. spin_lock (&dev->rate_lock);
  2043. PRINTD (DBG_QOS|DBG_VCC, "releasing %u TX PCR and %u RX PCR",
  2044. vcc->tx_rate, vcc->rx_rate);
  2045. dev->tx_avail += vcc->tx_rate;
  2046. dev->rx_avail += vcc->rx_rate;
  2047. spin_unlock (&dev->rate_lock);
  2048. // free our structure
  2049. kfree (vcc);
  2050. // say the VPI/VCI is free again
  2051. clear_bit(ATM_VF_ADDR,&atm_vcc->flags);
  2052. }
  2053. #if 0
  2054. static int hrz_ioctl (struct atm_dev * atm_dev, unsigned int cmd, void *arg) {
  2055. hrz_dev * dev = HRZ_DEV(atm_dev);
  2056. PRINTD (DBG_FLOW, "hrz_ioctl");
  2057. return -1;
  2058. }
  2059. unsigned char hrz_phy_get (struct atm_dev * atm_dev, unsigned long addr) {
  2060. hrz_dev * dev = HRZ_DEV(atm_dev);
  2061. PRINTD (DBG_FLOW, "hrz_phy_get");
  2062. return 0;
  2063. }
  2064. static void hrz_phy_put (struct atm_dev * atm_dev, unsigned char value,
  2065. unsigned long addr) {
  2066. hrz_dev * dev = HRZ_DEV(atm_dev);
  2067. PRINTD (DBG_FLOW, "hrz_phy_put");
  2068. }
  2069. static int hrz_change_qos (struct atm_vcc * atm_vcc, struct atm_qos *qos, int flgs) {
  2070. hrz_dev * dev = HRZ_DEV(vcc->dev);
  2071. PRINTD (DBG_FLOW, "hrz_change_qos");
  2072. return -1;
  2073. }
  2074. #endif
  2075. /********** proc file contents **********/
  2076. static int hrz_proc_read (struct atm_dev * atm_dev, loff_t * pos, char * page) {
  2077. hrz_dev * dev = HRZ_DEV(atm_dev);
  2078. int left = *pos;
  2079. PRINTD (DBG_FLOW, "hrz_proc_read");
  2080. /* more diagnostics here? */
  2081. #if 0
  2082. if (!left--) {
  2083. unsigned int count = sprintf (page, "vbr buckets:");
  2084. unsigned int i;
  2085. for (i = 0; i < TX_CHANS; ++i)
  2086. count += sprintf (page, " %u/%u",
  2087. query_tx_channel_config (dev, i, BUCKET_FULLNESS_ACCESS),
  2088. query_tx_channel_config (dev, i, BUCKET_CAPACITY_ACCESS));
  2089. count += sprintf (page+count, ".\n");
  2090. return count;
  2091. }
  2092. #endif
  2093. if (!left--)
  2094. return sprintf (page,
  2095. "cells: TX %lu, RX %lu, HEC errors %lu, unassigned %lu.\n",
  2096. dev->tx_cell_count, dev->rx_cell_count,
  2097. dev->hec_error_count, dev->unassigned_cell_count);
  2098. if (!left--)
  2099. return sprintf (page,
  2100. "free cell buffers: TX %hu, RX %hu+%hu.\n",
  2101. rd_regw (dev, TX_FREE_BUFFER_COUNT_OFF),
  2102. rd_regw (dev, RX_FREE_BUFFER_COUNT_OFF),
  2103. dev->noof_spare_buffers);
  2104. if (!left--)
  2105. return sprintf (page,
  2106. "cps remaining: TX %u, RX %u\n",
  2107. dev->tx_avail, dev->rx_avail);
  2108. return 0;
  2109. }
  2110. static const struct atmdev_ops hrz_ops = {
  2111. .open = hrz_open,
  2112. .close = hrz_close,
  2113. .send = hrz_send,
  2114. .proc_read = hrz_proc_read,
  2115. .owner = THIS_MODULE,
  2116. };
  2117. static int hrz_probe(struct pci_dev *pci_dev,
  2118. const struct pci_device_id *pci_ent)
  2119. {
  2120. hrz_dev * dev;
  2121. int err = 0;
  2122. // adapter slot free, read resources from PCI configuration space
  2123. u32 iobase = pci_resource_start (pci_dev, 0);
  2124. u32 * membase = bus_to_virt (pci_resource_start (pci_dev, 1));
  2125. unsigned int irq;
  2126. unsigned char lat;
  2127. PRINTD (DBG_FLOW, "hrz_probe");
  2128. if (pci_enable_device(pci_dev))
  2129. return -EINVAL;
  2130. /* XXX DEV_LABEL is a guess */
  2131. if (!request_region(iobase, HRZ_IO_EXTENT, DEV_LABEL)) {
  2132. err = -EINVAL;
  2133. goto out_disable;
  2134. }
  2135. dev = kzalloc(sizeof(hrz_dev), GFP_KERNEL);
  2136. if (!dev) {
  2137. // perhaps we should be nice: deregister all adapters and abort?
  2138. PRINTD(DBG_ERR, "out of memory");
  2139. err = -ENOMEM;
  2140. goto out_release;
  2141. }
  2142. pci_set_drvdata(pci_dev, dev);
  2143. // grab IRQ and install handler - move this someplace more sensible
  2144. irq = pci_dev->irq;
  2145. if (request_irq(irq,
  2146. interrupt_handler,
  2147. IRQF_SHARED, /* irqflags guess */
  2148. DEV_LABEL, /* name guess */
  2149. dev)) {
  2150. PRINTD(DBG_WARN, "request IRQ failed!");
  2151. err = -EINVAL;
  2152. goto out_free;
  2153. }
  2154. PRINTD(DBG_INFO, "found Madge ATM adapter (hrz) at: IO %x, IRQ %u, MEM %p",
  2155. iobase, irq, membase);
  2156. dev->atm_dev = atm_dev_register(DEV_LABEL, &pci_dev->dev, &hrz_ops, -1,
  2157. NULL);
  2158. if (!(dev->atm_dev)) {
  2159. PRINTD(DBG_ERR, "failed to register Madge ATM adapter");
  2160. err = -EINVAL;
  2161. goto out_free_irq;
  2162. }
  2163. PRINTD(DBG_INFO, "registered Madge ATM adapter (no. %d) (%p) at %p",
  2164. dev->atm_dev->number, dev, dev->atm_dev);
  2165. dev->atm_dev->dev_data = (void *) dev;
  2166. dev->pci_dev = pci_dev;
  2167. // enable bus master accesses
  2168. pci_set_master(pci_dev);
  2169. // frobnicate latency (upwards, usually)
  2170. pci_read_config_byte(pci_dev, PCI_LATENCY_TIMER, &lat);
  2171. if (pci_lat) {
  2172. PRINTD(DBG_INFO, "%s PCI latency timer from %hu to %hu",
  2173. "changing", lat, pci_lat);
  2174. pci_write_config_byte(pci_dev, PCI_LATENCY_TIMER, pci_lat);
  2175. } else if (lat < MIN_PCI_LATENCY) {
  2176. PRINTK(KERN_INFO, "%s PCI latency timer from %hu to %hu",
  2177. "increasing", lat, MIN_PCI_LATENCY);
  2178. pci_write_config_byte(pci_dev, PCI_LATENCY_TIMER, MIN_PCI_LATENCY);
  2179. }
  2180. dev->iobase = iobase;
  2181. dev->irq = irq;
  2182. dev->membase = membase;
  2183. dev->rx_q_entry = dev->rx_q_reset = &memmap->rx_q_entries[0];
  2184. dev->rx_q_wrap = &memmap->rx_q_entries[RX_CHANS-1];
  2185. // these next three are performance hacks
  2186. dev->last_vc = -1;
  2187. dev->tx_last = -1;
  2188. dev->tx_idle = 0;
  2189. dev->tx_regions = 0;
  2190. dev->tx_bytes = 0;
  2191. dev->tx_skb = NULL;
  2192. dev->tx_iovec = NULL;
  2193. dev->tx_cell_count = 0;
  2194. dev->rx_cell_count = 0;
  2195. dev->hec_error_count = 0;
  2196. dev->unassigned_cell_count = 0;
  2197. dev->noof_spare_buffers = 0;
  2198. {
  2199. unsigned int i;
  2200. for (i = 0; i < TX_CHANS; ++i)
  2201. dev->tx_channel_record[i] = -1;
  2202. }
  2203. dev->flags = 0;
  2204. // Allocate cell rates and remember ASIC version
  2205. // Fibre: ATM_OC3_PCR = 1555200000/8/270*260/53 - 29/53
  2206. // Copper: (WRONG) we want 6 into the above, close to 25Mb/s
  2207. // Copper: (plagarise!) 25600000/8/270*260/53 - n/53
  2208. if (hrz_init(dev)) {
  2209. // to be really pedantic, this should be ATM_OC3c_PCR
  2210. dev->tx_avail = ATM_OC3_PCR;
  2211. dev->rx_avail = ATM_OC3_PCR;
  2212. set_bit(ultra, &dev->flags); // NOT "|= ultra" !
  2213. } else {
  2214. dev->tx_avail = ((25600000/8)*26)/(27*53);
  2215. dev->rx_avail = ((25600000/8)*26)/(27*53);
  2216. PRINTD(DBG_WARN, "Buggy ASIC: no TX bus-mastering.");
  2217. }
  2218. // rate changes spinlock
  2219. spin_lock_init(&dev->rate_lock);
  2220. // on-board memory access spinlock; we want atomic reads and
  2221. // writes to adapter memory (handles IRQ and SMP)
  2222. spin_lock_init(&dev->mem_lock);
  2223. init_waitqueue_head(&dev->tx_queue);
  2224. // vpi in 0..4, vci in 6..10
  2225. dev->atm_dev->ci_range.vpi_bits = vpi_bits;
  2226. dev->atm_dev->ci_range.vci_bits = 10-vpi_bits;
  2227. timer_setup(&dev->housekeeping, do_housekeeping, 0);
  2228. mod_timer(&dev->housekeeping, jiffies);
  2229. out:
  2230. return err;
  2231. out_free_irq:
  2232. free_irq(irq, dev);
  2233. out_free:
  2234. kfree(dev);
  2235. out_release:
  2236. release_region(iobase, HRZ_IO_EXTENT);
  2237. out_disable:
  2238. pci_disable_device(pci_dev);
  2239. goto out;
  2240. }
  2241. static void hrz_remove_one(struct pci_dev *pci_dev)
  2242. {
  2243. hrz_dev *dev;
  2244. dev = pci_get_drvdata(pci_dev);
  2245. PRINTD(DBG_INFO, "closing %p (atm_dev = %p)", dev, dev->atm_dev);
  2246. del_timer_sync(&dev->housekeeping);
  2247. hrz_reset(dev);
  2248. atm_dev_deregister(dev->atm_dev);
  2249. free_irq(dev->irq, dev);
  2250. release_region(dev->iobase, HRZ_IO_EXTENT);
  2251. kfree(dev);
  2252. pci_disable_device(pci_dev);
  2253. }
  2254. static void __init hrz_check_args (void) {
  2255. #ifdef DEBUG_HORIZON
  2256. PRINTK (KERN_NOTICE, "debug bitmap is %hx", debug &= DBG_MASK);
  2257. #else
  2258. if (debug)
  2259. PRINTK (KERN_NOTICE, "no debug support in this image");
  2260. #endif
  2261. if (vpi_bits > HRZ_MAX_VPI)
  2262. PRINTK (KERN_ERR, "vpi_bits has been limited to %hu",
  2263. vpi_bits = HRZ_MAX_VPI);
  2264. if (max_tx_size < 0 || max_tx_size > TX_AAL5_LIMIT)
  2265. PRINTK (KERN_NOTICE, "max_tx_size has been limited to %hu",
  2266. max_tx_size = TX_AAL5_LIMIT);
  2267. if (max_rx_size < 0 || max_rx_size > RX_AAL5_LIMIT)
  2268. PRINTK (KERN_NOTICE, "max_rx_size has been limited to %hu",
  2269. max_rx_size = RX_AAL5_LIMIT);
  2270. return;
  2271. }
  2272. MODULE_AUTHOR(maintainer_string);
  2273. MODULE_DESCRIPTION(description_string);
  2274. MODULE_LICENSE("GPL");
  2275. module_param(debug, ushort, 0644);
  2276. module_param(vpi_bits, ushort, 0);
  2277. module_param(max_tx_size, int, 0);
  2278. module_param(max_rx_size, int, 0);
  2279. module_param(pci_lat, byte, 0);
  2280. MODULE_PARM_DESC(debug, "debug bitmap, see .h file");
  2281. MODULE_PARM_DESC(vpi_bits, "number of bits (0..4) to allocate to VPIs");
  2282. MODULE_PARM_DESC(max_tx_size, "maximum size of TX AAL5 frames");
  2283. MODULE_PARM_DESC(max_rx_size, "maximum size of RX AAL5 frames");
  2284. MODULE_PARM_DESC(pci_lat, "PCI latency in bus cycles");
  2285. static const struct pci_device_id hrz_pci_tbl[] = {
  2286. { PCI_VENDOR_ID_MADGE, PCI_DEVICE_ID_MADGE_HORIZON, PCI_ANY_ID, PCI_ANY_ID,
  2287. 0, 0, 0 },
  2288. { 0, }
  2289. };
  2290. MODULE_DEVICE_TABLE(pci, hrz_pci_tbl);
  2291. static struct pci_driver hrz_driver = {
  2292. .name = "horizon",
  2293. .probe = hrz_probe,
  2294. .remove = hrz_remove_one,
  2295. .id_table = hrz_pci_tbl,
  2296. };
  2297. /********** module entry **********/
  2298. static int __init hrz_module_init (void) {
  2299. BUILD_BUG_ON(sizeof(struct MEMMAP) != 128*1024/4);
  2300. show_version();
  2301. // check arguments
  2302. hrz_check_args();
  2303. // get the juice
  2304. return pci_register_driver(&hrz_driver);
  2305. }
  2306. /********** module exit **********/
  2307. static void __exit hrz_module_exit (void) {
  2308. PRINTD (DBG_FLOW, "cleanup_module");
  2309. pci_unregister_driver(&hrz_driver);
  2310. }
  2311. module_init(hrz_module_init);
  2312. module_exit(hrz_module_exit);