fore200e.h 38 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. #ifndef _FORE200E_H
  3. #define _FORE200E_H
  4. #ifdef __KERNEL__
  5. /* rx buffer sizes */
  6. #define SMALL_BUFFER_SIZE 384 /* size of small buffers (multiple of 48 (PCA) and 64 (SBA) bytes) */
  7. #define LARGE_BUFFER_SIZE 4032 /* size of large buffers (multiple of 48 (PCA) and 64 (SBA) bytes) */
  8. #define RBD_BLK_SIZE 32 /* nbr of supplied rx buffers per rbd */
  9. #define MAX_PDU_SIZE 65535 /* maximum PDU size supported by AALs */
  10. #define BUFFER_S1_SIZE SMALL_BUFFER_SIZE /* size of small buffers, scheme 1 */
  11. #define BUFFER_L1_SIZE LARGE_BUFFER_SIZE /* size of large buffers, scheme 1 */
  12. #define BUFFER_S2_SIZE SMALL_BUFFER_SIZE /* size of small buffers, scheme 2 */
  13. #define BUFFER_L2_SIZE LARGE_BUFFER_SIZE /* size of large buffers, scheme 2 */
  14. #define BUFFER_S1_NBR (RBD_BLK_SIZE * 6)
  15. #define BUFFER_L1_NBR (RBD_BLK_SIZE * 4)
  16. #define BUFFER_S2_NBR (RBD_BLK_SIZE * 6)
  17. #define BUFFER_L2_NBR (RBD_BLK_SIZE * 4)
  18. #define QUEUE_SIZE_CMD 16 /* command queue capacity */
  19. #define QUEUE_SIZE_RX 64 /* receive queue capacity */
  20. #define QUEUE_SIZE_TX 256 /* transmit queue capacity */
  21. #define QUEUE_SIZE_BS 32 /* buffer supply queue capacity */
  22. #define FORE200E_VPI_BITS 0
  23. #define FORE200E_VCI_BITS 10
  24. #define NBR_CONNECT (1 << (FORE200E_VPI_BITS + FORE200E_VCI_BITS)) /* number of connections */
  25. #define TSD_FIXED 2
  26. #define TSD_EXTENSION 0
  27. #define TSD_NBR (TSD_FIXED + TSD_EXTENSION)
  28. /* the cp starts putting a received PDU into one *small* buffer,
  29. then it uses a number of *large* buffers for the trailing data.
  30. we compute here the total number of receive segment descriptors
  31. required to hold the largest possible PDU */
  32. #define RSD_REQUIRED (((MAX_PDU_SIZE - SMALL_BUFFER_SIZE + LARGE_BUFFER_SIZE) / LARGE_BUFFER_SIZE) + 1)
  33. #define RSD_FIXED 3
  34. /* RSD_REQUIRED receive segment descriptors are enough to describe a max-sized PDU,
  35. but we have to keep the size of the receive PDU descriptor multiple of 32 bytes,
  36. so we add one extra RSD to RSD_EXTENSION
  37. (WARNING: THIS MAY CHANGE IF BUFFER SIZES ARE MODIFIED) */
  38. #define RSD_EXTENSION ((RSD_REQUIRED - RSD_FIXED) + 1)
  39. #define RSD_NBR (RSD_FIXED + RSD_EXTENSION)
  40. #define FORE200E_DEV(d) ((struct fore200e*)((d)->dev_data))
  41. #define FORE200E_VCC(d) ((struct fore200e_vcc*)((d)->dev_data))
  42. /* bitfields endian games */
  43. #if defined(__LITTLE_ENDIAN_BITFIELD)
  44. #define BITFIELD2(b1, b2) b1; b2;
  45. #define BITFIELD3(b1, b2, b3) b1; b2; b3;
  46. #define BITFIELD4(b1, b2, b3, b4) b1; b2; b3; b4;
  47. #define BITFIELD5(b1, b2, b3, b4, b5) b1; b2; b3; b4; b5;
  48. #define BITFIELD6(b1, b2, b3, b4, b5, b6) b1; b2; b3; b4; b5; b6;
  49. #elif defined(__BIG_ENDIAN_BITFIELD)
  50. #define BITFIELD2(b1, b2) b2; b1;
  51. #define BITFIELD3(b1, b2, b3) b3; b2; b1;
  52. #define BITFIELD4(b1, b2, b3, b4) b4; b3; b2; b1;
  53. #define BITFIELD5(b1, b2, b3, b4, b5) b5; b4; b3; b2; b1;
  54. #define BITFIELD6(b1, b2, b3, b4, b5, b6) b6; b5; b4; b3; b2; b1;
  55. #else
  56. #error unknown bitfield endianess
  57. #endif
  58. /* ATM cell header (minus HEC byte) */
  59. typedef struct atm_header {
  60. BITFIELD5(
  61. u32 clp : 1, /* cell loss priority */
  62. u32 plt : 3, /* payload type */
  63. u32 vci : 16, /* virtual channel identifier */
  64. u32 vpi : 8, /* virtual path identifier */
  65. u32 gfc : 4 /* generic flow control */
  66. )
  67. } atm_header_t;
  68. /* ATM adaptation layer id */
  69. typedef enum fore200e_aal {
  70. FORE200E_AAL0 = 0,
  71. FORE200E_AAL34 = 4,
  72. FORE200E_AAL5 = 5,
  73. } fore200e_aal_t;
  74. /* transmit PDU descriptor specification */
  75. typedef struct tpd_spec {
  76. BITFIELD4(
  77. u32 length : 16, /* total PDU length */
  78. u32 nseg : 8, /* number of transmit segments */
  79. enum fore200e_aal aal : 4, /* adaptation layer */
  80. u32 intr : 4 /* interrupt requested */
  81. )
  82. } tpd_spec_t;
  83. /* transmit PDU rate control */
  84. typedef struct tpd_rate
  85. {
  86. BITFIELD2(
  87. u32 idle_cells : 16, /* number of idle cells to insert */
  88. u32 data_cells : 16 /* number of data cells to transmit */
  89. )
  90. } tpd_rate_t;
  91. /* transmit segment descriptor */
  92. typedef struct tsd {
  93. u32 buffer; /* transmit buffer DMA address */
  94. u32 length; /* number of bytes in buffer */
  95. } tsd_t;
  96. /* transmit PDU descriptor */
  97. typedef struct tpd {
  98. struct atm_header atm_header; /* ATM header minus HEC byte */
  99. struct tpd_spec spec; /* tpd specification */
  100. struct tpd_rate rate; /* tpd rate control */
  101. u32 pad; /* reserved */
  102. struct tsd tsd[ TSD_NBR ]; /* transmit segment descriptors */
  103. } tpd_t;
  104. /* receive segment descriptor */
  105. typedef struct rsd {
  106. u32 handle; /* host supplied receive buffer handle */
  107. u32 length; /* number of bytes in buffer */
  108. } rsd_t;
  109. /* receive PDU descriptor */
  110. typedef struct rpd {
  111. struct atm_header atm_header; /* ATM header minus HEC byte */
  112. u32 nseg; /* number of receive segments */
  113. struct rsd rsd[ RSD_NBR ]; /* receive segment descriptors */
  114. } rpd_t;
  115. /* buffer scheme */
  116. typedef enum buffer_scheme {
  117. BUFFER_SCHEME_ONE,
  118. BUFFER_SCHEME_TWO,
  119. BUFFER_SCHEME_NBR /* always last */
  120. } buffer_scheme_t;
  121. /* buffer magnitude */
  122. typedef enum buffer_magn {
  123. BUFFER_MAGN_SMALL,
  124. BUFFER_MAGN_LARGE,
  125. BUFFER_MAGN_NBR /* always last */
  126. } buffer_magn_t;
  127. /* receive buffer descriptor */
  128. typedef struct rbd {
  129. u32 handle; /* host supplied handle */
  130. u32 buffer_haddr; /* host DMA address of host buffer */
  131. } rbd_t;
  132. /* receive buffer descriptor block */
  133. typedef struct rbd_block {
  134. struct rbd rbd[ RBD_BLK_SIZE ]; /* receive buffer descriptor */
  135. } rbd_block_t;
  136. /* tpd DMA address */
  137. typedef struct tpd_haddr {
  138. BITFIELD3(
  139. u32 size : 4, /* tpd size expressed in 32 byte blocks */
  140. u32 pad : 1, /* reserved */
  141. u32 haddr : 27 /* tpd DMA addr aligned on 32 byte boundary */
  142. )
  143. } tpd_haddr_t;
  144. #define TPD_HADDR_SHIFT 5 /* addr aligned on 32 byte boundary */
  145. /* cp resident transmit queue entry */
  146. typedef struct cp_txq_entry {
  147. struct tpd_haddr tpd_haddr; /* host DMA address of tpd */
  148. u32 status_haddr; /* host DMA address of completion status */
  149. } cp_txq_entry_t;
  150. /* cp resident receive queue entry */
  151. typedef struct cp_rxq_entry {
  152. u32 rpd_haddr; /* host DMA address of rpd */
  153. u32 status_haddr; /* host DMA address of completion status */
  154. } cp_rxq_entry_t;
  155. /* cp resident buffer supply queue entry */
  156. typedef struct cp_bsq_entry {
  157. u32 rbd_block_haddr; /* host DMA address of rbd block */
  158. u32 status_haddr; /* host DMA address of completion status */
  159. } cp_bsq_entry_t;
  160. /* completion status */
  161. typedef volatile enum status {
  162. STATUS_PENDING = (1<<0), /* initial status (written by host) */
  163. STATUS_COMPLETE = (1<<1), /* completion status (written by cp) */
  164. STATUS_FREE = (1<<2), /* initial status (written by host) */
  165. STATUS_ERROR = (1<<3) /* completion status (written by cp) */
  166. } status_t;
  167. /* cp operation code */
  168. typedef enum opcode {
  169. OPCODE_INITIALIZE = 1, /* initialize board */
  170. OPCODE_ACTIVATE_VCIN, /* activate incoming VCI */
  171. OPCODE_ACTIVATE_VCOUT, /* activate outgoing VCI */
  172. OPCODE_DEACTIVATE_VCIN, /* deactivate incoming VCI */
  173. OPCODE_DEACTIVATE_VCOUT, /* deactivate incoing VCI */
  174. OPCODE_GET_STATS, /* get board statistics */
  175. OPCODE_SET_OC3, /* set OC-3 registers */
  176. OPCODE_GET_OC3, /* get OC-3 registers */
  177. OPCODE_RESET_STATS, /* reset board statistics */
  178. OPCODE_GET_PROM, /* get expansion PROM data (PCI specific) */
  179. OPCODE_SET_VPI_BITS, /* set x bits of those decoded by the
  180. firmware to be low order bits from
  181. the VPI field of the ATM cell header */
  182. OPCODE_REQUEST_INTR = (1<<7) /* request interrupt */
  183. } opcode_t;
  184. /* virtual path / virtual channel identifiers */
  185. typedef struct vpvc {
  186. BITFIELD3(
  187. u32 vci : 16, /* virtual channel identifier */
  188. u32 vpi : 8, /* virtual path identifier */
  189. u32 pad : 8 /* reserved */
  190. )
  191. } vpvc_t;
  192. /* activate VC command opcode */
  193. typedef struct activate_opcode {
  194. BITFIELD4(
  195. enum opcode opcode : 8, /* cp opcode */
  196. enum fore200e_aal aal : 8, /* adaptation layer */
  197. enum buffer_scheme scheme : 8, /* buffer scheme */
  198. u32 pad : 8 /* reserved */
  199. )
  200. } activate_opcode_t;
  201. /* activate VC command block */
  202. typedef struct activate_block {
  203. struct activate_opcode opcode; /* activate VC command opcode */
  204. struct vpvc vpvc; /* VPI/VCI */
  205. u32 mtu; /* for AAL0 only */
  206. } activate_block_t;
  207. /* deactivate VC command opcode */
  208. typedef struct deactivate_opcode {
  209. BITFIELD2(
  210. enum opcode opcode : 8, /* cp opcode */
  211. u32 pad : 24 /* reserved */
  212. )
  213. } deactivate_opcode_t;
  214. /* deactivate VC command block */
  215. typedef struct deactivate_block {
  216. struct deactivate_opcode opcode; /* deactivate VC command opcode */
  217. struct vpvc vpvc; /* VPI/VCI */
  218. } deactivate_block_t;
  219. /* OC-3 registers */
  220. typedef struct oc3_regs {
  221. u32 reg[ 128 ]; /* see the PMC Sierra PC5346 S/UNI-155-Lite
  222. Saturn User Network Interface documentation
  223. for a description of the OC-3 chip registers */
  224. } oc3_regs_t;
  225. /* set/get OC-3 regs command opcode */
  226. typedef struct oc3_opcode {
  227. BITFIELD4(
  228. enum opcode opcode : 8, /* cp opcode */
  229. u32 reg : 8, /* register index */
  230. u32 value : 8, /* register value */
  231. u32 mask : 8 /* register mask that specifies which
  232. bits of the register value field
  233. are significant */
  234. )
  235. } oc3_opcode_t;
  236. /* set/get OC-3 regs command block */
  237. typedef struct oc3_block {
  238. struct oc3_opcode opcode; /* set/get OC-3 regs command opcode */
  239. u32 regs_haddr; /* host DMA address of OC-3 regs buffer */
  240. } oc3_block_t;
  241. /* physical encoding statistics */
  242. typedef struct stats_phy {
  243. __be32 crc_header_errors; /* cells received with bad header CRC */
  244. __be32 framing_errors; /* cells received with bad framing */
  245. __be32 pad[ 2 ]; /* i960 padding */
  246. } stats_phy_t;
  247. /* OC-3 statistics */
  248. typedef struct stats_oc3 {
  249. __be32 section_bip8_errors; /* section 8 bit interleaved parity */
  250. __be32 path_bip8_errors; /* path 8 bit interleaved parity */
  251. __be32 line_bip24_errors; /* line 24 bit interleaved parity */
  252. __be32 line_febe_errors; /* line far end block errors */
  253. __be32 path_febe_errors; /* path far end block errors */
  254. __be32 corr_hcs_errors; /* correctable header check sequence */
  255. __be32 ucorr_hcs_errors; /* uncorrectable header check sequence */
  256. __be32 pad[ 1 ]; /* i960 padding */
  257. } stats_oc3_t;
  258. /* ATM statistics */
  259. typedef struct stats_atm {
  260. __be32 cells_transmitted; /* cells transmitted */
  261. __be32 cells_received; /* cells received */
  262. __be32 vpi_bad_range; /* cell drops: VPI out of range */
  263. __be32 vpi_no_conn; /* cell drops: no connection for VPI */
  264. __be32 vci_bad_range; /* cell drops: VCI out of range */
  265. __be32 vci_no_conn; /* cell drops: no connection for VCI */
  266. __be32 pad[ 2 ]; /* i960 padding */
  267. } stats_atm_t;
  268. /* AAL0 statistics */
  269. typedef struct stats_aal0 {
  270. __be32 cells_transmitted; /* cells transmitted */
  271. __be32 cells_received; /* cells received */
  272. __be32 cells_dropped; /* cells dropped */
  273. __be32 pad[ 1 ]; /* i960 padding */
  274. } stats_aal0_t;
  275. /* AAL3/4 statistics */
  276. typedef struct stats_aal34 {
  277. __be32 cells_transmitted; /* cells transmitted from segmented PDUs */
  278. __be32 cells_received; /* cells reassembled into PDUs */
  279. __be32 cells_crc_errors; /* payload CRC error count */
  280. __be32 cells_protocol_errors; /* SAR or CS layer protocol errors */
  281. __be32 cells_dropped; /* cells dropped: partial reassembly */
  282. __be32 cspdus_transmitted; /* CS PDUs transmitted */
  283. __be32 cspdus_received; /* CS PDUs received */
  284. __be32 cspdus_protocol_errors; /* CS layer protocol errors */
  285. __be32 cspdus_dropped; /* reassembled PDUs drop'd (in cells) */
  286. __be32 pad[ 3 ]; /* i960 padding */
  287. } stats_aal34_t;
  288. /* AAL5 statistics */
  289. typedef struct stats_aal5 {
  290. __be32 cells_transmitted; /* cells transmitted from segmented SDUs */
  291. __be32 cells_received; /* cells reassembled into SDUs */
  292. __be32 cells_dropped; /* reassembled PDUs dropped (in cells) */
  293. __be32 congestion_experienced; /* CRC error and length wrong */
  294. __be32 cspdus_transmitted; /* CS PDUs transmitted */
  295. __be32 cspdus_received; /* CS PDUs received */
  296. __be32 cspdus_crc_errors; /* CS PDUs CRC errors */
  297. __be32 cspdus_protocol_errors; /* CS layer protocol errors */
  298. __be32 cspdus_dropped; /* reassembled PDUs dropped */
  299. __be32 pad[ 3 ]; /* i960 padding */
  300. } stats_aal5_t;
  301. /* auxiliary statistics */
  302. typedef struct stats_aux {
  303. __be32 small_b1_failed; /* receive BD allocation failures */
  304. __be32 large_b1_failed; /* receive BD allocation failures */
  305. __be32 small_b2_failed; /* receive BD allocation failures */
  306. __be32 large_b2_failed; /* receive BD allocation failures */
  307. __be32 rpd_alloc_failed; /* receive PDU allocation failures */
  308. __be32 receive_carrier; /* no carrier = 0, carrier = 1 */
  309. __be32 pad[ 2 ]; /* i960 padding */
  310. } stats_aux_t;
  311. /* whole statistics buffer */
  312. typedef struct stats {
  313. struct stats_phy phy; /* physical encoding statistics */
  314. struct stats_oc3 oc3; /* OC-3 statistics */
  315. struct stats_atm atm; /* ATM statistics */
  316. struct stats_aal0 aal0; /* AAL0 statistics */
  317. struct stats_aal34 aal34; /* AAL3/4 statistics */
  318. struct stats_aal5 aal5; /* AAL5 statistics */
  319. struct stats_aux aux; /* auxiliary statistics */
  320. } stats_t;
  321. /* get statistics command opcode */
  322. typedef struct stats_opcode {
  323. BITFIELD2(
  324. enum opcode opcode : 8, /* cp opcode */
  325. u32 pad : 24 /* reserved */
  326. )
  327. } stats_opcode_t;
  328. /* get statistics command block */
  329. typedef struct stats_block {
  330. struct stats_opcode opcode; /* get statistics command opcode */
  331. u32 stats_haddr; /* host DMA address of stats buffer */
  332. } stats_block_t;
  333. /* expansion PROM data (PCI specific) */
  334. typedef struct prom_data {
  335. u32 hw_revision; /* hardware revision */
  336. u32 serial_number; /* board serial number */
  337. u8 mac_addr[ 8 ]; /* board MAC address */
  338. } prom_data_t;
  339. /* get expansion PROM data command opcode */
  340. typedef struct prom_opcode {
  341. BITFIELD2(
  342. enum opcode opcode : 8, /* cp opcode */
  343. u32 pad : 24 /* reserved */
  344. )
  345. } prom_opcode_t;
  346. /* get expansion PROM data command block */
  347. typedef struct prom_block {
  348. struct prom_opcode opcode; /* get PROM data command opcode */
  349. u32 prom_haddr; /* host DMA address of PROM buffer */
  350. } prom_block_t;
  351. /* cp command */
  352. typedef union cmd {
  353. enum opcode opcode; /* operation code */
  354. struct activate_block activate_block; /* activate VC */
  355. struct deactivate_block deactivate_block; /* deactivate VC */
  356. struct stats_block stats_block; /* get statistics */
  357. struct prom_block prom_block; /* get expansion PROM data */
  358. struct oc3_block oc3_block; /* get/set OC-3 registers */
  359. u32 pad[ 4 ]; /* i960 padding */
  360. } cmd_t;
  361. /* cp resident command queue */
  362. typedef struct cp_cmdq_entry {
  363. union cmd cmd; /* command */
  364. u32 status_haddr; /* host DMA address of completion status */
  365. u32 pad[ 3 ]; /* i960 padding */
  366. } cp_cmdq_entry_t;
  367. /* host resident transmit queue entry */
  368. typedef struct host_txq_entry {
  369. struct cp_txq_entry __iomem *cp_entry; /* addr of cp resident tx queue entry */
  370. enum status* status; /* addr of host resident status */
  371. struct tpd* tpd; /* addr of transmit PDU descriptor */
  372. u32 tpd_dma; /* DMA address of tpd */
  373. struct sk_buff* skb; /* related skb */
  374. void* data; /* copy of misaligned data */
  375. unsigned long incarn; /* vc_map incarnation when submitted for tx */
  376. struct fore200e_vc_map* vc_map;
  377. } host_txq_entry_t;
  378. /* host resident receive queue entry */
  379. typedef struct host_rxq_entry {
  380. struct cp_rxq_entry __iomem *cp_entry; /* addr of cp resident rx queue entry */
  381. enum status* status; /* addr of host resident status */
  382. struct rpd* rpd; /* addr of receive PDU descriptor */
  383. u32 rpd_dma; /* DMA address of rpd */
  384. } host_rxq_entry_t;
  385. /* host resident buffer supply queue entry */
  386. typedef struct host_bsq_entry {
  387. struct cp_bsq_entry __iomem *cp_entry; /* addr of cp resident buffer supply queue entry */
  388. enum status* status; /* addr of host resident status */
  389. struct rbd_block* rbd_block; /* addr of receive buffer descriptor block */
  390. u32 rbd_block_dma; /* DMA address od rdb */
  391. } host_bsq_entry_t;
  392. /* host resident command queue entry */
  393. typedef struct host_cmdq_entry {
  394. struct cp_cmdq_entry __iomem *cp_entry; /* addr of cp resident cmd queue entry */
  395. enum status *status; /* addr of host resident status */
  396. } host_cmdq_entry_t;
  397. /* chunk of memory */
  398. typedef struct chunk {
  399. void* alloc_addr; /* base address of allocated chunk */
  400. void* align_addr; /* base address of aligned chunk */
  401. dma_addr_t dma_addr; /* DMA address of aligned chunk */
  402. int direction; /* direction of DMA mapping */
  403. u32 alloc_size; /* length of allocated chunk */
  404. u32 align_size; /* length of aligned chunk */
  405. } chunk_t;
  406. #define dma_size align_size /* DMA useable size */
  407. /* host resident receive buffer */
  408. typedef struct buffer {
  409. struct buffer* next; /* next receive buffer */
  410. enum buffer_scheme scheme; /* buffer scheme */
  411. enum buffer_magn magn; /* buffer magnitude */
  412. struct chunk data; /* data buffer */
  413. #ifdef FORE200E_BSQ_DEBUG
  414. unsigned long index; /* buffer # in queue */
  415. int supplied; /* 'buffer supplied' flag */
  416. #endif
  417. } buffer_t;
  418. #if (BITS_PER_LONG == 32)
  419. #define FORE200E_BUF2HDL(buffer) ((u32)(buffer))
  420. #define FORE200E_HDL2BUF(handle) ((struct buffer*)(handle))
  421. #else /* deal with 64 bit pointers */
  422. #define FORE200E_BUF2HDL(buffer) ((u32)((u64)(buffer)))
  423. #define FORE200E_HDL2BUF(handle) ((struct buffer*)(((u64)(handle)) | PAGE_OFFSET))
  424. #endif
  425. /* host resident command queue */
  426. typedef struct host_cmdq {
  427. struct host_cmdq_entry host_entry[ QUEUE_SIZE_CMD ]; /* host resident cmd queue entries */
  428. int head; /* head of cmd queue */
  429. struct chunk status; /* array of completion status */
  430. } host_cmdq_t;
  431. /* host resident transmit queue */
  432. typedef struct host_txq {
  433. struct host_txq_entry host_entry[ QUEUE_SIZE_TX ]; /* host resident tx queue entries */
  434. int head; /* head of tx queue */
  435. int tail; /* tail of tx queue */
  436. struct chunk tpd; /* array of tpds */
  437. struct chunk status; /* arry of completion status */
  438. int txing; /* number of pending PDUs in tx queue */
  439. } host_txq_t;
  440. /* host resident receive queue */
  441. typedef struct host_rxq {
  442. struct host_rxq_entry host_entry[ QUEUE_SIZE_RX ]; /* host resident rx queue entries */
  443. int head; /* head of rx queue */
  444. struct chunk rpd; /* array of rpds */
  445. struct chunk status; /* array of completion status */
  446. } host_rxq_t;
  447. /* host resident buffer supply queues */
  448. typedef struct host_bsq {
  449. struct host_bsq_entry host_entry[ QUEUE_SIZE_BS ]; /* host resident buffer supply queue entries */
  450. int head; /* head of buffer supply queue */
  451. struct chunk rbd_block; /* array of rbds */
  452. struct chunk status; /* array of completion status */
  453. struct buffer* buffer; /* array of rx buffers */
  454. struct buffer* freebuf; /* list of free rx buffers */
  455. volatile int freebuf_count; /* count of free rx buffers */
  456. } host_bsq_t;
  457. /* header of the firmware image */
  458. typedef struct fw_header {
  459. __le32 magic; /* magic number */
  460. __le32 version; /* firmware version id */
  461. __le32 load_offset; /* fw load offset in board memory */
  462. __le32 start_offset; /* fw execution start address in board memory */
  463. } fw_header_t;
  464. #define FW_HEADER_MAGIC 0x65726f66 /* 'fore' */
  465. /* receive buffer supply queues scheme specification */
  466. typedef struct bs_spec {
  467. u32 queue_length; /* queue capacity */
  468. u32 buffer_size; /* host buffer size */
  469. u32 pool_size; /* number of rbds */
  470. u32 supply_blksize; /* num of rbds in I/O block (multiple
  471. of 4 between 4 and 124 inclusive) */
  472. } bs_spec_t;
  473. /* initialization command block (one-time command, not in cmd queue) */
  474. typedef struct init_block {
  475. enum opcode opcode; /* initialize command */
  476. enum status status; /* related status word */
  477. u32 receive_threshold; /* not used */
  478. u32 num_connect; /* ATM connections */
  479. u32 cmd_queue_len; /* length of command queue */
  480. u32 tx_queue_len; /* length of transmit queue */
  481. u32 rx_queue_len; /* length of receive queue */
  482. u32 rsd_extension; /* number of extra 32 byte blocks */
  483. u32 tsd_extension; /* number of extra 32 byte blocks */
  484. u32 conless_vpvc; /* not used */
  485. u32 pad[ 2 ]; /* force quad alignment */
  486. struct bs_spec bs_spec[ BUFFER_SCHEME_NBR ][ BUFFER_MAGN_NBR ]; /* buffer supply queues spec */
  487. } init_block_t;
  488. typedef enum media_type {
  489. MEDIA_TYPE_CAT5_UTP = 0x06, /* unshielded twisted pair */
  490. MEDIA_TYPE_MM_OC3_ST = 0x16, /* multimode fiber ST */
  491. MEDIA_TYPE_MM_OC3_SC = 0x26, /* multimode fiber SC */
  492. MEDIA_TYPE_SM_OC3_ST = 0x36, /* single-mode fiber ST */
  493. MEDIA_TYPE_SM_OC3_SC = 0x46 /* single-mode fiber SC */
  494. } media_type_t;
  495. #define FORE200E_MEDIA_INDEX(media_type) ((media_type)>>4)
  496. /* cp resident queues */
  497. typedef struct cp_queues {
  498. u32 cp_cmdq; /* command queue */
  499. u32 cp_txq; /* transmit queue */
  500. u32 cp_rxq; /* receive queue */
  501. u32 cp_bsq[ BUFFER_SCHEME_NBR ][ BUFFER_MAGN_NBR ]; /* buffer supply queues */
  502. u32 imask; /* 1 enables cp to host interrupts */
  503. u32 istat; /* 1 for interrupt posted */
  504. u32 heap_base; /* offset form beginning of ram */
  505. u32 heap_size; /* space available for queues */
  506. u32 hlogger; /* non zero for host logging */
  507. u32 heartbeat; /* cp heartbeat */
  508. u32 fw_release; /* firmware version */
  509. u32 mon960_release; /* i960 monitor version */
  510. u32 tq_plen; /* transmit throughput measurements */
  511. /* make sure the init block remains on a quad word boundary */
  512. struct init_block init; /* one time cmd, not in cmd queue */
  513. enum media_type media_type; /* media type id */
  514. u32 oc3_revision; /* OC-3 revision number */
  515. } cp_queues_t;
  516. /* boot status */
  517. typedef enum boot_status {
  518. BSTAT_COLD_START = (u32) 0xc01dc01d, /* cold start */
  519. BSTAT_SELFTEST_OK = (u32) 0x02201958, /* self-test ok */
  520. BSTAT_SELFTEST_FAIL = (u32) 0xadbadbad, /* self-test failed */
  521. BSTAT_CP_RUNNING = (u32) 0xce11feed, /* cp is running */
  522. BSTAT_MON_TOO_BIG = (u32) 0x10aded00 /* i960 monitor is too big */
  523. } boot_status_t;
  524. /* software UART */
  525. typedef struct soft_uart {
  526. u32 send; /* write register */
  527. u32 recv; /* read register */
  528. } soft_uart_t;
  529. #define FORE200E_CP_MONITOR_UART_FREE 0x00000000
  530. #define FORE200E_CP_MONITOR_UART_AVAIL 0x01000000
  531. /* i960 monitor */
  532. typedef struct cp_monitor {
  533. struct soft_uart soft_uart; /* software UART */
  534. enum boot_status bstat; /* boot status */
  535. u32 app_base; /* application base offset */
  536. u32 mon_version; /* i960 monitor version */
  537. } cp_monitor_t;
  538. /* device state */
  539. typedef enum fore200e_state {
  540. FORE200E_STATE_BLANK, /* initial state */
  541. FORE200E_STATE_REGISTER, /* device registered */
  542. FORE200E_STATE_CONFIGURE, /* bus interface configured */
  543. FORE200E_STATE_MAP, /* board space mapped in host memory */
  544. FORE200E_STATE_RESET, /* board resetted */
  545. FORE200E_STATE_START_FW, /* firmware started */
  546. FORE200E_STATE_INITIALIZE, /* initialize command successful */
  547. FORE200E_STATE_INIT_CMDQ, /* command queue initialized */
  548. FORE200E_STATE_INIT_TXQ, /* transmit queue initialized */
  549. FORE200E_STATE_INIT_RXQ, /* receive queue initialized */
  550. FORE200E_STATE_INIT_BSQ, /* buffer supply queue initialized */
  551. FORE200E_STATE_ALLOC_BUF, /* receive buffers allocated */
  552. FORE200E_STATE_IRQ, /* host interrupt requested */
  553. FORE200E_STATE_COMPLETE /* initialization completed */
  554. } fore200e_state;
  555. /* PCA-200E registers */
  556. typedef struct fore200e_pca_regs {
  557. volatile u32 __iomem * hcr; /* address of host control register */
  558. volatile u32 __iomem * imr; /* address of host interrupt mask register */
  559. volatile u32 __iomem * psr; /* address of PCI specific register */
  560. } fore200e_pca_regs_t;
  561. /* SBA-200E registers */
  562. typedef struct fore200e_sba_regs {
  563. u32 __iomem *hcr; /* address of host control register */
  564. u32 __iomem *bsr; /* address of burst transfer size register */
  565. u32 __iomem *isr; /* address of interrupt level selection register */
  566. } fore200e_sba_regs_t;
  567. /* model-specific registers */
  568. typedef union fore200e_regs {
  569. struct fore200e_pca_regs pca; /* PCA-200E registers */
  570. struct fore200e_sba_regs sba; /* SBA-200E registers */
  571. } fore200e_regs;
  572. struct fore200e;
  573. /* bus-dependent data */
  574. typedef struct fore200e_bus {
  575. char* model_name; /* board model name */
  576. char* proc_name; /* board name under /proc/atm */
  577. int descr_alignment; /* tpd/rpd/rbd DMA alignment requirement */
  578. int buffer_alignment; /* rx buffers DMA alignment requirement */
  579. int status_alignment; /* status words DMA alignment requirement */
  580. u32 (*read)(volatile u32 __iomem *);
  581. void (*write)(u32, volatile u32 __iomem *);
  582. int (*configure)(struct fore200e*);
  583. int (*map)(struct fore200e*);
  584. void (*reset)(struct fore200e*);
  585. int (*prom_read)(struct fore200e*, struct prom_data*);
  586. void (*unmap)(struct fore200e*);
  587. void (*irq_enable)(struct fore200e*);
  588. int (*irq_check)(struct fore200e*);
  589. void (*irq_ack)(struct fore200e*);
  590. int (*proc_read)(struct fore200e*, char*);
  591. } fore200e_bus_t;
  592. /* vc mapping */
  593. typedef struct fore200e_vc_map {
  594. struct atm_vcc* vcc; /* vcc entry */
  595. unsigned long incarn; /* vcc incarnation number */
  596. } fore200e_vc_map_t;
  597. #define FORE200E_VC_MAP(fore200e, vpi, vci) \
  598. (& (fore200e)->vc_map[ ((vpi) << FORE200E_VCI_BITS) | (vci) ])
  599. /* per-device data */
  600. typedef struct fore200e {
  601. struct list_head entry; /* next device */
  602. const struct fore200e_bus* bus; /* bus-dependent code and data */
  603. union fore200e_regs regs; /* bus-dependent registers */
  604. struct atm_dev* atm_dev; /* ATM device */
  605. enum fore200e_state state; /* device state */
  606. char name[16]; /* device name */
  607. struct device *dev;
  608. int irq; /* irq number */
  609. unsigned long phys_base; /* physical base address */
  610. void __iomem * virt_base; /* virtual base address */
  611. unsigned char esi[ ESI_LEN ]; /* end system identifier */
  612. struct cp_monitor __iomem * cp_monitor; /* i960 monitor address */
  613. struct cp_queues __iomem * cp_queues; /* cp resident queues */
  614. struct host_cmdq host_cmdq; /* host resident cmd queue */
  615. struct host_txq host_txq; /* host resident tx queue */
  616. struct host_rxq host_rxq; /* host resident rx queue */
  617. /* host resident buffer supply queues */
  618. struct host_bsq host_bsq[ BUFFER_SCHEME_NBR ][ BUFFER_MAGN_NBR ];
  619. u32 available_cell_rate; /* remaining pseudo-CBR bw on link */
  620. int loop_mode; /* S/UNI loopback mode */
  621. struct stats* stats; /* last snapshot of the stats */
  622. struct mutex rate_mtx; /* protects rate reservation ops */
  623. spinlock_t q_lock; /* protects queue ops */
  624. #ifdef FORE200E_USE_TASKLET
  625. struct tasklet_struct tx_tasklet; /* performs tx interrupt work */
  626. struct tasklet_struct rx_tasklet; /* performs rx interrupt work */
  627. #endif
  628. unsigned long tx_sat; /* tx queue saturation count */
  629. unsigned long incarn_count;
  630. struct fore200e_vc_map vc_map[ NBR_CONNECT ]; /* vc mapping */
  631. } fore200e_t;
  632. /* per-vcc data */
  633. typedef struct fore200e_vcc {
  634. enum buffer_scheme scheme; /* rx buffer scheme */
  635. struct tpd_rate rate; /* tx rate control data */
  636. int rx_min_pdu; /* size of smallest PDU received */
  637. int rx_max_pdu; /* size of largest PDU received */
  638. int tx_min_pdu; /* size of smallest PDU transmitted */
  639. int tx_max_pdu; /* size of largest PDU transmitted */
  640. unsigned long tx_pdu; /* nbr of tx pdus */
  641. unsigned long rx_pdu; /* nbr of rx pdus */
  642. } fore200e_vcc_t;
  643. /* 200E-series common memory layout */
  644. #define FORE200E_CP_MONITOR_OFFSET 0x00000400 /* i960 monitor interface */
  645. #define FORE200E_CP_QUEUES_OFFSET 0x00004d40 /* cp resident queues */
  646. /* PCA-200E memory layout */
  647. #define PCA200E_IOSPACE_LENGTH 0x00200000
  648. #define PCA200E_HCR_OFFSET 0x00100000 /* board control register */
  649. #define PCA200E_IMR_OFFSET 0x00100004 /* host IRQ mask register */
  650. #define PCA200E_PSR_OFFSET 0x00100008 /* PCI specific register */
  651. /* PCA-200E host control register */
  652. #define PCA200E_HCR_RESET (1<<0) /* read / write */
  653. #define PCA200E_HCR_HOLD_LOCK (1<<1) /* read / write */
  654. #define PCA200E_HCR_I960FAIL (1<<2) /* read */
  655. #define PCA200E_HCR_INTRB (1<<2) /* write */
  656. #define PCA200E_HCR_HOLD_ACK (1<<3) /* read */
  657. #define PCA200E_HCR_INTRA (1<<3) /* write */
  658. #define PCA200E_HCR_OUTFULL (1<<4) /* read */
  659. #define PCA200E_HCR_CLRINTR (1<<4) /* write */
  660. #define PCA200E_HCR_ESPHOLD (1<<5) /* read */
  661. #define PCA200E_HCR_INFULL (1<<6) /* read */
  662. #define PCA200E_HCR_TESTMODE (1<<7) /* read */
  663. /* PCA-200E PCI bus interface regs (offsets in PCI config space) */
  664. #define PCA200E_PCI_LATENCY 0x40 /* maximum slave latenty */
  665. #define PCA200E_PCI_MASTER_CTRL 0x41 /* master control */
  666. #define PCA200E_PCI_THRESHOLD 0x42 /* burst / continuous req threshold */
  667. /* PBI master control register */
  668. #define PCA200E_CTRL_DIS_CACHE_RD (1<<0) /* disable cache-line reads */
  669. #define PCA200E_CTRL_DIS_WRT_INVAL (1<<1) /* disable writes and invalidates */
  670. #define PCA200E_CTRL_2_CACHE_WRT_INVAL (1<<2) /* require 2 cache-lines for writes and invalidates */
  671. #define PCA200E_CTRL_IGN_LAT_TIMER (1<<3) /* ignore the latency timer */
  672. #define PCA200E_CTRL_ENA_CONT_REQ_MODE (1<<4) /* enable continuous request mode */
  673. #define PCA200E_CTRL_LARGE_PCI_BURSTS (1<<5) /* force large PCI bus bursts */
  674. #define PCA200E_CTRL_CONVERT_ENDIAN (1<<6) /* convert endianess of slave RAM accesses */
  675. #define SBA200E_PROM_NAME "FORE,sba-200e" /* device name in openprom tree */
  676. /* size of SBA-200E registers */
  677. #define SBA200E_HCR_LENGTH 4
  678. #define SBA200E_BSR_LENGTH 4
  679. #define SBA200E_ISR_LENGTH 4
  680. #define SBA200E_RAM_LENGTH 0x40000
  681. /* SBA-200E SBUS burst transfer size register */
  682. #define SBA200E_BSR_BURST4 0x04
  683. #define SBA200E_BSR_BURST8 0x08
  684. #define SBA200E_BSR_BURST16 0x10
  685. /* SBA-200E host control register */
  686. #define SBA200E_HCR_RESET (1<<0) /* read / write (sticky) */
  687. #define SBA200E_HCR_HOLD_LOCK (1<<1) /* read / write (sticky) */
  688. #define SBA200E_HCR_I960FAIL (1<<2) /* read */
  689. #define SBA200E_HCR_I960SETINTR (1<<2) /* write */
  690. #define SBA200E_HCR_OUTFULL (1<<3) /* read */
  691. #define SBA200E_HCR_INTR_CLR (1<<3) /* write */
  692. #define SBA200E_HCR_INTR_ENA (1<<4) /* read / write (sticky) */
  693. #define SBA200E_HCR_ESPHOLD (1<<5) /* read */
  694. #define SBA200E_HCR_INFULL (1<<6) /* read */
  695. #define SBA200E_HCR_TESTMODE (1<<7) /* read */
  696. #define SBA200E_HCR_INTR_REQ (1<<8) /* read */
  697. #define SBA200E_HCR_STICKY (SBA200E_HCR_RESET | SBA200E_HCR_HOLD_LOCK | SBA200E_HCR_INTR_ENA)
  698. #endif /* __KERNEL__ */
  699. #endif /* _FORE200E_H */