sata_vsc.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * sata_vsc.c - Vitesse VSC7174 4 port DPA SATA
  4. *
  5. * Maintained by: Jeremy Higdon @ SGI
  6. * Please ALWAYS copy linux-ide@vger.kernel.org
  7. * on emails.
  8. *
  9. * Copyright 2004 SGI
  10. *
  11. * Bits from Jeff Garzik, Copyright RedHat, Inc.
  12. *
  13. * libata documentation is available via 'make {ps|pdf}docs',
  14. * as Documentation/driver-api/libata.rst
  15. *
  16. * Vitesse hardware documentation presumably available under NDA.
  17. * Intel 31244 (same hardware interface) documentation presumably
  18. * available from http://developer.intel.com/
  19. */
  20. #include <linux/kernel.h>
  21. #include <linux/module.h>
  22. #include <linux/pci.h>
  23. #include <linux/blkdev.h>
  24. #include <linux/delay.h>
  25. #include <linux/interrupt.h>
  26. #include <linux/dma-mapping.h>
  27. #include <linux/device.h>
  28. #include <scsi/scsi_host.h>
  29. #include <linux/libata.h>
  30. #define DRV_NAME "sata_vsc"
  31. #define DRV_VERSION "2.3"
  32. enum {
  33. VSC_MMIO_BAR = 0,
  34. /* Interrupt register offsets (from chip base address) */
  35. VSC_SATA_INT_STAT_OFFSET = 0x00,
  36. VSC_SATA_INT_MASK_OFFSET = 0x04,
  37. /* Taskfile registers offsets */
  38. VSC_SATA_TF_CMD_OFFSET = 0x00,
  39. VSC_SATA_TF_DATA_OFFSET = 0x00,
  40. VSC_SATA_TF_ERROR_OFFSET = 0x04,
  41. VSC_SATA_TF_FEATURE_OFFSET = 0x06,
  42. VSC_SATA_TF_NSECT_OFFSET = 0x08,
  43. VSC_SATA_TF_LBAL_OFFSET = 0x0c,
  44. VSC_SATA_TF_LBAM_OFFSET = 0x10,
  45. VSC_SATA_TF_LBAH_OFFSET = 0x14,
  46. VSC_SATA_TF_DEVICE_OFFSET = 0x18,
  47. VSC_SATA_TF_STATUS_OFFSET = 0x1c,
  48. VSC_SATA_TF_COMMAND_OFFSET = 0x1d,
  49. VSC_SATA_TF_ALTSTATUS_OFFSET = 0x28,
  50. VSC_SATA_TF_CTL_OFFSET = 0x29,
  51. /* DMA base */
  52. VSC_SATA_UP_DESCRIPTOR_OFFSET = 0x64,
  53. VSC_SATA_UP_DATA_BUFFER_OFFSET = 0x6C,
  54. VSC_SATA_DMA_CMD_OFFSET = 0x70,
  55. /* SCRs base */
  56. VSC_SATA_SCR_STATUS_OFFSET = 0x100,
  57. VSC_SATA_SCR_ERROR_OFFSET = 0x104,
  58. VSC_SATA_SCR_CONTROL_OFFSET = 0x108,
  59. /* Port stride */
  60. VSC_SATA_PORT_OFFSET = 0x200,
  61. /* Error interrupt status bit offsets */
  62. VSC_SATA_INT_ERROR_CRC = 0x40,
  63. VSC_SATA_INT_ERROR_T = 0x20,
  64. VSC_SATA_INT_ERROR_P = 0x10,
  65. VSC_SATA_INT_ERROR_R = 0x8,
  66. VSC_SATA_INT_ERROR_E = 0x4,
  67. VSC_SATA_INT_ERROR_M = 0x2,
  68. VSC_SATA_INT_PHY_CHANGE = 0x1,
  69. VSC_SATA_INT_ERROR = (VSC_SATA_INT_ERROR_CRC | VSC_SATA_INT_ERROR_T | \
  70. VSC_SATA_INT_ERROR_P | VSC_SATA_INT_ERROR_R | \
  71. VSC_SATA_INT_ERROR_E | VSC_SATA_INT_ERROR_M | \
  72. VSC_SATA_INT_PHY_CHANGE),
  73. };
  74. static int vsc_sata_scr_read(struct ata_link *link,
  75. unsigned int sc_reg, u32 *val)
  76. {
  77. if (sc_reg > SCR_CONTROL)
  78. return -EINVAL;
  79. *val = readl(link->ap->ioaddr.scr_addr + (sc_reg * 4));
  80. return 0;
  81. }
  82. static int vsc_sata_scr_write(struct ata_link *link,
  83. unsigned int sc_reg, u32 val)
  84. {
  85. if (sc_reg > SCR_CONTROL)
  86. return -EINVAL;
  87. writel(val, link->ap->ioaddr.scr_addr + (sc_reg * 4));
  88. return 0;
  89. }
  90. static void vsc_freeze(struct ata_port *ap)
  91. {
  92. void __iomem *mask_addr;
  93. mask_addr = ap->host->iomap[VSC_MMIO_BAR] +
  94. VSC_SATA_INT_MASK_OFFSET + ap->port_no;
  95. writeb(0, mask_addr);
  96. }
  97. static void vsc_thaw(struct ata_port *ap)
  98. {
  99. void __iomem *mask_addr;
  100. mask_addr = ap->host->iomap[VSC_MMIO_BAR] +
  101. VSC_SATA_INT_MASK_OFFSET + ap->port_no;
  102. writeb(0xff, mask_addr);
  103. }
  104. static void vsc_intr_mask_update(struct ata_port *ap, u8 ctl)
  105. {
  106. void __iomem *mask_addr;
  107. u8 mask;
  108. mask_addr = ap->host->iomap[VSC_MMIO_BAR] +
  109. VSC_SATA_INT_MASK_OFFSET + ap->port_no;
  110. mask = readb(mask_addr);
  111. if (ctl & ATA_NIEN)
  112. mask |= 0x80;
  113. else
  114. mask &= 0x7F;
  115. writeb(mask, mask_addr);
  116. }
  117. static void vsc_sata_tf_load(struct ata_port *ap, const struct ata_taskfile *tf)
  118. {
  119. struct ata_ioports *ioaddr = &ap->ioaddr;
  120. unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
  121. /*
  122. * The only thing the ctl register is used for is SRST.
  123. * That is not enabled or disabled via tf_load.
  124. * However, if ATA_NIEN is changed, then we need to change
  125. * the interrupt register.
  126. */
  127. if ((tf->ctl & ATA_NIEN) != (ap->last_ctl & ATA_NIEN)) {
  128. ap->last_ctl = tf->ctl;
  129. vsc_intr_mask_update(ap, tf->ctl & ATA_NIEN);
  130. }
  131. if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
  132. writew(tf->feature | (((u16)tf->hob_feature) << 8),
  133. ioaddr->feature_addr);
  134. writew(tf->nsect | (((u16)tf->hob_nsect) << 8),
  135. ioaddr->nsect_addr);
  136. writew(tf->lbal | (((u16)tf->hob_lbal) << 8),
  137. ioaddr->lbal_addr);
  138. writew(tf->lbam | (((u16)tf->hob_lbam) << 8),
  139. ioaddr->lbam_addr);
  140. writew(tf->lbah | (((u16)tf->hob_lbah) << 8),
  141. ioaddr->lbah_addr);
  142. } else if (is_addr) {
  143. writew(tf->feature, ioaddr->feature_addr);
  144. writew(tf->nsect, ioaddr->nsect_addr);
  145. writew(tf->lbal, ioaddr->lbal_addr);
  146. writew(tf->lbam, ioaddr->lbam_addr);
  147. writew(tf->lbah, ioaddr->lbah_addr);
  148. }
  149. if (tf->flags & ATA_TFLAG_DEVICE)
  150. writeb(tf->device, ioaddr->device_addr);
  151. ata_wait_idle(ap);
  152. }
  153. static void vsc_sata_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
  154. {
  155. struct ata_ioports *ioaddr = &ap->ioaddr;
  156. u16 nsect, lbal, lbam, lbah, feature;
  157. tf->command = ata_sff_check_status(ap);
  158. tf->device = readw(ioaddr->device_addr);
  159. feature = readw(ioaddr->error_addr);
  160. nsect = readw(ioaddr->nsect_addr);
  161. lbal = readw(ioaddr->lbal_addr);
  162. lbam = readw(ioaddr->lbam_addr);
  163. lbah = readw(ioaddr->lbah_addr);
  164. tf->feature = feature;
  165. tf->nsect = nsect;
  166. tf->lbal = lbal;
  167. tf->lbam = lbam;
  168. tf->lbah = lbah;
  169. if (tf->flags & ATA_TFLAG_LBA48) {
  170. tf->hob_feature = feature >> 8;
  171. tf->hob_nsect = nsect >> 8;
  172. tf->hob_lbal = lbal >> 8;
  173. tf->hob_lbam = lbam >> 8;
  174. tf->hob_lbah = lbah >> 8;
  175. }
  176. }
  177. static inline void vsc_error_intr(u8 port_status, struct ata_port *ap)
  178. {
  179. if (port_status & (VSC_SATA_INT_PHY_CHANGE | VSC_SATA_INT_ERROR_M))
  180. ata_port_freeze(ap);
  181. else
  182. ata_port_abort(ap);
  183. }
  184. static void vsc_port_intr(u8 port_status, struct ata_port *ap)
  185. {
  186. struct ata_queued_cmd *qc;
  187. int handled = 0;
  188. if (unlikely(port_status & VSC_SATA_INT_ERROR)) {
  189. vsc_error_intr(port_status, ap);
  190. return;
  191. }
  192. qc = ata_qc_from_tag(ap, ap->link.active_tag);
  193. if (qc && likely(!(qc->tf.flags & ATA_TFLAG_POLLING)))
  194. handled = ata_bmdma_port_intr(ap, qc);
  195. /* We received an interrupt during a polled command,
  196. * or some other spurious condition. Interrupt reporting
  197. * with this hardware is fairly reliable so it is safe to
  198. * simply clear the interrupt
  199. */
  200. if (unlikely(!handled))
  201. ap->ops->sff_check_status(ap);
  202. }
  203. /*
  204. * vsc_sata_interrupt
  205. *
  206. * Read the interrupt register and process for the devices that have
  207. * them pending.
  208. */
  209. static irqreturn_t vsc_sata_interrupt(int irq, void *dev_instance)
  210. {
  211. struct ata_host *host = dev_instance;
  212. unsigned int i;
  213. unsigned int handled = 0;
  214. u32 status;
  215. status = readl(host->iomap[VSC_MMIO_BAR] + VSC_SATA_INT_STAT_OFFSET);
  216. if (unlikely(status == 0xffffffff || status == 0)) {
  217. if (status)
  218. dev_err(host->dev,
  219. ": IRQ status == 0xffffffff, PCI fault or device removal?\n");
  220. goto out;
  221. }
  222. spin_lock(&host->lock);
  223. for (i = 0; i < host->n_ports; i++) {
  224. u8 port_status = (status >> (8 * i)) & 0xff;
  225. if (port_status) {
  226. vsc_port_intr(port_status, host->ports[i]);
  227. handled++;
  228. }
  229. }
  230. spin_unlock(&host->lock);
  231. out:
  232. return IRQ_RETVAL(handled);
  233. }
  234. static struct scsi_host_template vsc_sata_sht = {
  235. ATA_BMDMA_SHT(DRV_NAME),
  236. };
  237. static struct ata_port_operations vsc_sata_ops = {
  238. .inherits = &ata_bmdma_port_ops,
  239. /* The IRQ handling is not quite standard SFF behaviour so we
  240. cannot use the default lost interrupt handler */
  241. .lost_interrupt = ATA_OP_NULL,
  242. .sff_tf_load = vsc_sata_tf_load,
  243. .sff_tf_read = vsc_sata_tf_read,
  244. .freeze = vsc_freeze,
  245. .thaw = vsc_thaw,
  246. .scr_read = vsc_sata_scr_read,
  247. .scr_write = vsc_sata_scr_write,
  248. };
  249. static void vsc_sata_setup_port(struct ata_ioports *port, void __iomem *base)
  250. {
  251. port->cmd_addr = base + VSC_SATA_TF_CMD_OFFSET;
  252. port->data_addr = base + VSC_SATA_TF_DATA_OFFSET;
  253. port->error_addr = base + VSC_SATA_TF_ERROR_OFFSET;
  254. port->feature_addr = base + VSC_SATA_TF_FEATURE_OFFSET;
  255. port->nsect_addr = base + VSC_SATA_TF_NSECT_OFFSET;
  256. port->lbal_addr = base + VSC_SATA_TF_LBAL_OFFSET;
  257. port->lbam_addr = base + VSC_SATA_TF_LBAM_OFFSET;
  258. port->lbah_addr = base + VSC_SATA_TF_LBAH_OFFSET;
  259. port->device_addr = base + VSC_SATA_TF_DEVICE_OFFSET;
  260. port->status_addr = base + VSC_SATA_TF_STATUS_OFFSET;
  261. port->command_addr = base + VSC_SATA_TF_COMMAND_OFFSET;
  262. port->altstatus_addr = base + VSC_SATA_TF_ALTSTATUS_OFFSET;
  263. port->ctl_addr = base + VSC_SATA_TF_CTL_OFFSET;
  264. port->bmdma_addr = base + VSC_SATA_DMA_CMD_OFFSET;
  265. port->scr_addr = base + VSC_SATA_SCR_STATUS_OFFSET;
  266. writel(0, base + VSC_SATA_UP_DESCRIPTOR_OFFSET);
  267. writel(0, base + VSC_SATA_UP_DATA_BUFFER_OFFSET);
  268. }
  269. static int vsc_sata_init_one(struct pci_dev *pdev,
  270. const struct pci_device_id *ent)
  271. {
  272. static const struct ata_port_info pi = {
  273. .flags = ATA_FLAG_SATA,
  274. .pio_mask = ATA_PIO4,
  275. .mwdma_mask = ATA_MWDMA2,
  276. .udma_mask = ATA_UDMA6,
  277. .port_ops = &vsc_sata_ops,
  278. };
  279. const struct ata_port_info *ppi[] = { &pi, NULL };
  280. struct ata_host *host;
  281. void __iomem *mmio_base;
  282. int i, rc;
  283. u8 cls;
  284. ata_print_version_once(&pdev->dev, DRV_VERSION);
  285. /* allocate host */
  286. host = ata_host_alloc_pinfo(&pdev->dev, ppi, 4);
  287. if (!host)
  288. return -ENOMEM;
  289. rc = pcim_enable_device(pdev);
  290. if (rc)
  291. return rc;
  292. /* check if we have needed resource mapped */
  293. if (pci_resource_len(pdev, 0) == 0)
  294. return -ENODEV;
  295. /* map IO regions and initialize host accordingly */
  296. rc = pcim_iomap_regions(pdev, 1 << VSC_MMIO_BAR, DRV_NAME);
  297. if (rc == -EBUSY)
  298. pcim_pin_device(pdev);
  299. if (rc)
  300. return rc;
  301. host->iomap = pcim_iomap_table(pdev);
  302. mmio_base = host->iomap[VSC_MMIO_BAR];
  303. for (i = 0; i < host->n_ports; i++) {
  304. struct ata_port *ap = host->ports[i];
  305. unsigned int offset = (i + 1) * VSC_SATA_PORT_OFFSET;
  306. vsc_sata_setup_port(&ap->ioaddr, mmio_base + offset);
  307. ata_port_pbar_desc(ap, VSC_MMIO_BAR, -1, "mmio");
  308. ata_port_pbar_desc(ap, VSC_MMIO_BAR, offset, "port");
  309. }
  310. /*
  311. * Use 32 bit DMA mask, because 64 bit address support is poor.
  312. */
  313. rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
  314. if (rc)
  315. return rc;
  316. /*
  317. * Due to a bug in the chip, the default cache line size can't be
  318. * used (unless the default is non-zero).
  319. */
  320. pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &cls);
  321. if (cls == 0x00)
  322. pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x80);
  323. if (pci_enable_msi(pdev) == 0)
  324. pci_intx(pdev, 0);
  325. /*
  326. * Config offset 0x98 is "Extended Control and Status Register 0"
  327. * Default value is (1 << 28). All bits except bit 28 are reserved in
  328. * DPA mode. If bit 28 is set, LED 0 reflects all ports' activity.
  329. * If bit 28 is clear, each port has its own LED.
  330. */
  331. pci_write_config_dword(pdev, 0x98, 0);
  332. pci_set_master(pdev);
  333. return ata_host_activate(host, pdev->irq, vsc_sata_interrupt,
  334. IRQF_SHARED, &vsc_sata_sht);
  335. }
  336. static const struct pci_device_id vsc_sata_pci_tbl[] = {
  337. { PCI_VENDOR_ID_VITESSE, 0x7174,
  338. PCI_ANY_ID, PCI_ANY_ID, 0x10600, 0xFFFFFF, 0 },
  339. { PCI_VENDOR_ID_INTEL, 0x3200,
  340. PCI_ANY_ID, PCI_ANY_ID, 0x10600, 0xFFFFFF, 0 },
  341. { } /* terminate list */
  342. };
  343. static struct pci_driver vsc_sata_pci_driver = {
  344. .name = DRV_NAME,
  345. .id_table = vsc_sata_pci_tbl,
  346. .probe = vsc_sata_init_one,
  347. .remove = ata_pci_remove_one,
  348. };
  349. module_pci_driver(vsc_sata_pci_driver);
  350. MODULE_AUTHOR("Jeremy Higdon");
  351. MODULE_DESCRIPTION("low-level driver for Vitesse VSC7174 SATA controller");
  352. MODULE_LICENSE("GPL");
  353. MODULE_DEVICE_TABLE(pci, vsc_sata_pci_tbl);
  354. MODULE_VERSION(DRV_VERSION);