sata_via.c 20 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * sata_via.c - VIA Serial ATA controllers
  4. *
  5. * Maintained by: Tejun Heo <tj@kernel.org>
  6. * Please ALWAYS copy linux-ide@vger.kernel.org
  7. * on emails.
  8. *
  9. * Copyright 2003-2004 Red Hat, Inc. All rights reserved.
  10. * Copyright 2003-2004 Jeff Garzik
  11. *
  12. * libata documentation is available via 'make {ps|pdf}docs',
  13. * as Documentation/driver-api/libata.rst
  14. *
  15. * Hardware documentation available under NDA.
  16. */
  17. #include <linux/kernel.h>
  18. #include <linux/module.h>
  19. #include <linux/pci.h>
  20. #include <linux/blkdev.h>
  21. #include <linux/delay.h>
  22. #include <linux/device.h>
  23. #include <scsi/scsi.h>
  24. #include <scsi/scsi_cmnd.h>
  25. #include <scsi/scsi_host.h>
  26. #include <linux/libata.h>
  27. #define DRV_NAME "sata_via"
  28. #define DRV_VERSION "2.6"
  29. /*
  30. * vt8251 is different from other sata controllers of VIA. It has two
  31. * channels, each channel has both Master and Slave slot.
  32. */
  33. enum board_ids_enum {
  34. vt6420,
  35. vt6421,
  36. vt8251,
  37. };
  38. enum {
  39. SATA_CHAN_ENAB = 0x40, /* SATA channel enable */
  40. SATA_INT_GATE = 0x41, /* SATA interrupt gating */
  41. SATA_NATIVE_MODE = 0x42, /* Native mode enable */
  42. SVIA_MISC_3 = 0x46, /* Miscellaneous Control III */
  43. PATA_UDMA_TIMING = 0xB3, /* PATA timing for DMA/ cable detect */
  44. PATA_PIO_TIMING = 0xAB, /* PATA timing register */
  45. PORT0 = (1 << 1),
  46. PORT1 = (1 << 0),
  47. ALL_PORTS = PORT0 | PORT1,
  48. NATIVE_MODE_ALL = (1 << 7) | (1 << 6) | (1 << 5) | (1 << 4),
  49. SATA_EXT_PHY = (1 << 6), /* 0==use PATA, 1==ext phy */
  50. SATA_HOTPLUG = (1 << 5), /* enable IRQ on hotplug */
  51. };
  52. struct svia_priv {
  53. bool wd_workaround;
  54. };
  55. static int vt6420_hotplug;
  56. module_param_named(vt6420_hotplug, vt6420_hotplug, int, 0644);
  57. MODULE_PARM_DESC(vt6420_hotplug, "Enable hot-plug support for VT6420 (0=Don't support, 1=support)");
  58. static int svia_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
  59. #ifdef CONFIG_PM_SLEEP
  60. static int svia_pci_device_resume(struct pci_dev *pdev);
  61. #endif
  62. static int svia_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val);
  63. static int svia_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val);
  64. static int vt8251_scr_read(struct ata_link *link, unsigned int scr, u32 *val);
  65. static int vt8251_scr_write(struct ata_link *link, unsigned int scr, u32 val);
  66. static void svia_tf_load(struct ata_port *ap, const struct ata_taskfile *tf);
  67. static void svia_noop_freeze(struct ata_port *ap);
  68. static int vt6420_prereset(struct ata_link *link, unsigned long deadline);
  69. static void vt6420_bmdma_start(struct ata_queued_cmd *qc);
  70. static int vt6421_pata_cable_detect(struct ata_port *ap);
  71. static void vt6421_set_pio_mode(struct ata_port *ap, struct ata_device *adev);
  72. static void vt6421_set_dma_mode(struct ata_port *ap, struct ata_device *adev);
  73. static void vt6421_error_handler(struct ata_port *ap);
  74. static const struct pci_device_id svia_pci_tbl[] = {
  75. { PCI_VDEVICE(VIA, 0x5337), vt6420 },
  76. { PCI_VDEVICE(VIA, 0x0591), vt6420 }, /* 2 sata chnls (Master) */
  77. { PCI_VDEVICE(VIA, 0x3149), vt6420 }, /* 2 sata chnls (Master) */
  78. { PCI_VDEVICE(VIA, 0x3249), vt6421 }, /* 2 sata chnls, 1 pata chnl */
  79. { PCI_VDEVICE(VIA, 0x5372), vt6420 },
  80. { PCI_VDEVICE(VIA, 0x7372), vt6420 },
  81. { PCI_VDEVICE(VIA, 0x5287), vt8251 }, /* 2 sata chnls (Master/Slave) */
  82. { PCI_VDEVICE(VIA, 0x9000), vt8251 },
  83. { } /* terminate list */
  84. };
  85. static struct pci_driver svia_pci_driver = {
  86. .name = DRV_NAME,
  87. .id_table = svia_pci_tbl,
  88. .probe = svia_init_one,
  89. #ifdef CONFIG_PM_SLEEP
  90. .suspend = ata_pci_device_suspend,
  91. .resume = svia_pci_device_resume,
  92. #endif
  93. .remove = ata_pci_remove_one,
  94. };
  95. static struct scsi_host_template svia_sht = {
  96. ATA_BMDMA_SHT(DRV_NAME),
  97. };
  98. static struct ata_port_operations svia_base_ops = {
  99. .inherits = &ata_bmdma_port_ops,
  100. .sff_tf_load = svia_tf_load,
  101. };
  102. static struct ata_port_operations vt6420_sata_ops = {
  103. .inherits = &svia_base_ops,
  104. .freeze = svia_noop_freeze,
  105. .prereset = vt6420_prereset,
  106. .bmdma_start = vt6420_bmdma_start,
  107. };
  108. static struct ata_port_operations vt6421_pata_ops = {
  109. .inherits = &svia_base_ops,
  110. .cable_detect = vt6421_pata_cable_detect,
  111. .set_piomode = vt6421_set_pio_mode,
  112. .set_dmamode = vt6421_set_dma_mode,
  113. };
  114. static struct ata_port_operations vt6421_sata_ops = {
  115. .inherits = &svia_base_ops,
  116. .scr_read = svia_scr_read,
  117. .scr_write = svia_scr_write,
  118. .error_handler = vt6421_error_handler,
  119. };
  120. static struct ata_port_operations vt8251_ops = {
  121. .inherits = &svia_base_ops,
  122. .hardreset = sata_std_hardreset,
  123. .scr_read = vt8251_scr_read,
  124. .scr_write = vt8251_scr_write,
  125. };
  126. static const struct ata_port_info vt6420_port_info = {
  127. .flags = ATA_FLAG_SATA,
  128. .pio_mask = ATA_PIO4,
  129. .mwdma_mask = ATA_MWDMA2,
  130. .udma_mask = ATA_UDMA6,
  131. .port_ops = &vt6420_sata_ops,
  132. };
  133. static const struct ata_port_info vt6421_sport_info = {
  134. .flags = ATA_FLAG_SATA,
  135. .pio_mask = ATA_PIO4,
  136. .mwdma_mask = ATA_MWDMA2,
  137. .udma_mask = ATA_UDMA6,
  138. .port_ops = &vt6421_sata_ops,
  139. };
  140. static const struct ata_port_info vt6421_pport_info = {
  141. .flags = ATA_FLAG_SLAVE_POSS,
  142. .pio_mask = ATA_PIO4,
  143. /* No MWDMA */
  144. .udma_mask = ATA_UDMA6,
  145. .port_ops = &vt6421_pata_ops,
  146. };
  147. static const struct ata_port_info vt8251_port_info = {
  148. .flags = ATA_FLAG_SATA | ATA_FLAG_SLAVE_POSS,
  149. .pio_mask = ATA_PIO4,
  150. .mwdma_mask = ATA_MWDMA2,
  151. .udma_mask = ATA_UDMA6,
  152. .port_ops = &vt8251_ops,
  153. };
  154. MODULE_AUTHOR("Jeff Garzik");
  155. MODULE_DESCRIPTION("SCSI low-level driver for VIA SATA controllers");
  156. MODULE_LICENSE("GPL");
  157. MODULE_DEVICE_TABLE(pci, svia_pci_tbl);
  158. MODULE_VERSION(DRV_VERSION);
  159. static int svia_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val)
  160. {
  161. if (sc_reg > SCR_CONTROL)
  162. return -EINVAL;
  163. *val = ioread32(link->ap->ioaddr.scr_addr + (4 * sc_reg));
  164. return 0;
  165. }
  166. static int svia_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val)
  167. {
  168. if (sc_reg > SCR_CONTROL)
  169. return -EINVAL;
  170. iowrite32(val, link->ap->ioaddr.scr_addr + (4 * sc_reg));
  171. return 0;
  172. }
  173. static int vt8251_scr_read(struct ata_link *link, unsigned int scr, u32 *val)
  174. {
  175. static const u8 ipm_tbl[] = { 1, 2, 6, 0 };
  176. struct pci_dev *pdev = to_pci_dev(link->ap->host->dev);
  177. int slot = 2 * link->ap->port_no + link->pmp;
  178. u32 v = 0;
  179. u8 raw;
  180. switch (scr) {
  181. case SCR_STATUS:
  182. pci_read_config_byte(pdev, 0xA0 + slot, &raw);
  183. /* read the DET field, bit0 and 1 of the config byte */
  184. v |= raw & 0x03;
  185. /* read the SPD field, bit4 of the configure byte */
  186. if (raw & (1 << 4))
  187. v |= 0x02 << 4;
  188. else
  189. v |= 0x01 << 4;
  190. /* read the IPM field, bit2 and 3 of the config byte */
  191. v |= ipm_tbl[(raw >> 2) & 0x3];
  192. break;
  193. case SCR_ERROR:
  194. /* devices other than 5287 uses 0xA8 as base */
  195. WARN_ON(pdev->device != 0x5287);
  196. pci_read_config_dword(pdev, 0xB0 + slot * 4, &v);
  197. break;
  198. case SCR_CONTROL:
  199. pci_read_config_byte(pdev, 0xA4 + slot, &raw);
  200. /* read the DET field, bit0 and bit1 */
  201. v |= ((raw & 0x02) << 1) | (raw & 0x01);
  202. /* read the IPM field, bit2 and bit3 */
  203. v |= ((raw >> 2) & 0x03) << 8;
  204. break;
  205. default:
  206. return -EINVAL;
  207. }
  208. *val = v;
  209. return 0;
  210. }
  211. static int vt8251_scr_write(struct ata_link *link, unsigned int scr, u32 val)
  212. {
  213. struct pci_dev *pdev = to_pci_dev(link->ap->host->dev);
  214. int slot = 2 * link->ap->port_no + link->pmp;
  215. u32 v = 0;
  216. switch (scr) {
  217. case SCR_ERROR:
  218. /* devices other than 5287 uses 0xA8 as base */
  219. WARN_ON(pdev->device != 0x5287);
  220. pci_write_config_dword(pdev, 0xB0 + slot * 4, val);
  221. return 0;
  222. case SCR_CONTROL:
  223. /* set the DET field */
  224. v |= ((val & 0x4) >> 1) | (val & 0x1);
  225. /* set the IPM field */
  226. v |= ((val >> 8) & 0x3) << 2;
  227. pci_write_config_byte(pdev, 0xA4 + slot, v);
  228. return 0;
  229. default:
  230. return -EINVAL;
  231. }
  232. }
  233. /**
  234. * svia_tf_load - send taskfile registers to host controller
  235. * @ap: Port to which output is sent
  236. * @tf: ATA taskfile register set
  237. *
  238. * Outputs ATA taskfile to standard ATA host controller.
  239. *
  240. * This is to fix the internal bug of via chipsets, which will
  241. * reset the device register after changing the IEN bit on ctl
  242. * register.
  243. */
  244. static void svia_tf_load(struct ata_port *ap, const struct ata_taskfile *tf)
  245. {
  246. struct ata_taskfile ttf;
  247. if (tf->ctl != ap->last_ctl) {
  248. ttf = *tf;
  249. ttf.flags |= ATA_TFLAG_DEVICE;
  250. tf = &ttf;
  251. }
  252. ata_sff_tf_load(ap, tf);
  253. }
  254. static void svia_noop_freeze(struct ata_port *ap)
  255. {
  256. /* Some VIA controllers choke if ATA_NIEN is manipulated in
  257. * certain way. Leave it alone and just clear pending IRQ.
  258. */
  259. ap->ops->sff_check_status(ap);
  260. ata_bmdma_irq_clear(ap);
  261. }
  262. /**
  263. * vt6420_prereset - prereset for vt6420
  264. * @link: target ATA link
  265. * @deadline: deadline jiffies for the operation
  266. *
  267. * SCR registers on vt6420 are pieces of shit and may hang the
  268. * whole machine completely if accessed with the wrong timing.
  269. * To avoid such catastrophe, vt6420 doesn't provide generic SCR
  270. * access operations, but uses SStatus and SControl only during
  271. * boot probing in controlled way.
  272. *
  273. * As the old (pre EH update) probing code is proven to work, we
  274. * strictly follow the access pattern.
  275. *
  276. * LOCKING:
  277. * Kernel thread context (may sleep)
  278. *
  279. * RETURNS:
  280. * 0 on success, -errno otherwise.
  281. */
  282. static int vt6420_prereset(struct ata_link *link, unsigned long deadline)
  283. {
  284. struct ata_port *ap = link->ap;
  285. struct ata_eh_context *ehc = &ap->link.eh_context;
  286. unsigned long timeout = jiffies + (HZ * 5);
  287. u32 sstatus, scontrol;
  288. int online;
  289. /* don't do any SCR stuff if we're not loading */
  290. if (!(ap->pflags & ATA_PFLAG_LOADING))
  291. goto skip_scr;
  292. /* Resume phy. This is the old SATA resume sequence */
  293. svia_scr_write(link, SCR_CONTROL, 0x300);
  294. svia_scr_read(link, SCR_CONTROL, &scontrol); /* flush */
  295. /* wait for phy to become ready, if necessary */
  296. do {
  297. ata_msleep(link->ap, 200);
  298. svia_scr_read(link, SCR_STATUS, &sstatus);
  299. if ((sstatus & 0xf) != 1)
  300. break;
  301. } while (time_before(jiffies, timeout));
  302. /* open code sata_print_link_status() */
  303. svia_scr_read(link, SCR_STATUS, &sstatus);
  304. svia_scr_read(link, SCR_CONTROL, &scontrol);
  305. online = (sstatus & 0xf) == 0x3;
  306. ata_port_info(ap,
  307. "SATA link %s 1.5 Gbps (SStatus %X SControl %X)\n",
  308. online ? "up" : "down", sstatus, scontrol);
  309. /* SStatus is read one more time */
  310. svia_scr_read(link, SCR_STATUS, &sstatus);
  311. if (!online) {
  312. /* tell EH to bail */
  313. ehc->i.action &= ~ATA_EH_RESET;
  314. return 0;
  315. }
  316. skip_scr:
  317. /* wait for !BSY */
  318. ata_sff_wait_ready(link, deadline);
  319. return 0;
  320. }
  321. static void vt6420_bmdma_start(struct ata_queued_cmd *qc)
  322. {
  323. struct ata_port *ap = qc->ap;
  324. if ((qc->tf.command == ATA_CMD_PACKET) &&
  325. (qc->scsicmd->sc_data_direction == DMA_TO_DEVICE)) {
  326. /* Prevents corruption on some ATAPI burners */
  327. ata_sff_pause(ap);
  328. }
  329. ata_bmdma_start(qc);
  330. }
  331. static int vt6421_pata_cable_detect(struct ata_port *ap)
  332. {
  333. struct pci_dev *pdev = to_pci_dev(ap->host->dev);
  334. u8 tmp;
  335. pci_read_config_byte(pdev, PATA_UDMA_TIMING, &tmp);
  336. if (tmp & 0x10)
  337. return ATA_CBL_PATA40;
  338. return ATA_CBL_PATA80;
  339. }
  340. static void vt6421_set_pio_mode(struct ata_port *ap, struct ata_device *adev)
  341. {
  342. struct pci_dev *pdev = to_pci_dev(ap->host->dev);
  343. static const u8 pio_bits[] = { 0xA8, 0x65, 0x65, 0x31, 0x20 };
  344. pci_write_config_byte(pdev, PATA_PIO_TIMING - adev->devno,
  345. pio_bits[adev->pio_mode - XFER_PIO_0]);
  346. }
  347. static void vt6421_set_dma_mode(struct ata_port *ap, struct ata_device *adev)
  348. {
  349. struct pci_dev *pdev = to_pci_dev(ap->host->dev);
  350. static const u8 udma_bits[] = { 0xEE, 0xE8, 0xE6, 0xE4, 0xE2, 0xE1, 0xE0, 0xE0 };
  351. pci_write_config_byte(pdev, PATA_UDMA_TIMING - adev->devno,
  352. udma_bits[adev->dma_mode - XFER_UDMA_0]);
  353. }
  354. static const unsigned int svia_bar_sizes[] = {
  355. 8, 4, 8, 4, 16, 256
  356. };
  357. static const unsigned int vt6421_bar_sizes[] = {
  358. 16, 16, 16, 16, 32, 128
  359. };
  360. static void __iomem *svia_scr_addr(void __iomem *addr, unsigned int port)
  361. {
  362. return addr + (port * 128);
  363. }
  364. static void __iomem *vt6421_scr_addr(void __iomem *addr, unsigned int port)
  365. {
  366. return addr + (port * 64);
  367. }
  368. static void vt6421_init_addrs(struct ata_port *ap)
  369. {
  370. void __iomem * const * iomap = ap->host->iomap;
  371. void __iomem *reg_addr = iomap[ap->port_no];
  372. void __iomem *bmdma_addr = iomap[4] + (ap->port_no * 8);
  373. struct ata_ioports *ioaddr = &ap->ioaddr;
  374. ioaddr->cmd_addr = reg_addr;
  375. ioaddr->altstatus_addr =
  376. ioaddr->ctl_addr = (void __iomem *)
  377. ((unsigned long)(reg_addr + 8) | ATA_PCI_CTL_OFS);
  378. ioaddr->bmdma_addr = bmdma_addr;
  379. ioaddr->scr_addr = vt6421_scr_addr(iomap[5], ap->port_no);
  380. ata_sff_std_ports(ioaddr);
  381. ata_port_pbar_desc(ap, ap->port_no, -1, "port");
  382. ata_port_pbar_desc(ap, 4, ap->port_no * 8, "bmdma");
  383. }
  384. static int vt6420_prepare_host(struct pci_dev *pdev, struct ata_host **r_host)
  385. {
  386. const struct ata_port_info *ppi[] = { &vt6420_port_info, NULL };
  387. struct ata_host *host;
  388. int rc;
  389. if (vt6420_hotplug) {
  390. ppi[0]->port_ops->scr_read = svia_scr_read;
  391. ppi[0]->port_ops->scr_write = svia_scr_write;
  392. }
  393. rc = ata_pci_bmdma_prepare_host(pdev, ppi, &host);
  394. if (rc)
  395. return rc;
  396. *r_host = host;
  397. rc = pcim_iomap_regions(pdev, 1 << 5, DRV_NAME);
  398. if (rc) {
  399. dev_err(&pdev->dev, "failed to iomap PCI BAR 5\n");
  400. return rc;
  401. }
  402. host->ports[0]->ioaddr.scr_addr = svia_scr_addr(host->iomap[5], 0);
  403. host->ports[1]->ioaddr.scr_addr = svia_scr_addr(host->iomap[5], 1);
  404. return 0;
  405. }
  406. static int vt6421_prepare_host(struct pci_dev *pdev, struct ata_host **r_host)
  407. {
  408. const struct ata_port_info *ppi[] =
  409. { &vt6421_sport_info, &vt6421_sport_info, &vt6421_pport_info };
  410. struct ata_host *host;
  411. int i, rc;
  412. *r_host = host = ata_host_alloc_pinfo(&pdev->dev, ppi, ARRAY_SIZE(ppi));
  413. if (!host) {
  414. dev_err(&pdev->dev, "failed to allocate host\n");
  415. return -ENOMEM;
  416. }
  417. rc = pcim_iomap_regions(pdev, 0x3f, DRV_NAME);
  418. if (rc) {
  419. dev_err(&pdev->dev, "failed to request/iomap PCI BARs (errno=%d)\n",
  420. rc);
  421. return rc;
  422. }
  423. host->iomap = pcim_iomap_table(pdev);
  424. for (i = 0; i < host->n_ports; i++)
  425. vt6421_init_addrs(host->ports[i]);
  426. return dma_set_mask_and_coherent(&pdev->dev, ATA_DMA_MASK);
  427. }
  428. static int vt8251_prepare_host(struct pci_dev *pdev, struct ata_host **r_host)
  429. {
  430. const struct ata_port_info *ppi[] = { &vt8251_port_info, NULL };
  431. struct ata_host *host;
  432. int i, rc;
  433. rc = ata_pci_bmdma_prepare_host(pdev, ppi, &host);
  434. if (rc)
  435. return rc;
  436. *r_host = host;
  437. rc = pcim_iomap_regions(pdev, 1 << 5, DRV_NAME);
  438. if (rc) {
  439. dev_err(&pdev->dev, "failed to iomap PCI BAR 5\n");
  440. return rc;
  441. }
  442. /* 8251 hosts four sata ports as M/S of the two channels */
  443. for (i = 0; i < host->n_ports; i++)
  444. ata_slave_link_init(host->ports[i]);
  445. return 0;
  446. }
  447. static void svia_wd_fix(struct pci_dev *pdev)
  448. {
  449. u8 tmp8;
  450. pci_read_config_byte(pdev, 0x52, &tmp8);
  451. pci_write_config_byte(pdev, 0x52, tmp8 | BIT(2));
  452. }
  453. static irqreturn_t vt642x_interrupt(int irq, void *dev_instance)
  454. {
  455. struct ata_host *host = dev_instance;
  456. irqreturn_t rc = ata_bmdma_interrupt(irq, dev_instance);
  457. /* if the IRQ was not handled, it might be a hotplug IRQ */
  458. if (rc != IRQ_HANDLED) {
  459. u32 serror;
  460. unsigned long flags;
  461. spin_lock_irqsave(&host->lock, flags);
  462. /* check for hotplug on port 0 */
  463. svia_scr_read(&host->ports[0]->link, SCR_ERROR, &serror);
  464. if (serror & SERR_PHYRDY_CHG) {
  465. ata_ehi_hotplugged(&host->ports[0]->link.eh_info);
  466. ata_port_freeze(host->ports[0]);
  467. rc = IRQ_HANDLED;
  468. }
  469. /* check for hotplug on port 1 */
  470. svia_scr_read(&host->ports[1]->link, SCR_ERROR, &serror);
  471. if (serror & SERR_PHYRDY_CHG) {
  472. ata_ehi_hotplugged(&host->ports[1]->link.eh_info);
  473. ata_port_freeze(host->ports[1]);
  474. rc = IRQ_HANDLED;
  475. }
  476. spin_unlock_irqrestore(&host->lock, flags);
  477. }
  478. return rc;
  479. }
  480. static void vt6421_error_handler(struct ata_port *ap)
  481. {
  482. struct svia_priv *hpriv = ap->host->private_data;
  483. struct pci_dev *pdev = to_pci_dev(ap->host->dev);
  484. u32 serror;
  485. /* see svia_configure() for description */
  486. if (!hpriv->wd_workaround) {
  487. svia_scr_read(&ap->link, SCR_ERROR, &serror);
  488. if (serror == 0x1000500) {
  489. ata_port_warn(ap, "Incompatible drive: enabling workaround. This slows down transfer rate to ~60 MB/s");
  490. svia_wd_fix(pdev);
  491. hpriv->wd_workaround = true;
  492. ap->link.eh_context.i.flags |= ATA_EHI_QUIET;
  493. }
  494. }
  495. ata_sff_error_handler(ap);
  496. }
  497. static void svia_configure(struct pci_dev *pdev, int board_id,
  498. struct svia_priv *hpriv)
  499. {
  500. u8 tmp8;
  501. pci_read_config_byte(pdev, PCI_INTERRUPT_LINE, &tmp8);
  502. dev_info(&pdev->dev, "routed to hard irq line %d\n",
  503. (int) (tmp8 & 0xf0) == 0xf0 ? 0 : tmp8 & 0x0f);
  504. /* make sure SATA channels are enabled */
  505. pci_read_config_byte(pdev, SATA_CHAN_ENAB, &tmp8);
  506. if ((tmp8 & ALL_PORTS) != ALL_PORTS) {
  507. dev_dbg(&pdev->dev, "enabling SATA channels (0x%x)\n",
  508. (int)tmp8);
  509. tmp8 |= ALL_PORTS;
  510. pci_write_config_byte(pdev, SATA_CHAN_ENAB, tmp8);
  511. }
  512. /* make sure interrupts for each channel sent to us */
  513. pci_read_config_byte(pdev, SATA_INT_GATE, &tmp8);
  514. if ((tmp8 & ALL_PORTS) != ALL_PORTS) {
  515. dev_dbg(&pdev->dev, "enabling SATA channel interrupts (0x%x)\n",
  516. (int) tmp8);
  517. tmp8 |= ALL_PORTS;
  518. pci_write_config_byte(pdev, SATA_INT_GATE, tmp8);
  519. }
  520. /* make sure native mode is enabled */
  521. pci_read_config_byte(pdev, SATA_NATIVE_MODE, &tmp8);
  522. if ((tmp8 & NATIVE_MODE_ALL) != NATIVE_MODE_ALL) {
  523. dev_dbg(&pdev->dev,
  524. "enabling SATA channel native mode (0x%x)\n",
  525. (int) tmp8);
  526. tmp8 |= NATIVE_MODE_ALL;
  527. pci_write_config_byte(pdev, SATA_NATIVE_MODE, tmp8);
  528. }
  529. if ((board_id == vt6420 && vt6420_hotplug) || board_id == vt6421) {
  530. /* enable IRQ on hotplug */
  531. pci_read_config_byte(pdev, SVIA_MISC_3, &tmp8);
  532. if ((tmp8 & SATA_HOTPLUG) != SATA_HOTPLUG) {
  533. dev_dbg(&pdev->dev,
  534. "enabling SATA hotplug (0x%x)\n",
  535. (int) tmp8);
  536. tmp8 |= SATA_HOTPLUG;
  537. pci_write_config_byte(pdev, SVIA_MISC_3, tmp8);
  538. }
  539. }
  540. /*
  541. * vt6420/1 has problems talking to some drives. The following
  542. * is the fix from Joseph Chan <JosephChan@via.com.tw>.
  543. *
  544. * When host issues HOLD, device may send up to 20DW of data
  545. * before acknowledging it with HOLDA and the host should be
  546. * able to buffer them in FIFO. Unfortunately, some WD drives
  547. * send up to 40DW before acknowledging HOLD and, in the
  548. * default configuration, this ends up overflowing vt6421's
  549. * FIFO, making the controller abort the transaction with
  550. * R_ERR.
  551. *
  552. * Rx52[2] is the internal 128DW FIFO Flow control watermark
  553. * adjusting mechanism enable bit and the default value 0
  554. * means host will issue HOLD to device when the left FIFO
  555. * size goes below 32DW. Setting it to 1 makes the watermark
  556. * 64DW.
  557. *
  558. * https://bugzilla.kernel.org/show_bug.cgi?id=15173
  559. * http://article.gmane.org/gmane.linux.ide/46352
  560. * http://thread.gmane.org/gmane.linux.kernel/1062139
  561. *
  562. * As the fix slows down data transfer, apply it only if the error
  563. * actually appears - see vt6421_error_handler()
  564. * Apply the fix always on vt6420 as we don't know if SCR_ERROR can be
  565. * read safely.
  566. */
  567. if (board_id == vt6420) {
  568. svia_wd_fix(pdev);
  569. hpriv->wd_workaround = true;
  570. }
  571. }
  572. static int svia_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
  573. {
  574. unsigned int i;
  575. int rc;
  576. struct ata_host *host = NULL;
  577. int board_id = (int) ent->driver_data;
  578. const unsigned *bar_sizes;
  579. struct svia_priv *hpriv;
  580. ata_print_version_once(&pdev->dev, DRV_VERSION);
  581. rc = pcim_enable_device(pdev);
  582. if (rc)
  583. return rc;
  584. if (board_id == vt6421)
  585. bar_sizes = &vt6421_bar_sizes[0];
  586. else
  587. bar_sizes = &svia_bar_sizes[0];
  588. for (i = 0; i < ARRAY_SIZE(svia_bar_sizes); i++)
  589. if ((pci_resource_start(pdev, i) == 0) ||
  590. (pci_resource_len(pdev, i) < bar_sizes[i])) {
  591. dev_err(&pdev->dev,
  592. "invalid PCI BAR %u (sz 0x%llx, val 0x%llx)\n",
  593. i,
  594. (unsigned long long)pci_resource_start(pdev, i),
  595. (unsigned long long)pci_resource_len(pdev, i));
  596. return -ENODEV;
  597. }
  598. switch (board_id) {
  599. case vt6420:
  600. rc = vt6420_prepare_host(pdev, &host);
  601. break;
  602. case vt6421:
  603. rc = vt6421_prepare_host(pdev, &host);
  604. break;
  605. case vt8251:
  606. rc = vt8251_prepare_host(pdev, &host);
  607. break;
  608. default:
  609. rc = -EINVAL;
  610. }
  611. if (rc)
  612. return rc;
  613. hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
  614. if (!hpriv)
  615. return -ENOMEM;
  616. host->private_data = hpriv;
  617. svia_configure(pdev, board_id, hpriv);
  618. pci_set_master(pdev);
  619. if ((board_id == vt6420 && vt6420_hotplug) || board_id == vt6421)
  620. return ata_host_activate(host, pdev->irq, vt642x_interrupt,
  621. IRQF_SHARED, &svia_sht);
  622. else
  623. return ata_host_activate(host, pdev->irq, ata_bmdma_interrupt,
  624. IRQF_SHARED, &svia_sht);
  625. }
  626. #ifdef CONFIG_PM_SLEEP
  627. static int svia_pci_device_resume(struct pci_dev *pdev)
  628. {
  629. struct ata_host *host = pci_get_drvdata(pdev);
  630. struct svia_priv *hpriv = host->private_data;
  631. int rc;
  632. rc = ata_pci_device_do_resume(pdev);
  633. if (rc)
  634. return rc;
  635. if (hpriv->wd_workaround)
  636. svia_wd_fix(pdev);
  637. ata_host_resume(host);
  638. return 0;
  639. }
  640. #endif
  641. module_pci_driver(svia_pci_driver);