sata_qstor.c 16 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * sata_qstor.c - Pacific Digital Corporation QStor SATA
  4. *
  5. * Maintained by: Mark Lord <mlord@pobox.com>
  6. *
  7. * Copyright 2005 Pacific Digital Corporation.
  8. * (OSL/GPL code release authorized by Jalil Fadavi).
  9. *
  10. * libata documentation is available via 'make {ps|pdf}docs',
  11. * as Documentation/driver-api/libata.rst
  12. */
  13. #include <linux/kernel.h>
  14. #include <linux/module.h>
  15. #include <linux/gfp.h>
  16. #include <linux/pci.h>
  17. #include <linux/blkdev.h>
  18. #include <linux/delay.h>
  19. #include <linux/interrupt.h>
  20. #include <linux/device.h>
  21. #include <scsi/scsi_host.h>
  22. #include <linux/libata.h>
  23. #define DRV_NAME "sata_qstor"
  24. #define DRV_VERSION "0.09"
  25. enum {
  26. QS_MMIO_BAR = 4,
  27. QS_PORTS = 4,
  28. QS_MAX_PRD = LIBATA_MAX_PRD,
  29. QS_CPB_ORDER = 6,
  30. QS_CPB_BYTES = (1 << QS_CPB_ORDER),
  31. QS_PRD_BYTES = QS_MAX_PRD * 16,
  32. QS_PKT_BYTES = QS_CPB_BYTES + QS_PRD_BYTES,
  33. /* global register offsets */
  34. QS_HCF_CNFG3 = 0x0003, /* host configuration offset */
  35. QS_HID_HPHY = 0x0004, /* host physical interface info */
  36. QS_HCT_CTRL = 0x00e4, /* global interrupt mask offset */
  37. QS_HST_SFF = 0x0100, /* host status fifo offset */
  38. QS_HVS_SERD3 = 0x0393, /* PHY enable offset */
  39. /* global control bits */
  40. QS_HPHY_64BIT = (1 << 1), /* 64-bit bus detected */
  41. QS_CNFG3_GSRST = 0x01, /* global chip reset */
  42. QS_SERD3_PHY_ENA = 0xf0, /* PHY detection ENAble*/
  43. /* per-channel register offsets */
  44. QS_CCF_CPBA = 0x0710, /* chan CPB base address */
  45. QS_CCF_CSEP = 0x0718, /* chan CPB separation factor */
  46. QS_CFC_HUFT = 0x0800, /* host upstream fifo threshold */
  47. QS_CFC_HDFT = 0x0804, /* host downstream fifo threshold */
  48. QS_CFC_DUFT = 0x0808, /* dev upstream fifo threshold */
  49. QS_CFC_DDFT = 0x080c, /* dev downstream fifo threshold */
  50. QS_CCT_CTR0 = 0x0900, /* chan control-0 offset */
  51. QS_CCT_CTR1 = 0x0901, /* chan control-1 offset */
  52. QS_CCT_CFF = 0x0a00, /* chan command fifo offset */
  53. /* channel control bits */
  54. QS_CTR0_REG = (1 << 1), /* register mode (vs. pkt mode) */
  55. QS_CTR0_CLER = (1 << 2), /* clear channel errors */
  56. QS_CTR1_RDEV = (1 << 1), /* sata phy/comms reset */
  57. QS_CTR1_RCHN = (1 << 4), /* reset channel logic */
  58. QS_CCF_RUN_PKT = 0x107, /* RUN a new dma PKT */
  59. /* pkt sub-field headers */
  60. QS_HCB_HDR = 0x01, /* Host Control Block header */
  61. QS_DCB_HDR = 0x02, /* Device Control Block header */
  62. /* pkt HCB flag bits */
  63. QS_HF_DIRO = (1 << 0), /* data DIRection Out */
  64. QS_HF_DAT = (1 << 3), /* DATa pkt */
  65. QS_HF_IEN = (1 << 4), /* Interrupt ENable */
  66. QS_HF_VLD = (1 << 5), /* VaLiD pkt */
  67. /* pkt DCB flag bits */
  68. QS_DF_PORD = (1 << 2), /* Pio OR Dma */
  69. QS_DF_ELBA = (1 << 3), /* Extended LBA (lba48) */
  70. /* PCI device IDs */
  71. board_2068_idx = 0, /* QStor 4-port SATA/RAID */
  72. };
  73. enum {
  74. QS_DMA_BOUNDARY = ~0UL
  75. };
  76. typedef enum { qs_state_mmio, qs_state_pkt } qs_state_t;
  77. struct qs_port_priv {
  78. u8 *pkt;
  79. dma_addr_t pkt_dma;
  80. qs_state_t state;
  81. };
  82. static int qs_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val);
  83. static int qs_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val);
  84. static int qs_ata_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
  85. static int qs_port_start(struct ata_port *ap);
  86. static void qs_host_stop(struct ata_host *host);
  87. static enum ata_completion_errors qs_qc_prep(struct ata_queued_cmd *qc);
  88. static unsigned int qs_qc_issue(struct ata_queued_cmd *qc);
  89. static int qs_check_atapi_dma(struct ata_queued_cmd *qc);
  90. static void qs_freeze(struct ata_port *ap);
  91. static void qs_thaw(struct ata_port *ap);
  92. static int qs_prereset(struct ata_link *link, unsigned long deadline);
  93. static void qs_error_handler(struct ata_port *ap);
  94. static struct scsi_host_template qs_ata_sht = {
  95. ATA_BASE_SHT(DRV_NAME),
  96. .sg_tablesize = QS_MAX_PRD,
  97. .dma_boundary = QS_DMA_BOUNDARY,
  98. };
  99. static struct ata_port_operations qs_ata_ops = {
  100. .inherits = &ata_sff_port_ops,
  101. .check_atapi_dma = qs_check_atapi_dma,
  102. .qc_prep = qs_qc_prep,
  103. .qc_issue = qs_qc_issue,
  104. .freeze = qs_freeze,
  105. .thaw = qs_thaw,
  106. .prereset = qs_prereset,
  107. .softreset = ATA_OP_NULL,
  108. .error_handler = qs_error_handler,
  109. .lost_interrupt = ATA_OP_NULL,
  110. .scr_read = qs_scr_read,
  111. .scr_write = qs_scr_write,
  112. .port_start = qs_port_start,
  113. .host_stop = qs_host_stop,
  114. };
  115. static const struct ata_port_info qs_port_info[] = {
  116. /* board_2068_idx */
  117. {
  118. .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_POLLING,
  119. .pio_mask = ATA_PIO4_ONLY,
  120. .udma_mask = ATA_UDMA6,
  121. .port_ops = &qs_ata_ops,
  122. },
  123. };
  124. static const struct pci_device_id qs_ata_pci_tbl[] = {
  125. { PCI_VDEVICE(PDC, 0x2068), board_2068_idx },
  126. { } /* terminate list */
  127. };
  128. static struct pci_driver qs_ata_pci_driver = {
  129. .name = DRV_NAME,
  130. .id_table = qs_ata_pci_tbl,
  131. .probe = qs_ata_init_one,
  132. .remove = ata_pci_remove_one,
  133. };
  134. static void __iomem *qs_mmio_base(struct ata_host *host)
  135. {
  136. return host->iomap[QS_MMIO_BAR];
  137. }
  138. static int qs_check_atapi_dma(struct ata_queued_cmd *qc)
  139. {
  140. return 1; /* ATAPI DMA not supported */
  141. }
  142. static inline void qs_enter_reg_mode(struct ata_port *ap)
  143. {
  144. u8 __iomem *chan = qs_mmio_base(ap->host) + (ap->port_no * 0x4000);
  145. struct qs_port_priv *pp = ap->private_data;
  146. pp->state = qs_state_mmio;
  147. writeb(QS_CTR0_REG, chan + QS_CCT_CTR0);
  148. readb(chan + QS_CCT_CTR0); /* flush */
  149. }
  150. static inline void qs_reset_channel_logic(struct ata_port *ap)
  151. {
  152. u8 __iomem *chan = qs_mmio_base(ap->host) + (ap->port_no * 0x4000);
  153. writeb(QS_CTR1_RCHN, chan + QS_CCT_CTR1);
  154. readb(chan + QS_CCT_CTR0); /* flush */
  155. qs_enter_reg_mode(ap);
  156. }
  157. static void qs_freeze(struct ata_port *ap)
  158. {
  159. u8 __iomem *mmio_base = qs_mmio_base(ap->host);
  160. writeb(0, mmio_base + QS_HCT_CTRL); /* disable host interrupts */
  161. qs_enter_reg_mode(ap);
  162. }
  163. static void qs_thaw(struct ata_port *ap)
  164. {
  165. u8 __iomem *mmio_base = qs_mmio_base(ap->host);
  166. qs_enter_reg_mode(ap);
  167. writeb(1, mmio_base + QS_HCT_CTRL); /* enable host interrupts */
  168. }
  169. static int qs_prereset(struct ata_link *link, unsigned long deadline)
  170. {
  171. struct ata_port *ap = link->ap;
  172. qs_reset_channel_logic(ap);
  173. return ata_sff_prereset(link, deadline);
  174. }
  175. static int qs_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val)
  176. {
  177. if (sc_reg > SCR_CONTROL)
  178. return -EINVAL;
  179. *val = readl(link->ap->ioaddr.scr_addr + (sc_reg * 8));
  180. return 0;
  181. }
  182. static void qs_error_handler(struct ata_port *ap)
  183. {
  184. qs_enter_reg_mode(ap);
  185. ata_sff_error_handler(ap);
  186. }
  187. static int qs_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val)
  188. {
  189. if (sc_reg > SCR_CONTROL)
  190. return -EINVAL;
  191. writel(val, link->ap->ioaddr.scr_addr + (sc_reg * 8));
  192. return 0;
  193. }
  194. static unsigned int qs_fill_sg(struct ata_queued_cmd *qc)
  195. {
  196. struct scatterlist *sg;
  197. struct ata_port *ap = qc->ap;
  198. struct qs_port_priv *pp = ap->private_data;
  199. u8 *prd = pp->pkt + QS_CPB_BYTES;
  200. unsigned int si;
  201. for_each_sg(qc->sg, sg, qc->n_elem, si) {
  202. u64 addr;
  203. u32 len;
  204. addr = sg_dma_address(sg);
  205. *(__le64 *)prd = cpu_to_le64(addr);
  206. prd += sizeof(u64);
  207. len = sg_dma_len(sg);
  208. *(__le32 *)prd = cpu_to_le32(len);
  209. prd += sizeof(u64);
  210. VPRINTK("PRD[%u] = (0x%llX, 0x%X)\n", si,
  211. (unsigned long long)addr, len);
  212. }
  213. return si;
  214. }
  215. static enum ata_completion_errors qs_qc_prep(struct ata_queued_cmd *qc)
  216. {
  217. struct qs_port_priv *pp = qc->ap->private_data;
  218. u8 dflags = QS_DF_PORD, *buf = pp->pkt;
  219. u8 hflags = QS_HF_DAT | QS_HF_IEN | QS_HF_VLD;
  220. u64 addr;
  221. unsigned int nelem;
  222. VPRINTK("ENTER\n");
  223. qs_enter_reg_mode(qc->ap);
  224. if (qc->tf.protocol != ATA_PROT_DMA)
  225. return AC_ERR_OK;
  226. nelem = qs_fill_sg(qc);
  227. if ((qc->tf.flags & ATA_TFLAG_WRITE))
  228. hflags |= QS_HF_DIRO;
  229. if ((qc->tf.flags & ATA_TFLAG_LBA48))
  230. dflags |= QS_DF_ELBA;
  231. /* host control block (HCB) */
  232. buf[ 0] = QS_HCB_HDR;
  233. buf[ 1] = hflags;
  234. *(__le32 *)(&buf[ 4]) = cpu_to_le32(qc->nbytes);
  235. *(__le32 *)(&buf[ 8]) = cpu_to_le32(nelem);
  236. addr = ((u64)pp->pkt_dma) + QS_CPB_BYTES;
  237. *(__le64 *)(&buf[16]) = cpu_to_le64(addr);
  238. /* device control block (DCB) */
  239. buf[24] = QS_DCB_HDR;
  240. buf[28] = dflags;
  241. /* frame information structure (FIS) */
  242. ata_tf_to_fis(&qc->tf, 0, 1, &buf[32]);
  243. return AC_ERR_OK;
  244. }
  245. static inline void qs_packet_start(struct ata_queued_cmd *qc)
  246. {
  247. struct ata_port *ap = qc->ap;
  248. u8 __iomem *chan = qs_mmio_base(ap->host) + (ap->port_no * 0x4000);
  249. VPRINTK("ENTER, ap %p\n", ap);
  250. writeb(QS_CTR0_CLER, chan + QS_CCT_CTR0);
  251. wmb(); /* flush PRDs and pkt to memory */
  252. writel(QS_CCF_RUN_PKT, chan + QS_CCT_CFF);
  253. readl(chan + QS_CCT_CFF); /* flush */
  254. }
  255. static unsigned int qs_qc_issue(struct ata_queued_cmd *qc)
  256. {
  257. struct qs_port_priv *pp = qc->ap->private_data;
  258. switch (qc->tf.protocol) {
  259. case ATA_PROT_DMA:
  260. pp->state = qs_state_pkt;
  261. qs_packet_start(qc);
  262. return 0;
  263. case ATAPI_PROT_DMA:
  264. BUG();
  265. break;
  266. default:
  267. break;
  268. }
  269. pp->state = qs_state_mmio;
  270. return ata_sff_qc_issue(qc);
  271. }
  272. static void qs_do_or_die(struct ata_queued_cmd *qc, u8 status)
  273. {
  274. qc->err_mask |= ac_err_mask(status);
  275. if (!qc->err_mask) {
  276. ata_qc_complete(qc);
  277. } else {
  278. struct ata_port *ap = qc->ap;
  279. struct ata_eh_info *ehi = &ap->link.eh_info;
  280. ata_ehi_clear_desc(ehi);
  281. ata_ehi_push_desc(ehi, "status 0x%02X", status);
  282. if (qc->err_mask == AC_ERR_DEV)
  283. ata_port_abort(ap);
  284. else
  285. ata_port_freeze(ap);
  286. }
  287. }
  288. static inline unsigned int qs_intr_pkt(struct ata_host *host)
  289. {
  290. unsigned int handled = 0;
  291. u8 sFFE;
  292. u8 __iomem *mmio_base = qs_mmio_base(host);
  293. do {
  294. u32 sff0 = readl(mmio_base + QS_HST_SFF);
  295. u32 sff1 = readl(mmio_base + QS_HST_SFF + 4);
  296. u8 sEVLD = (sff1 >> 30) & 0x01; /* valid flag */
  297. sFFE = sff1 >> 31; /* empty flag */
  298. if (sEVLD) {
  299. u8 sDST = sff0 >> 16; /* dev status */
  300. u8 sHST = sff1 & 0x3f; /* host status */
  301. unsigned int port_no = (sff1 >> 8) & 0x03;
  302. struct ata_port *ap = host->ports[port_no];
  303. struct qs_port_priv *pp = ap->private_data;
  304. struct ata_queued_cmd *qc;
  305. DPRINTK("SFF=%08x%08x: sCHAN=%u sHST=%d sDST=%02x\n",
  306. sff1, sff0, port_no, sHST, sDST);
  307. handled = 1;
  308. if (!pp || pp->state != qs_state_pkt)
  309. continue;
  310. qc = ata_qc_from_tag(ap, ap->link.active_tag);
  311. if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING))) {
  312. switch (sHST) {
  313. case 0: /* successful CPB */
  314. case 3: /* device error */
  315. qs_enter_reg_mode(qc->ap);
  316. qs_do_or_die(qc, sDST);
  317. break;
  318. default:
  319. break;
  320. }
  321. }
  322. }
  323. } while (!sFFE);
  324. return handled;
  325. }
  326. static inline unsigned int qs_intr_mmio(struct ata_host *host)
  327. {
  328. unsigned int handled = 0, port_no;
  329. for (port_no = 0; port_no < host->n_ports; ++port_no) {
  330. struct ata_port *ap = host->ports[port_no];
  331. struct qs_port_priv *pp = ap->private_data;
  332. struct ata_queued_cmd *qc;
  333. qc = ata_qc_from_tag(ap, ap->link.active_tag);
  334. if (!qc) {
  335. /*
  336. * The qstor hardware generates spurious
  337. * interrupts from time to time when switching
  338. * in and out of packet mode. There's no
  339. * obvious way to know if we're here now due
  340. * to that, so just ack the irq and pretend we
  341. * knew it was ours.. (ugh). This does not
  342. * affect packet mode.
  343. */
  344. ata_sff_check_status(ap);
  345. handled = 1;
  346. continue;
  347. }
  348. if (!pp || pp->state != qs_state_mmio)
  349. continue;
  350. if (!(qc->tf.flags & ATA_TFLAG_POLLING))
  351. handled |= ata_sff_port_intr(ap, qc);
  352. }
  353. return handled;
  354. }
  355. static irqreturn_t qs_intr(int irq, void *dev_instance)
  356. {
  357. struct ata_host *host = dev_instance;
  358. unsigned int handled = 0;
  359. unsigned long flags;
  360. VPRINTK("ENTER\n");
  361. spin_lock_irqsave(&host->lock, flags);
  362. handled = qs_intr_pkt(host) | qs_intr_mmio(host);
  363. spin_unlock_irqrestore(&host->lock, flags);
  364. VPRINTK("EXIT\n");
  365. return IRQ_RETVAL(handled);
  366. }
  367. static void qs_ata_setup_port(struct ata_ioports *port, void __iomem *base)
  368. {
  369. port->cmd_addr =
  370. port->data_addr = base + 0x400;
  371. port->error_addr =
  372. port->feature_addr = base + 0x408; /* hob_feature = 0x409 */
  373. port->nsect_addr = base + 0x410; /* hob_nsect = 0x411 */
  374. port->lbal_addr = base + 0x418; /* hob_lbal = 0x419 */
  375. port->lbam_addr = base + 0x420; /* hob_lbam = 0x421 */
  376. port->lbah_addr = base + 0x428; /* hob_lbah = 0x429 */
  377. port->device_addr = base + 0x430;
  378. port->status_addr =
  379. port->command_addr = base + 0x438;
  380. port->altstatus_addr =
  381. port->ctl_addr = base + 0x440;
  382. port->scr_addr = base + 0xc00;
  383. }
  384. static int qs_port_start(struct ata_port *ap)
  385. {
  386. struct device *dev = ap->host->dev;
  387. struct qs_port_priv *pp;
  388. void __iomem *mmio_base = qs_mmio_base(ap->host);
  389. void __iomem *chan = mmio_base + (ap->port_no * 0x4000);
  390. u64 addr;
  391. pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
  392. if (!pp)
  393. return -ENOMEM;
  394. pp->pkt = dmam_alloc_coherent(dev, QS_PKT_BYTES, &pp->pkt_dma,
  395. GFP_KERNEL);
  396. if (!pp->pkt)
  397. return -ENOMEM;
  398. ap->private_data = pp;
  399. qs_enter_reg_mode(ap);
  400. addr = (u64)pp->pkt_dma;
  401. writel((u32) addr, chan + QS_CCF_CPBA);
  402. writel((u32)(addr >> 32), chan + QS_CCF_CPBA + 4);
  403. return 0;
  404. }
  405. static void qs_host_stop(struct ata_host *host)
  406. {
  407. void __iomem *mmio_base = qs_mmio_base(host);
  408. writeb(0, mmio_base + QS_HCT_CTRL); /* disable host interrupts */
  409. writeb(QS_CNFG3_GSRST, mmio_base + QS_HCF_CNFG3); /* global reset */
  410. }
  411. static void qs_host_init(struct ata_host *host, unsigned int chip_id)
  412. {
  413. void __iomem *mmio_base = host->iomap[QS_MMIO_BAR];
  414. unsigned int port_no;
  415. writeb(0, mmio_base + QS_HCT_CTRL); /* disable host interrupts */
  416. writeb(QS_CNFG3_GSRST, mmio_base + QS_HCF_CNFG3); /* global reset */
  417. /* reset each channel in turn */
  418. for (port_no = 0; port_no < host->n_ports; ++port_no) {
  419. u8 __iomem *chan = mmio_base + (port_no * 0x4000);
  420. writeb(QS_CTR1_RDEV|QS_CTR1_RCHN, chan + QS_CCT_CTR1);
  421. writeb(QS_CTR0_REG, chan + QS_CCT_CTR0);
  422. readb(chan + QS_CCT_CTR0); /* flush */
  423. }
  424. writeb(QS_SERD3_PHY_ENA, mmio_base + QS_HVS_SERD3); /* enable phy */
  425. for (port_no = 0; port_no < host->n_ports; ++port_no) {
  426. u8 __iomem *chan = mmio_base + (port_no * 0x4000);
  427. /* set FIFO depths to same settings as Windows driver */
  428. writew(32, chan + QS_CFC_HUFT);
  429. writew(32, chan + QS_CFC_HDFT);
  430. writew(10, chan + QS_CFC_DUFT);
  431. writew( 8, chan + QS_CFC_DDFT);
  432. /* set CPB size in bytes, as a power of two */
  433. writeb(QS_CPB_ORDER, chan + QS_CCF_CSEP);
  434. }
  435. writeb(1, mmio_base + QS_HCT_CTRL); /* enable host interrupts */
  436. }
  437. /*
  438. * The QStor understands 64-bit buses, and uses 64-bit fields
  439. * for DMA pointers regardless of bus width. We just have to
  440. * make sure our DMA masks are set appropriately for whatever
  441. * bridge lies between us and the QStor, and then the DMA mapping
  442. * code will ensure we only ever "see" appropriate buffer addresses.
  443. * If we're 32-bit limited somewhere, then our 64-bit fields will
  444. * just end up with zeros in the upper 32-bits, without any special
  445. * logic required outside of this routine (below).
  446. */
  447. static int qs_set_dma_masks(struct pci_dev *pdev, void __iomem *mmio_base)
  448. {
  449. u32 bus_info = readl(mmio_base + QS_HID_HPHY);
  450. int dma_bits = (bus_info & QS_HPHY_64BIT) ? 64 : 32;
  451. int rc;
  452. rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(dma_bits));
  453. if (rc)
  454. dev_err(&pdev->dev, "%d-bit DMA enable failed\n", dma_bits);
  455. return rc;
  456. }
  457. static int qs_ata_init_one(struct pci_dev *pdev,
  458. const struct pci_device_id *ent)
  459. {
  460. unsigned int board_idx = (unsigned int) ent->driver_data;
  461. const struct ata_port_info *ppi[] = { &qs_port_info[board_idx], NULL };
  462. struct ata_host *host;
  463. int rc, port_no;
  464. ata_print_version_once(&pdev->dev, DRV_VERSION);
  465. /* alloc host */
  466. host = ata_host_alloc_pinfo(&pdev->dev, ppi, QS_PORTS);
  467. if (!host)
  468. return -ENOMEM;
  469. /* acquire resources and fill host */
  470. rc = pcim_enable_device(pdev);
  471. if (rc)
  472. return rc;
  473. if ((pci_resource_flags(pdev, QS_MMIO_BAR) & IORESOURCE_MEM) == 0)
  474. return -ENODEV;
  475. rc = pcim_iomap_regions(pdev, 1 << QS_MMIO_BAR, DRV_NAME);
  476. if (rc)
  477. return rc;
  478. host->iomap = pcim_iomap_table(pdev);
  479. rc = qs_set_dma_masks(pdev, host->iomap[QS_MMIO_BAR]);
  480. if (rc)
  481. return rc;
  482. for (port_no = 0; port_no < host->n_ports; ++port_no) {
  483. struct ata_port *ap = host->ports[port_no];
  484. unsigned int offset = port_no * 0x4000;
  485. void __iomem *chan = host->iomap[QS_MMIO_BAR] + offset;
  486. qs_ata_setup_port(&ap->ioaddr, chan);
  487. ata_port_pbar_desc(ap, QS_MMIO_BAR, -1, "mmio");
  488. ata_port_pbar_desc(ap, QS_MMIO_BAR, offset, "port");
  489. }
  490. /* initialize adapter */
  491. qs_host_init(host, board_idx);
  492. pci_set_master(pdev);
  493. return ata_host_activate(host, pdev->irq, qs_intr, IRQF_SHARED,
  494. &qs_ata_sht);
  495. }
  496. module_pci_driver(qs_ata_pci_driver);
  497. MODULE_AUTHOR("Mark Lord");
  498. MODULE_DESCRIPTION("Pacific Digital Corporation QStor SATA low-level driver");
  499. MODULE_LICENSE("GPL");
  500. MODULE_DEVICE_TABLE(pci, qs_ata_pci_tbl);
  501. MODULE_VERSION(DRV_VERSION);