sata_highbank.c 17 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Calxeda Highbank AHCI SATA platform driver
  4. * Copyright 2012 Calxeda, Inc.
  5. *
  6. * based on the AHCI SATA platform driver by Jeff Garzik and Anton Vorontsov
  7. */
  8. #include <linux/kernel.h>
  9. #include <linux/gfp.h>
  10. #include <linux/module.h>
  11. #include <linux/types.h>
  12. #include <linux/err.h>
  13. #include <linux/io.h>
  14. #include <linux/spinlock.h>
  15. #include <linux/device.h>
  16. #include <linux/of_device.h>
  17. #include <linux/of_address.h>
  18. #include <linux/platform_device.h>
  19. #include <linux/libata.h>
  20. #include <linux/interrupt.h>
  21. #include <linux/delay.h>
  22. #include <linux/export.h>
  23. #include <linux/gpio/consumer.h>
  24. #include "ahci.h"
  25. #define CPHY_MAP(dev, addr) ((((dev) & 0x1f) << 7) | (((addr) >> 9) & 0x7f))
  26. #define CPHY_ADDR(addr) (((addr) & 0x1ff) << 2)
  27. #define SERDES_CR_CTL 0x80a0
  28. #define SERDES_CR_ADDR 0x80a1
  29. #define SERDES_CR_DATA 0x80a2
  30. #define CR_BUSY 0x0001
  31. #define CR_START 0x0001
  32. #define CR_WR_RDN 0x0002
  33. #define CPHY_TX_INPUT_STS 0x2001
  34. #define CPHY_RX_INPUT_STS 0x2002
  35. #define CPHY_SATA_TX_OVERRIDE 0x8000
  36. #define CPHY_SATA_RX_OVERRIDE 0x4000
  37. #define CPHY_TX_OVERRIDE 0x2004
  38. #define CPHY_RX_OVERRIDE 0x2005
  39. #define SPHY_LANE 0x100
  40. #define SPHY_HALF_RATE 0x0001
  41. #define CPHY_SATA_DPLL_MODE 0x0700
  42. #define CPHY_SATA_DPLL_SHIFT 8
  43. #define CPHY_SATA_DPLL_RESET (1 << 11)
  44. #define CPHY_SATA_TX_ATTEN 0x1c00
  45. #define CPHY_SATA_TX_ATTEN_SHIFT 10
  46. #define CPHY_PHY_COUNT 6
  47. #define CPHY_LANE_COUNT 4
  48. #define CPHY_PORT_COUNT (CPHY_PHY_COUNT * CPHY_LANE_COUNT)
  49. static DEFINE_SPINLOCK(cphy_lock);
  50. /* Each of the 6 phys can have up to 4 sata ports attached to i. Map 0-based
  51. * sata ports to their phys and then to their lanes within the phys
  52. */
  53. struct phy_lane_info {
  54. void __iomem *phy_base;
  55. u8 lane_mapping;
  56. u8 phy_devs;
  57. u8 tx_atten;
  58. };
  59. static struct phy_lane_info port_data[CPHY_PORT_COUNT];
  60. static DEFINE_SPINLOCK(sgpio_lock);
  61. #define SCLOCK 0
  62. #define SLOAD 1
  63. #define SDATA 2
  64. #define SGPIO_PINS 3
  65. #define SGPIO_PORTS 8
  66. struct ecx_plat_data {
  67. u32 n_ports;
  68. /* number of extra clocks that the SGPIO PIC controller expects */
  69. u32 pre_clocks;
  70. u32 post_clocks;
  71. struct gpio_desc *sgpio_gpiod[SGPIO_PINS];
  72. u32 sgpio_pattern;
  73. u32 port_to_sgpio[SGPIO_PORTS];
  74. };
  75. #define SGPIO_SIGNALS 3
  76. #define ECX_ACTIVITY_BITS 0x300000
  77. #define ECX_ACTIVITY_SHIFT 0
  78. #define ECX_LOCATE_BITS 0x80000
  79. #define ECX_LOCATE_SHIFT 1
  80. #define ECX_FAULT_BITS 0x400000
  81. #define ECX_FAULT_SHIFT 2
  82. static inline int sgpio_bit_shift(struct ecx_plat_data *pdata, u32 port,
  83. u32 shift)
  84. {
  85. return 1 << (3 * pdata->port_to_sgpio[port] + shift);
  86. }
  87. static void ecx_parse_sgpio(struct ecx_plat_data *pdata, u32 port, u32 state)
  88. {
  89. if (state & ECX_ACTIVITY_BITS)
  90. pdata->sgpio_pattern |= sgpio_bit_shift(pdata, port,
  91. ECX_ACTIVITY_SHIFT);
  92. else
  93. pdata->sgpio_pattern &= ~sgpio_bit_shift(pdata, port,
  94. ECX_ACTIVITY_SHIFT);
  95. if (state & ECX_LOCATE_BITS)
  96. pdata->sgpio_pattern |= sgpio_bit_shift(pdata, port,
  97. ECX_LOCATE_SHIFT);
  98. else
  99. pdata->sgpio_pattern &= ~sgpio_bit_shift(pdata, port,
  100. ECX_LOCATE_SHIFT);
  101. if (state & ECX_FAULT_BITS)
  102. pdata->sgpio_pattern |= sgpio_bit_shift(pdata, port,
  103. ECX_FAULT_SHIFT);
  104. else
  105. pdata->sgpio_pattern &= ~sgpio_bit_shift(pdata, port,
  106. ECX_FAULT_SHIFT);
  107. }
  108. /*
  109. * Tell the LED controller that the signal has changed by raising the clock
  110. * line for 50 uS and then lowering it for 50 uS.
  111. */
  112. static void ecx_led_cycle_clock(struct ecx_plat_data *pdata)
  113. {
  114. gpiod_set_value(pdata->sgpio_gpiod[SCLOCK], 1);
  115. udelay(50);
  116. gpiod_set_value(pdata->sgpio_gpiod[SCLOCK], 0);
  117. udelay(50);
  118. }
  119. static ssize_t ecx_transmit_led_message(struct ata_port *ap, u32 state,
  120. ssize_t size)
  121. {
  122. struct ahci_host_priv *hpriv = ap->host->private_data;
  123. struct ecx_plat_data *pdata = hpriv->plat_data;
  124. struct ahci_port_priv *pp = ap->private_data;
  125. unsigned long flags;
  126. int pmp, i;
  127. struct ahci_em_priv *emp;
  128. u32 sgpio_out;
  129. /* get the slot number from the message */
  130. pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8;
  131. if (pmp < EM_MAX_SLOTS)
  132. emp = &pp->em_priv[pmp];
  133. else
  134. return -EINVAL;
  135. if (!(hpriv->em_msg_type & EM_MSG_TYPE_LED))
  136. return size;
  137. spin_lock_irqsave(&sgpio_lock, flags);
  138. ecx_parse_sgpio(pdata, ap->port_no, state);
  139. sgpio_out = pdata->sgpio_pattern;
  140. for (i = 0; i < pdata->pre_clocks; i++)
  141. ecx_led_cycle_clock(pdata);
  142. gpiod_set_value(pdata->sgpio_gpiod[SLOAD], 1);
  143. ecx_led_cycle_clock(pdata);
  144. gpiod_set_value(pdata->sgpio_gpiod[SLOAD], 0);
  145. /*
  146. * bit-bang out the SGPIO pattern, by consuming a bit and then
  147. * clocking it out.
  148. */
  149. for (i = 0; i < (SGPIO_SIGNALS * pdata->n_ports); i++) {
  150. gpiod_set_value(pdata->sgpio_gpiod[SDATA], sgpio_out & 1);
  151. sgpio_out >>= 1;
  152. ecx_led_cycle_clock(pdata);
  153. }
  154. for (i = 0; i < pdata->post_clocks; i++)
  155. ecx_led_cycle_clock(pdata);
  156. /* save off new led state for port/slot */
  157. emp->led_state = state;
  158. spin_unlock_irqrestore(&sgpio_lock, flags);
  159. return size;
  160. }
  161. static void highbank_set_em_messages(struct device *dev,
  162. struct ahci_host_priv *hpriv,
  163. struct ata_port_info *pi)
  164. {
  165. struct device_node *np = dev->of_node;
  166. struct ecx_plat_data *pdata = hpriv->plat_data;
  167. int i;
  168. for (i = 0; i < SGPIO_PINS; i++) {
  169. struct gpio_desc *gpiod;
  170. gpiod = devm_gpiod_get_index(dev, "calxeda,sgpio", i,
  171. GPIOD_OUT_HIGH);
  172. if (IS_ERR(gpiod)) {
  173. dev_err(dev, "failed to get GPIO %d\n", i);
  174. continue;
  175. }
  176. gpiod_set_consumer_name(gpiod, "CX SGPIO");
  177. pdata->sgpio_gpiod[i] = gpiod;
  178. }
  179. of_property_read_u32_array(np, "calxeda,led-order",
  180. pdata->port_to_sgpio,
  181. pdata->n_ports);
  182. if (of_property_read_u32(np, "calxeda,pre-clocks", &pdata->pre_clocks))
  183. pdata->pre_clocks = 0;
  184. if (of_property_read_u32(np, "calxeda,post-clocks",
  185. &pdata->post_clocks))
  186. pdata->post_clocks = 0;
  187. /* store em_loc */
  188. hpriv->em_loc = 0;
  189. hpriv->em_buf_sz = 4;
  190. hpriv->em_msg_type = EM_MSG_TYPE_LED;
  191. pi->flags |= ATA_FLAG_EM | ATA_FLAG_SW_ACTIVITY;
  192. }
  193. static u32 __combo_phy_reg_read(u8 sata_port, u32 addr)
  194. {
  195. u32 data;
  196. u8 dev = port_data[sata_port].phy_devs;
  197. spin_lock(&cphy_lock);
  198. writel(CPHY_MAP(dev, addr), port_data[sata_port].phy_base + 0x800);
  199. data = readl(port_data[sata_port].phy_base + CPHY_ADDR(addr));
  200. spin_unlock(&cphy_lock);
  201. return data;
  202. }
  203. static void __combo_phy_reg_write(u8 sata_port, u32 addr, u32 data)
  204. {
  205. u8 dev = port_data[sata_port].phy_devs;
  206. spin_lock(&cphy_lock);
  207. writel(CPHY_MAP(dev, addr), port_data[sata_port].phy_base + 0x800);
  208. writel(data, port_data[sata_port].phy_base + CPHY_ADDR(addr));
  209. spin_unlock(&cphy_lock);
  210. }
  211. static void combo_phy_wait_for_ready(u8 sata_port)
  212. {
  213. while (__combo_phy_reg_read(sata_port, SERDES_CR_CTL) & CR_BUSY)
  214. udelay(5);
  215. }
  216. static u32 combo_phy_read(u8 sata_port, u32 addr)
  217. {
  218. combo_phy_wait_for_ready(sata_port);
  219. __combo_phy_reg_write(sata_port, SERDES_CR_ADDR, addr);
  220. __combo_phy_reg_write(sata_port, SERDES_CR_CTL, CR_START);
  221. combo_phy_wait_for_ready(sata_port);
  222. return __combo_phy_reg_read(sata_port, SERDES_CR_DATA);
  223. }
  224. static void combo_phy_write(u8 sata_port, u32 addr, u32 data)
  225. {
  226. combo_phy_wait_for_ready(sata_port);
  227. __combo_phy_reg_write(sata_port, SERDES_CR_ADDR, addr);
  228. __combo_phy_reg_write(sata_port, SERDES_CR_DATA, data);
  229. __combo_phy_reg_write(sata_port, SERDES_CR_CTL, CR_WR_RDN | CR_START);
  230. }
  231. static void highbank_cphy_disable_overrides(u8 sata_port)
  232. {
  233. u8 lane = port_data[sata_port].lane_mapping;
  234. u32 tmp;
  235. if (unlikely(port_data[sata_port].phy_base == NULL))
  236. return;
  237. tmp = combo_phy_read(sata_port, CPHY_RX_INPUT_STS + lane * SPHY_LANE);
  238. tmp &= ~CPHY_SATA_RX_OVERRIDE;
  239. combo_phy_write(sata_port, CPHY_RX_OVERRIDE + lane * SPHY_LANE, tmp);
  240. }
  241. static void cphy_override_tx_attenuation(u8 sata_port, u32 val)
  242. {
  243. u8 lane = port_data[sata_port].lane_mapping;
  244. u32 tmp;
  245. if (val & 0x8)
  246. return;
  247. tmp = combo_phy_read(sata_port, CPHY_TX_INPUT_STS + lane * SPHY_LANE);
  248. tmp &= ~CPHY_SATA_TX_OVERRIDE;
  249. combo_phy_write(sata_port, CPHY_TX_OVERRIDE + lane * SPHY_LANE, tmp);
  250. tmp |= CPHY_SATA_TX_OVERRIDE;
  251. combo_phy_write(sata_port, CPHY_TX_OVERRIDE + lane * SPHY_LANE, tmp);
  252. tmp |= (val << CPHY_SATA_TX_ATTEN_SHIFT) & CPHY_SATA_TX_ATTEN;
  253. combo_phy_write(sata_port, CPHY_TX_OVERRIDE + lane * SPHY_LANE, tmp);
  254. }
  255. static void cphy_override_rx_mode(u8 sata_port, u32 val)
  256. {
  257. u8 lane = port_data[sata_port].lane_mapping;
  258. u32 tmp;
  259. tmp = combo_phy_read(sata_port, CPHY_RX_INPUT_STS + lane * SPHY_LANE);
  260. tmp &= ~CPHY_SATA_RX_OVERRIDE;
  261. combo_phy_write(sata_port, CPHY_RX_OVERRIDE + lane * SPHY_LANE, tmp);
  262. tmp |= CPHY_SATA_RX_OVERRIDE;
  263. combo_phy_write(sata_port, CPHY_RX_OVERRIDE + lane * SPHY_LANE, tmp);
  264. tmp &= ~CPHY_SATA_DPLL_MODE;
  265. tmp |= val << CPHY_SATA_DPLL_SHIFT;
  266. combo_phy_write(sata_port, CPHY_RX_OVERRIDE + lane * SPHY_LANE, tmp);
  267. tmp |= CPHY_SATA_DPLL_RESET;
  268. combo_phy_write(sata_port, CPHY_RX_OVERRIDE + lane * SPHY_LANE, tmp);
  269. tmp &= ~CPHY_SATA_DPLL_RESET;
  270. combo_phy_write(sata_port, CPHY_RX_OVERRIDE + lane * SPHY_LANE, tmp);
  271. msleep(15);
  272. }
  273. static void highbank_cphy_override_lane(u8 sata_port)
  274. {
  275. u8 lane = port_data[sata_port].lane_mapping;
  276. u32 tmp, k = 0;
  277. if (unlikely(port_data[sata_port].phy_base == NULL))
  278. return;
  279. do {
  280. tmp = combo_phy_read(sata_port, CPHY_RX_INPUT_STS +
  281. lane * SPHY_LANE);
  282. } while ((tmp & SPHY_HALF_RATE) && (k++ < 1000));
  283. cphy_override_rx_mode(sata_port, 3);
  284. cphy_override_tx_attenuation(sata_port, port_data[sata_port].tx_atten);
  285. }
  286. static int highbank_initialize_phys(struct device *dev, void __iomem *addr)
  287. {
  288. struct device_node *sata_node = dev->of_node;
  289. int phy_count = 0, phy, port = 0, i;
  290. void __iomem *cphy_base[CPHY_PHY_COUNT] = {};
  291. struct device_node *phy_nodes[CPHY_PHY_COUNT] = {};
  292. u32 tx_atten[CPHY_PORT_COUNT] = {};
  293. memset(port_data, 0, sizeof(struct phy_lane_info) * CPHY_PORT_COUNT);
  294. do {
  295. u32 tmp;
  296. struct of_phandle_args phy_data;
  297. if (of_parse_phandle_with_args(sata_node,
  298. "calxeda,port-phys", "#phy-cells",
  299. port, &phy_data))
  300. break;
  301. for (phy = 0; phy < phy_count; phy++) {
  302. if (phy_nodes[phy] == phy_data.np)
  303. break;
  304. }
  305. if (phy_nodes[phy] == NULL) {
  306. phy_nodes[phy] = phy_data.np;
  307. cphy_base[phy] = of_iomap(phy_nodes[phy], 0);
  308. if (cphy_base[phy] == NULL) {
  309. return 0;
  310. }
  311. phy_count += 1;
  312. }
  313. port_data[port].lane_mapping = phy_data.args[0];
  314. of_property_read_u32(phy_nodes[phy], "phydev", &tmp);
  315. port_data[port].phy_devs = tmp;
  316. port_data[port].phy_base = cphy_base[phy];
  317. of_node_put(phy_data.np);
  318. port += 1;
  319. } while (port < CPHY_PORT_COUNT);
  320. of_property_read_u32_array(sata_node, "calxeda,tx-atten",
  321. tx_atten, port);
  322. for (i = 0; i < port; i++)
  323. port_data[i].tx_atten = (u8) tx_atten[i];
  324. return 0;
  325. }
  326. /*
  327. * The Calxeda SATA phy intermittently fails to bring up a link with Gen3
  328. * Retrying the phy hard reset can work around the issue, but the drive
  329. * may fail again. In less than 150 out of 15000 test runs, it took more
  330. * than 10 tries for the link to be established (but never more than 35).
  331. * Triple the maximum observed retry count to provide plenty of margin for
  332. * rare events and to guarantee that the link is established.
  333. *
  334. * Also, the default 2 second time-out on a failed drive is too long in
  335. * this situation. The uboot implementation of the same driver function
  336. * uses a much shorter time-out period and never experiences a time out
  337. * issue. Reducing the time-out to 500ms improves the responsiveness.
  338. * The other timing constants were kept the same as the stock AHCI driver.
  339. * This change was also tested 15000 times on 24 drives and none of them
  340. * experienced a time out.
  341. */
  342. static int ahci_highbank_hardreset(struct ata_link *link, unsigned int *class,
  343. unsigned long deadline)
  344. {
  345. static const unsigned long timing[] = { 5, 100, 500};
  346. struct ata_port *ap = link->ap;
  347. struct ahci_port_priv *pp = ap->private_data;
  348. struct ahci_host_priv *hpriv = ap->host->private_data;
  349. u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
  350. struct ata_taskfile tf;
  351. bool online;
  352. u32 sstatus;
  353. int rc;
  354. int retry = 100;
  355. hpriv->stop_engine(ap);
  356. /* clear D2H reception area to properly wait for D2H FIS */
  357. ata_tf_init(link->device, &tf);
  358. tf.command = ATA_BUSY;
  359. ata_tf_to_fis(&tf, 0, 0, d2h_fis);
  360. do {
  361. highbank_cphy_disable_overrides(link->ap->port_no);
  362. rc = sata_link_hardreset(link, timing, deadline, &online, NULL);
  363. highbank_cphy_override_lane(link->ap->port_no);
  364. /* If the status is 1, we are connected, but the link did not
  365. * come up. So retry resetting the link again.
  366. */
  367. if (sata_scr_read(link, SCR_STATUS, &sstatus))
  368. break;
  369. if (!(sstatus & 0x3))
  370. break;
  371. } while (!online && retry--);
  372. hpriv->start_engine(ap);
  373. if (online)
  374. *class = ahci_dev_classify(ap);
  375. return rc;
  376. }
  377. static struct ata_port_operations ahci_highbank_ops = {
  378. .inherits = &ahci_ops,
  379. .hardreset = ahci_highbank_hardreset,
  380. .transmit_led_message = ecx_transmit_led_message,
  381. };
  382. static const struct ata_port_info ahci_highbank_port_info = {
  383. .flags = AHCI_FLAG_COMMON,
  384. .pio_mask = ATA_PIO4,
  385. .udma_mask = ATA_UDMA6,
  386. .port_ops = &ahci_highbank_ops,
  387. };
  388. static struct scsi_host_template ahci_highbank_platform_sht = {
  389. AHCI_SHT("sata_highbank"),
  390. };
  391. static const struct of_device_id ahci_of_match[] = {
  392. { .compatible = "calxeda,hb-ahci" },
  393. {},
  394. };
  395. MODULE_DEVICE_TABLE(of, ahci_of_match);
  396. static int ahci_highbank_probe(struct platform_device *pdev)
  397. {
  398. struct device *dev = &pdev->dev;
  399. struct ahci_host_priv *hpriv;
  400. struct ecx_plat_data *pdata;
  401. struct ata_host *host;
  402. struct resource *mem;
  403. int irq;
  404. int i;
  405. int rc;
  406. u32 n_ports;
  407. struct ata_port_info pi = ahci_highbank_port_info;
  408. const struct ata_port_info *ppi[] = { &pi, NULL };
  409. mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  410. if (!mem) {
  411. dev_err(dev, "no mmio space\n");
  412. return -EINVAL;
  413. }
  414. irq = platform_get_irq(pdev, 0);
  415. if (irq < 0) {
  416. dev_err(dev, "no irq\n");
  417. return irq;
  418. }
  419. if (!irq)
  420. return -EINVAL;
  421. hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
  422. if (!hpriv) {
  423. dev_err(dev, "can't alloc ahci_host_priv\n");
  424. return -ENOMEM;
  425. }
  426. pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
  427. if (!pdata) {
  428. dev_err(dev, "can't alloc ecx_plat_data\n");
  429. return -ENOMEM;
  430. }
  431. hpriv->irq = irq;
  432. hpriv->flags |= (unsigned long)pi.private_data;
  433. hpriv->mmio = devm_ioremap(dev, mem->start, resource_size(mem));
  434. if (!hpriv->mmio) {
  435. dev_err(dev, "can't map %pR\n", mem);
  436. return -ENOMEM;
  437. }
  438. rc = highbank_initialize_phys(dev, hpriv->mmio);
  439. if (rc)
  440. return rc;
  441. ahci_save_initial_config(dev, hpriv);
  442. /* prepare host */
  443. if (hpriv->cap & HOST_CAP_NCQ)
  444. pi.flags |= ATA_FLAG_NCQ;
  445. if (hpriv->cap & HOST_CAP_PMP)
  446. pi.flags |= ATA_FLAG_PMP;
  447. if (hpriv->cap & HOST_CAP_64)
  448. dma_set_coherent_mask(dev, DMA_BIT_MASK(64));
  449. /* CAP.NP sometimes indicate the index of the last enabled
  450. * port, at other times, that of the last possible port, so
  451. * determining the maximum port number requires looking at
  452. * both CAP.NP and port_map.
  453. */
  454. n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
  455. pdata->n_ports = n_ports;
  456. hpriv->plat_data = pdata;
  457. highbank_set_em_messages(dev, hpriv, &pi);
  458. host = ata_host_alloc_pinfo(dev, ppi, n_ports);
  459. if (!host) {
  460. rc = -ENOMEM;
  461. goto err0;
  462. }
  463. host->private_data = hpriv;
  464. if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
  465. host->flags |= ATA_HOST_PARALLEL_SCAN;
  466. for (i = 0; i < host->n_ports; i++) {
  467. struct ata_port *ap = host->ports[i];
  468. ata_port_desc(ap, "mmio %pR", mem);
  469. ata_port_desc(ap, "port 0x%x", 0x100 + ap->port_no * 0x80);
  470. /* set enclosure management message type */
  471. if (ap->flags & ATA_FLAG_EM)
  472. ap->em_message_type = hpriv->em_msg_type;
  473. /* disabled/not-implemented port */
  474. if (!(hpriv->port_map & (1 << i)))
  475. ap->ops = &ata_dummy_port_ops;
  476. }
  477. rc = ahci_reset_controller(host);
  478. if (rc)
  479. goto err0;
  480. ahci_init_controller(host);
  481. ahci_print_info(host, "platform");
  482. rc = ahci_host_activate(host, &ahci_highbank_platform_sht);
  483. if (rc)
  484. goto err0;
  485. return 0;
  486. err0:
  487. return rc;
  488. }
  489. #ifdef CONFIG_PM_SLEEP
  490. static int ahci_highbank_suspend(struct device *dev)
  491. {
  492. struct ata_host *host = dev_get_drvdata(dev);
  493. struct ahci_host_priv *hpriv = host->private_data;
  494. void __iomem *mmio = hpriv->mmio;
  495. u32 ctl;
  496. if (hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
  497. dev_err(dev, "firmware update required for suspend/resume\n");
  498. return -EIO;
  499. }
  500. /*
  501. * AHCI spec rev1.1 section 8.3.3:
  502. * Software must disable interrupts prior to requesting a
  503. * transition of the HBA to D3 state.
  504. */
  505. ctl = readl(mmio + HOST_CTL);
  506. ctl &= ~HOST_IRQ_EN;
  507. writel(ctl, mmio + HOST_CTL);
  508. readl(mmio + HOST_CTL); /* flush */
  509. return ata_host_suspend(host, PMSG_SUSPEND);
  510. }
  511. static int ahci_highbank_resume(struct device *dev)
  512. {
  513. struct ata_host *host = dev_get_drvdata(dev);
  514. int rc;
  515. if (dev->power.power_state.event == PM_EVENT_SUSPEND) {
  516. rc = ahci_reset_controller(host);
  517. if (rc)
  518. return rc;
  519. ahci_init_controller(host);
  520. }
  521. ata_host_resume(host);
  522. return 0;
  523. }
  524. #endif
  525. static SIMPLE_DEV_PM_OPS(ahci_highbank_pm_ops,
  526. ahci_highbank_suspend, ahci_highbank_resume);
  527. static struct platform_driver ahci_highbank_driver = {
  528. .remove = ata_platform_remove_one,
  529. .driver = {
  530. .name = "highbank-ahci",
  531. .of_match_table = ahci_of_match,
  532. .pm = &ahci_highbank_pm_ops,
  533. },
  534. .probe = ahci_highbank_probe,
  535. };
  536. module_platform_driver(ahci_highbank_driver);
  537. MODULE_DESCRIPTION("Calxeda Highbank AHCI SATA platform driver");
  538. MODULE_AUTHOR("Mark Langsdorf <mark.langsdorf@calxeda.com>");
  539. MODULE_LICENSE("GPL");
  540. MODULE_ALIAS("sata:highbank");