sata_fsl.c 43 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * drivers/ata/sata_fsl.c
  4. *
  5. * Freescale 3.0Gbps SATA device driver
  6. *
  7. * Author: Ashish Kalra <ashish.kalra@freescale.com>
  8. * Li Yang <leoli@freescale.com>
  9. *
  10. * Copyright (c) 2006-2007, 2011-2012 Freescale Semiconductor, Inc.
  11. */
  12. #include <linux/kernel.h>
  13. #include <linux/module.h>
  14. #include <linux/platform_device.h>
  15. #include <linux/slab.h>
  16. #include <scsi/scsi_host.h>
  17. #include <scsi/scsi_cmnd.h>
  18. #include <linux/libata.h>
  19. #include <asm/io.h>
  20. #include <linux/of_address.h>
  21. #include <linux/of_irq.h>
  22. #include <linux/of_platform.h>
  23. static unsigned int intr_coalescing_count;
  24. module_param(intr_coalescing_count, int, S_IRUGO);
  25. MODULE_PARM_DESC(intr_coalescing_count,
  26. "INT coalescing count threshold (1..31)");
  27. static unsigned int intr_coalescing_ticks;
  28. module_param(intr_coalescing_ticks, int, S_IRUGO);
  29. MODULE_PARM_DESC(intr_coalescing_ticks,
  30. "INT coalescing timer threshold in AHB ticks");
  31. /* Controller information */
  32. enum {
  33. SATA_FSL_QUEUE_DEPTH = 16,
  34. SATA_FSL_MAX_PRD = 63,
  35. SATA_FSL_MAX_PRD_USABLE = SATA_FSL_MAX_PRD - 1,
  36. SATA_FSL_MAX_PRD_DIRECT = 16, /* Direct PRDT entries */
  37. SATA_FSL_HOST_FLAGS = (ATA_FLAG_SATA | ATA_FLAG_PIO_DMA |
  38. ATA_FLAG_PMP | ATA_FLAG_NCQ |
  39. ATA_FLAG_AN | ATA_FLAG_NO_LOG_PAGE),
  40. SATA_FSL_MAX_CMDS = SATA_FSL_QUEUE_DEPTH,
  41. SATA_FSL_CMD_HDR_SIZE = 16, /* 4 DWORDS */
  42. SATA_FSL_CMD_SLOT_SIZE = (SATA_FSL_MAX_CMDS * SATA_FSL_CMD_HDR_SIZE),
  43. /*
  44. * SATA-FSL host controller supports a max. of (15+1) direct PRDEs, and
  45. * chained indirect PRDEs up to a max count of 63.
  46. * We are allocating an array of 63 PRDEs contiguously, but PRDE#15 will
  47. * be setup as an indirect descriptor, pointing to it's next
  48. * (contiguous) PRDE. Though chained indirect PRDE arrays are
  49. * supported,it will be more efficient to use a direct PRDT and
  50. * a single chain/link to indirect PRDE array/PRDT.
  51. */
  52. SATA_FSL_CMD_DESC_CFIS_SZ = 32,
  53. SATA_FSL_CMD_DESC_SFIS_SZ = 32,
  54. SATA_FSL_CMD_DESC_ACMD_SZ = 16,
  55. SATA_FSL_CMD_DESC_RSRVD = 16,
  56. SATA_FSL_CMD_DESC_SIZE = (SATA_FSL_CMD_DESC_CFIS_SZ +
  57. SATA_FSL_CMD_DESC_SFIS_SZ +
  58. SATA_FSL_CMD_DESC_ACMD_SZ +
  59. SATA_FSL_CMD_DESC_RSRVD +
  60. SATA_FSL_MAX_PRD * 16),
  61. SATA_FSL_CMD_DESC_OFFSET_TO_PRDT =
  62. (SATA_FSL_CMD_DESC_CFIS_SZ +
  63. SATA_FSL_CMD_DESC_SFIS_SZ +
  64. SATA_FSL_CMD_DESC_ACMD_SZ +
  65. SATA_FSL_CMD_DESC_RSRVD),
  66. SATA_FSL_CMD_DESC_AR_SZ = (SATA_FSL_CMD_DESC_SIZE * SATA_FSL_MAX_CMDS),
  67. SATA_FSL_PORT_PRIV_DMA_SZ = (SATA_FSL_CMD_SLOT_SIZE +
  68. SATA_FSL_CMD_DESC_AR_SZ),
  69. /*
  70. * MPC8315 has two SATA controllers, SATA1 & SATA2
  71. * (one port per controller)
  72. * MPC837x has 2/4 controllers, one port per controller
  73. */
  74. SATA_FSL_MAX_PORTS = 1,
  75. SATA_FSL_IRQ_FLAG = IRQF_SHARED,
  76. };
  77. /*
  78. * Interrupt Coalescing Control Register bitdefs */
  79. enum {
  80. ICC_MIN_INT_COUNT_THRESHOLD = 1,
  81. ICC_MAX_INT_COUNT_THRESHOLD = ((1 << 5) - 1),
  82. ICC_MIN_INT_TICKS_THRESHOLD = 0,
  83. ICC_MAX_INT_TICKS_THRESHOLD = ((1 << 19) - 1),
  84. ICC_SAFE_INT_TICKS = 1,
  85. };
  86. /*
  87. * Host Controller command register set - per port
  88. */
  89. enum {
  90. CQ = 0,
  91. CA = 8,
  92. CC = 0x10,
  93. CE = 0x18,
  94. DE = 0x20,
  95. CHBA = 0x24,
  96. HSTATUS = 0x28,
  97. HCONTROL = 0x2C,
  98. CQPMP = 0x30,
  99. SIGNATURE = 0x34,
  100. ICC = 0x38,
  101. /*
  102. * Host Status Register (HStatus) bitdefs
  103. */
  104. ONLINE = (1 << 31),
  105. GOING_OFFLINE = (1 << 30),
  106. BIST_ERR = (1 << 29),
  107. CLEAR_ERROR = (1 << 27),
  108. FATAL_ERR_HC_MASTER_ERR = (1 << 18),
  109. FATAL_ERR_PARITY_ERR_TX = (1 << 17),
  110. FATAL_ERR_PARITY_ERR_RX = (1 << 16),
  111. FATAL_ERR_DATA_UNDERRUN = (1 << 13),
  112. FATAL_ERR_DATA_OVERRUN = (1 << 12),
  113. FATAL_ERR_CRC_ERR_TX = (1 << 11),
  114. FATAL_ERR_CRC_ERR_RX = (1 << 10),
  115. FATAL_ERR_FIFO_OVRFL_TX = (1 << 9),
  116. FATAL_ERR_FIFO_OVRFL_RX = (1 << 8),
  117. FATAL_ERROR_DECODE = FATAL_ERR_HC_MASTER_ERR |
  118. FATAL_ERR_PARITY_ERR_TX |
  119. FATAL_ERR_PARITY_ERR_RX |
  120. FATAL_ERR_DATA_UNDERRUN |
  121. FATAL_ERR_DATA_OVERRUN |
  122. FATAL_ERR_CRC_ERR_TX |
  123. FATAL_ERR_CRC_ERR_RX |
  124. FATAL_ERR_FIFO_OVRFL_TX | FATAL_ERR_FIFO_OVRFL_RX,
  125. INT_ON_DATA_LENGTH_MISMATCH = (1 << 12),
  126. INT_ON_FATAL_ERR = (1 << 5),
  127. INT_ON_PHYRDY_CHG = (1 << 4),
  128. INT_ON_SIGNATURE_UPDATE = (1 << 3),
  129. INT_ON_SNOTIFY_UPDATE = (1 << 2),
  130. INT_ON_SINGL_DEVICE_ERR = (1 << 1),
  131. INT_ON_CMD_COMPLETE = 1,
  132. INT_ON_ERROR = INT_ON_FATAL_ERR | INT_ON_SNOTIFY_UPDATE |
  133. INT_ON_PHYRDY_CHG | INT_ON_SINGL_DEVICE_ERR,
  134. /*
  135. * Host Control Register (HControl) bitdefs
  136. */
  137. HCONTROL_ONLINE_PHY_RST = (1 << 31),
  138. HCONTROL_FORCE_OFFLINE = (1 << 30),
  139. HCONTROL_LEGACY = (1 << 28),
  140. HCONTROL_PARITY_PROT_MOD = (1 << 14),
  141. HCONTROL_DPATH_PARITY = (1 << 12),
  142. HCONTROL_SNOOP_ENABLE = (1 << 10),
  143. HCONTROL_PMP_ATTACHED = (1 << 9),
  144. HCONTROL_COPYOUT_STATFIS = (1 << 8),
  145. IE_ON_FATAL_ERR = (1 << 5),
  146. IE_ON_PHYRDY_CHG = (1 << 4),
  147. IE_ON_SIGNATURE_UPDATE = (1 << 3),
  148. IE_ON_SNOTIFY_UPDATE = (1 << 2),
  149. IE_ON_SINGL_DEVICE_ERR = (1 << 1),
  150. IE_ON_CMD_COMPLETE = 1,
  151. DEFAULT_PORT_IRQ_ENABLE_MASK = IE_ON_FATAL_ERR | IE_ON_PHYRDY_CHG |
  152. IE_ON_SIGNATURE_UPDATE | IE_ON_SNOTIFY_UPDATE |
  153. IE_ON_SINGL_DEVICE_ERR | IE_ON_CMD_COMPLETE,
  154. EXT_INDIRECT_SEG_PRD_FLAG = (1 << 31),
  155. DATA_SNOOP_ENABLE_V1 = (1 << 22),
  156. DATA_SNOOP_ENABLE_V2 = (1 << 28),
  157. };
  158. /*
  159. * SATA Superset Registers
  160. */
  161. enum {
  162. SSTATUS = 0,
  163. SERROR = 4,
  164. SCONTROL = 8,
  165. SNOTIFY = 0xC,
  166. };
  167. /*
  168. * Control Status Register Set
  169. */
  170. enum {
  171. TRANSCFG = 0,
  172. TRANSSTATUS = 4,
  173. LINKCFG = 8,
  174. LINKCFG1 = 0xC,
  175. LINKCFG2 = 0x10,
  176. LINKSTATUS = 0x14,
  177. LINKSTATUS1 = 0x18,
  178. PHYCTRLCFG = 0x1C,
  179. COMMANDSTAT = 0x20,
  180. };
  181. /* TRANSCFG (transport-layer) configuration control */
  182. enum {
  183. TRANSCFG_RX_WATER_MARK = (1 << 4),
  184. };
  185. /* PHY (link-layer) configuration control */
  186. enum {
  187. PHY_BIST_ENABLE = 0x01,
  188. };
  189. /*
  190. * Command Header Table entry, i.e, command slot
  191. * 4 Dwords per command slot, command header size == 64 Dwords.
  192. */
  193. struct cmdhdr_tbl_entry {
  194. u32 cda;
  195. u32 prde_fis_len;
  196. u32 ttl;
  197. u32 desc_info;
  198. };
  199. /*
  200. * Description information bitdefs
  201. */
  202. enum {
  203. CMD_DESC_RES = (1 << 11),
  204. VENDOR_SPECIFIC_BIST = (1 << 10),
  205. CMD_DESC_SNOOP_ENABLE = (1 << 9),
  206. FPDMA_QUEUED_CMD = (1 << 8),
  207. SRST_CMD = (1 << 7),
  208. BIST = (1 << 6),
  209. ATAPI_CMD = (1 << 5),
  210. };
  211. /*
  212. * Command Descriptor
  213. */
  214. struct command_desc {
  215. u8 cfis[8 * 4];
  216. u8 sfis[8 * 4];
  217. u8 acmd[4 * 4];
  218. u8 fill[4 * 4];
  219. u32 prdt[SATA_FSL_MAX_PRD_DIRECT * 4];
  220. u32 prdt_indirect[(SATA_FSL_MAX_PRD - SATA_FSL_MAX_PRD_DIRECT) * 4];
  221. };
  222. /*
  223. * Physical region table descriptor(PRD)
  224. */
  225. struct prde {
  226. u32 dba;
  227. u8 fill[2 * 4];
  228. u32 ddc_and_ext;
  229. };
  230. /*
  231. * ata_port private data
  232. * This is our per-port instance data.
  233. */
  234. struct sata_fsl_port_priv {
  235. struct cmdhdr_tbl_entry *cmdslot;
  236. dma_addr_t cmdslot_paddr;
  237. struct command_desc *cmdentry;
  238. dma_addr_t cmdentry_paddr;
  239. };
  240. /*
  241. * ata_port->host_set private data
  242. */
  243. struct sata_fsl_host_priv {
  244. void __iomem *hcr_base;
  245. void __iomem *ssr_base;
  246. void __iomem *csr_base;
  247. int irq;
  248. int data_snoop;
  249. struct device_attribute intr_coalescing;
  250. struct device_attribute rx_watermark;
  251. };
  252. static void fsl_sata_set_irq_coalescing(struct ata_host *host,
  253. unsigned int count, unsigned int ticks)
  254. {
  255. struct sata_fsl_host_priv *host_priv = host->private_data;
  256. void __iomem *hcr_base = host_priv->hcr_base;
  257. unsigned long flags;
  258. if (count > ICC_MAX_INT_COUNT_THRESHOLD)
  259. count = ICC_MAX_INT_COUNT_THRESHOLD;
  260. else if (count < ICC_MIN_INT_COUNT_THRESHOLD)
  261. count = ICC_MIN_INT_COUNT_THRESHOLD;
  262. if (ticks > ICC_MAX_INT_TICKS_THRESHOLD)
  263. ticks = ICC_MAX_INT_TICKS_THRESHOLD;
  264. else if ((ICC_MIN_INT_TICKS_THRESHOLD == ticks) &&
  265. (count > ICC_MIN_INT_COUNT_THRESHOLD))
  266. ticks = ICC_SAFE_INT_TICKS;
  267. spin_lock_irqsave(&host->lock, flags);
  268. iowrite32((count << 24 | ticks), hcr_base + ICC);
  269. intr_coalescing_count = count;
  270. intr_coalescing_ticks = ticks;
  271. spin_unlock_irqrestore(&host->lock, flags);
  272. DPRINTK("interrupt coalescing, count = 0x%x, ticks = %x\n",
  273. intr_coalescing_count, intr_coalescing_ticks);
  274. DPRINTK("ICC register status: (hcr base: 0x%x) = 0x%x\n",
  275. hcr_base, ioread32(hcr_base + ICC));
  276. }
  277. static ssize_t fsl_sata_intr_coalescing_show(struct device *dev,
  278. struct device_attribute *attr, char *buf)
  279. {
  280. return sprintf(buf, "%d %d\n",
  281. intr_coalescing_count, intr_coalescing_ticks);
  282. }
  283. static ssize_t fsl_sata_intr_coalescing_store(struct device *dev,
  284. struct device_attribute *attr,
  285. const char *buf, size_t count)
  286. {
  287. unsigned int coalescing_count, coalescing_ticks;
  288. if (sscanf(buf, "%d%d",
  289. &coalescing_count,
  290. &coalescing_ticks) != 2) {
  291. printk(KERN_ERR "fsl-sata: wrong parameter format.\n");
  292. return -EINVAL;
  293. }
  294. fsl_sata_set_irq_coalescing(dev_get_drvdata(dev),
  295. coalescing_count, coalescing_ticks);
  296. return strlen(buf);
  297. }
  298. static ssize_t fsl_sata_rx_watermark_show(struct device *dev,
  299. struct device_attribute *attr, char *buf)
  300. {
  301. unsigned int rx_watermark;
  302. unsigned long flags;
  303. struct ata_host *host = dev_get_drvdata(dev);
  304. struct sata_fsl_host_priv *host_priv = host->private_data;
  305. void __iomem *csr_base = host_priv->csr_base;
  306. spin_lock_irqsave(&host->lock, flags);
  307. rx_watermark = ioread32(csr_base + TRANSCFG);
  308. rx_watermark &= 0x1f;
  309. spin_unlock_irqrestore(&host->lock, flags);
  310. return sprintf(buf, "%d\n", rx_watermark);
  311. }
  312. static ssize_t fsl_sata_rx_watermark_store(struct device *dev,
  313. struct device_attribute *attr,
  314. const char *buf, size_t count)
  315. {
  316. unsigned int rx_watermark;
  317. unsigned long flags;
  318. struct ata_host *host = dev_get_drvdata(dev);
  319. struct sata_fsl_host_priv *host_priv = host->private_data;
  320. void __iomem *csr_base = host_priv->csr_base;
  321. u32 temp;
  322. if (sscanf(buf, "%d", &rx_watermark) != 1) {
  323. printk(KERN_ERR "fsl-sata: wrong parameter format.\n");
  324. return -EINVAL;
  325. }
  326. spin_lock_irqsave(&host->lock, flags);
  327. temp = ioread32(csr_base + TRANSCFG);
  328. temp &= 0xffffffe0;
  329. iowrite32(temp | rx_watermark, csr_base + TRANSCFG);
  330. spin_unlock_irqrestore(&host->lock, flags);
  331. return strlen(buf);
  332. }
  333. static inline unsigned int sata_fsl_tag(unsigned int tag,
  334. void __iomem *hcr_base)
  335. {
  336. /* We let libATA core do actual (queue) tag allocation */
  337. if (unlikely(tag >= SATA_FSL_QUEUE_DEPTH)) {
  338. DPRINTK("tag %d invalid : out of range\n", tag);
  339. return 0;
  340. }
  341. if (unlikely((ioread32(hcr_base + CQ)) & (1 << tag))) {
  342. DPRINTK("tag %d invalid : in use!!\n", tag);
  343. return 0;
  344. }
  345. return tag;
  346. }
  347. static void sata_fsl_setup_cmd_hdr_entry(struct sata_fsl_port_priv *pp,
  348. unsigned int tag, u32 desc_info,
  349. u32 data_xfer_len, u8 num_prde,
  350. u8 fis_len)
  351. {
  352. dma_addr_t cmd_descriptor_address;
  353. cmd_descriptor_address = pp->cmdentry_paddr +
  354. tag * SATA_FSL_CMD_DESC_SIZE;
  355. /* NOTE: both data_xfer_len & fis_len are Dword counts */
  356. pp->cmdslot[tag].cda = cpu_to_le32(cmd_descriptor_address);
  357. pp->cmdslot[tag].prde_fis_len =
  358. cpu_to_le32((num_prde << 16) | (fis_len << 2));
  359. pp->cmdslot[tag].ttl = cpu_to_le32(data_xfer_len & ~0x03);
  360. pp->cmdslot[tag].desc_info = cpu_to_le32(desc_info | (tag & 0x1F));
  361. VPRINTK("cda=0x%x, prde_fis_len=0x%x, ttl=0x%x, di=0x%x\n",
  362. pp->cmdslot[tag].cda,
  363. pp->cmdslot[tag].prde_fis_len,
  364. pp->cmdslot[tag].ttl, pp->cmdslot[tag].desc_info);
  365. }
  366. static unsigned int sata_fsl_fill_sg(struct ata_queued_cmd *qc, void *cmd_desc,
  367. u32 *ttl, dma_addr_t cmd_desc_paddr,
  368. int data_snoop)
  369. {
  370. struct scatterlist *sg;
  371. unsigned int num_prde = 0;
  372. u32 ttl_dwords = 0;
  373. /*
  374. * NOTE : direct & indirect prdt's are contiguously allocated
  375. */
  376. struct prde *prd = (struct prde *)&((struct command_desc *)
  377. cmd_desc)->prdt;
  378. struct prde *prd_ptr_to_indirect_ext = NULL;
  379. unsigned indirect_ext_segment_sz = 0;
  380. dma_addr_t indirect_ext_segment_paddr;
  381. unsigned int si;
  382. VPRINTK("SATA FSL : cd = 0x%p, prd = 0x%p\n", cmd_desc, prd);
  383. indirect_ext_segment_paddr = cmd_desc_paddr +
  384. SATA_FSL_CMD_DESC_OFFSET_TO_PRDT + SATA_FSL_MAX_PRD_DIRECT * 16;
  385. for_each_sg(qc->sg, sg, qc->n_elem, si) {
  386. dma_addr_t sg_addr = sg_dma_address(sg);
  387. u32 sg_len = sg_dma_len(sg);
  388. VPRINTK("SATA FSL : fill_sg, sg_addr = 0x%llx, sg_len = %d\n",
  389. (unsigned long long)sg_addr, sg_len);
  390. /* warn if each s/g element is not dword aligned */
  391. if (unlikely(sg_addr & 0x03))
  392. ata_port_err(qc->ap, "s/g addr unaligned : 0x%llx\n",
  393. (unsigned long long)sg_addr);
  394. if (unlikely(sg_len & 0x03))
  395. ata_port_err(qc->ap, "s/g len unaligned : 0x%x\n",
  396. sg_len);
  397. if (num_prde == (SATA_FSL_MAX_PRD_DIRECT - 1) &&
  398. sg_next(sg) != NULL) {
  399. VPRINTK("setting indirect prde\n");
  400. prd_ptr_to_indirect_ext = prd;
  401. prd->dba = cpu_to_le32(indirect_ext_segment_paddr);
  402. indirect_ext_segment_sz = 0;
  403. ++prd;
  404. ++num_prde;
  405. }
  406. ttl_dwords += sg_len;
  407. prd->dba = cpu_to_le32(sg_addr);
  408. prd->ddc_and_ext = cpu_to_le32(data_snoop | (sg_len & ~0x03));
  409. VPRINTK("sg_fill, ttl=%d, dba=0x%x, ddc=0x%x\n",
  410. ttl_dwords, prd->dba, prd->ddc_and_ext);
  411. ++num_prde;
  412. ++prd;
  413. if (prd_ptr_to_indirect_ext)
  414. indirect_ext_segment_sz += sg_len;
  415. }
  416. if (prd_ptr_to_indirect_ext) {
  417. /* set indirect extension flag along with indirect ext. size */
  418. prd_ptr_to_indirect_ext->ddc_and_ext =
  419. cpu_to_le32((EXT_INDIRECT_SEG_PRD_FLAG |
  420. data_snoop |
  421. (indirect_ext_segment_sz & ~0x03)));
  422. }
  423. *ttl = ttl_dwords;
  424. return num_prde;
  425. }
  426. static enum ata_completion_errors sata_fsl_qc_prep(struct ata_queued_cmd *qc)
  427. {
  428. struct ata_port *ap = qc->ap;
  429. struct sata_fsl_port_priv *pp = ap->private_data;
  430. struct sata_fsl_host_priv *host_priv = ap->host->private_data;
  431. void __iomem *hcr_base = host_priv->hcr_base;
  432. unsigned int tag = sata_fsl_tag(qc->hw_tag, hcr_base);
  433. struct command_desc *cd;
  434. u32 desc_info = CMD_DESC_RES | CMD_DESC_SNOOP_ENABLE;
  435. u32 num_prde = 0;
  436. u32 ttl_dwords = 0;
  437. dma_addr_t cd_paddr;
  438. cd = (struct command_desc *)pp->cmdentry + tag;
  439. cd_paddr = pp->cmdentry_paddr + tag * SATA_FSL_CMD_DESC_SIZE;
  440. ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, (u8 *) &cd->cfis);
  441. VPRINTK("Dumping cfis : 0x%x, 0x%x, 0x%x\n",
  442. cd->cfis[0], cd->cfis[1], cd->cfis[2]);
  443. if (qc->tf.protocol == ATA_PROT_NCQ) {
  444. VPRINTK("FPDMA xfer,Sctor cnt[0:7],[8:15] = %d,%d\n",
  445. cd->cfis[3], cd->cfis[11]);
  446. }
  447. /* setup "ACMD - atapi command" in cmd. desc. if this is ATAPI cmd */
  448. if (ata_is_atapi(qc->tf.protocol)) {
  449. desc_info |= ATAPI_CMD;
  450. memset((void *)&cd->acmd, 0, 32);
  451. memcpy((void *)&cd->acmd, qc->cdb, qc->dev->cdb_len);
  452. }
  453. if (qc->flags & ATA_QCFLAG_DMAMAP)
  454. num_prde = sata_fsl_fill_sg(qc, (void *)cd,
  455. &ttl_dwords, cd_paddr,
  456. host_priv->data_snoop);
  457. if (qc->tf.protocol == ATA_PROT_NCQ)
  458. desc_info |= FPDMA_QUEUED_CMD;
  459. sata_fsl_setup_cmd_hdr_entry(pp, tag, desc_info, ttl_dwords,
  460. num_prde, 5);
  461. VPRINTK("SATA FSL : xx_qc_prep, di = 0x%x, ttl = %d, num_prde = %d\n",
  462. desc_info, ttl_dwords, num_prde);
  463. return AC_ERR_OK;
  464. }
  465. static unsigned int sata_fsl_qc_issue(struct ata_queued_cmd *qc)
  466. {
  467. struct ata_port *ap = qc->ap;
  468. struct sata_fsl_host_priv *host_priv = ap->host->private_data;
  469. void __iomem *hcr_base = host_priv->hcr_base;
  470. unsigned int tag = sata_fsl_tag(qc->hw_tag, hcr_base);
  471. VPRINTK("xx_qc_issue called,CQ=0x%x,CA=0x%x,CE=0x%x,CC=0x%x\n",
  472. ioread32(CQ + hcr_base),
  473. ioread32(CA + hcr_base),
  474. ioread32(CE + hcr_base), ioread32(CC + hcr_base));
  475. iowrite32(qc->dev->link->pmp, CQPMP + hcr_base);
  476. /* Simply queue command to the controller/device */
  477. iowrite32(1 << tag, CQ + hcr_base);
  478. VPRINTK("xx_qc_issue called, tag=%d, CQ=0x%x, CA=0x%x\n",
  479. tag, ioread32(CQ + hcr_base), ioread32(CA + hcr_base));
  480. VPRINTK("CE=0x%x, DE=0x%x, CC=0x%x, CmdStat = 0x%x\n",
  481. ioread32(CE + hcr_base),
  482. ioread32(DE + hcr_base),
  483. ioread32(CC + hcr_base),
  484. ioread32(COMMANDSTAT + host_priv->csr_base));
  485. return 0;
  486. }
  487. static bool sata_fsl_qc_fill_rtf(struct ata_queued_cmd *qc)
  488. {
  489. struct sata_fsl_port_priv *pp = qc->ap->private_data;
  490. struct sata_fsl_host_priv *host_priv = qc->ap->host->private_data;
  491. void __iomem *hcr_base = host_priv->hcr_base;
  492. unsigned int tag = sata_fsl_tag(qc->hw_tag, hcr_base);
  493. struct command_desc *cd;
  494. cd = pp->cmdentry + tag;
  495. ata_tf_from_fis(cd->sfis, &qc->result_tf);
  496. return true;
  497. }
  498. static int sata_fsl_scr_write(struct ata_link *link,
  499. unsigned int sc_reg_in, u32 val)
  500. {
  501. struct sata_fsl_host_priv *host_priv = link->ap->host->private_data;
  502. void __iomem *ssr_base = host_priv->ssr_base;
  503. unsigned int sc_reg;
  504. switch (sc_reg_in) {
  505. case SCR_STATUS:
  506. case SCR_ERROR:
  507. case SCR_CONTROL:
  508. case SCR_ACTIVE:
  509. sc_reg = sc_reg_in;
  510. break;
  511. default:
  512. return -EINVAL;
  513. }
  514. VPRINTK("xx_scr_write, reg_in = %d\n", sc_reg);
  515. iowrite32(val, ssr_base + (sc_reg * 4));
  516. return 0;
  517. }
  518. static int sata_fsl_scr_read(struct ata_link *link,
  519. unsigned int sc_reg_in, u32 *val)
  520. {
  521. struct sata_fsl_host_priv *host_priv = link->ap->host->private_data;
  522. void __iomem *ssr_base = host_priv->ssr_base;
  523. unsigned int sc_reg;
  524. switch (sc_reg_in) {
  525. case SCR_STATUS:
  526. case SCR_ERROR:
  527. case SCR_CONTROL:
  528. case SCR_ACTIVE:
  529. sc_reg = sc_reg_in;
  530. break;
  531. default:
  532. return -EINVAL;
  533. }
  534. VPRINTK("xx_scr_read, reg_in = %d\n", sc_reg);
  535. *val = ioread32(ssr_base + (sc_reg * 4));
  536. return 0;
  537. }
  538. static void sata_fsl_freeze(struct ata_port *ap)
  539. {
  540. struct sata_fsl_host_priv *host_priv = ap->host->private_data;
  541. void __iomem *hcr_base = host_priv->hcr_base;
  542. u32 temp;
  543. VPRINTK("xx_freeze, CQ=0x%x, CA=0x%x, CE=0x%x, DE=0x%x\n",
  544. ioread32(CQ + hcr_base),
  545. ioread32(CA + hcr_base),
  546. ioread32(CE + hcr_base), ioread32(DE + hcr_base));
  547. VPRINTK("CmdStat = 0x%x\n",
  548. ioread32(host_priv->csr_base + COMMANDSTAT));
  549. /* disable interrupts on the controller/port */
  550. temp = ioread32(hcr_base + HCONTROL);
  551. iowrite32((temp & ~0x3F), hcr_base + HCONTROL);
  552. VPRINTK("in xx_freeze : HControl = 0x%x, HStatus = 0x%x\n",
  553. ioread32(hcr_base + HCONTROL), ioread32(hcr_base + HSTATUS));
  554. }
  555. static void sata_fsl_thaw(struct ata_port *ap)
  556. {
  557. struct sata_fsl_host_priv *host_priv = ap->host->private_data;
  558. void __iomem *hcr_base = host_priv->hcr_base;
  559. u32 temp;
  560. /* ack. any pending IRQs for this controller/port */
  561. temp = ioread32(hcr_base + HSTATUS);
  562. VPRINTK("xx_thaw, pending IRQs = 0x%x\n", (temp & 0x3F));
  563. if (temp & 0x3F)
  564. iowrite32((temp & 0x3F), hcr_base + HSTATUS);
  565. /* enable interrupts on the controller/port */
  566. temp = ioread32(hcr_base + HCONTROL);
  567. iowrite32((temp | DEFAULT_PORT_IRQ_ENABLE_MASK), hcr_base + HCONTROL);
  568. VPRINTK("xx_thaw : HControl = 0x%x, HStatus = 0x%x\n",
  569. ioread32(hcr_base + HCONTROL), ioread32(hcr_base + HSTATUS));
  570. }
  571. static void sata_fsl_pmp_attach(struct ata_port *ap)
  572. {
  573. struct sata_fsl_host_priv *host_priv = ap->host->private_data;
  574. void __iomem *hcr_base = host_priv->hcr_base;
  575. u32 temp;
  576. temp = ioread32(hcr_base + HCONTROL);
  577. iowrite32((temp | HCONTROL_PMP_ATTACHED), hcr_base + HCONTROL);
  578. }
  579. static void sata_fsl_pmp_detach(struct ata_port *ap)
  580. {
  581. struct sata_fsl_host_priv *host_priv = ap->host->private_data;
  582. void __iomem *hcr_base = host_priv->hcr_base;
  583. u32 temp;
  584. temp = ioread32(hcr_base + HCONTROL);
  585. temp &= ~HCONTROL_PMP_ATTACHED;
  586. iowrite32(temp, hcr_base + HCONTROL);
  587. /* enable interrupts on the controller/port */
  588. temp = ioread32(hcr_base + HCONTROL);
  589. iowrite32((temp | DEFAULT_PORT_IRQ_ENABLE_MASK), hcr_base + HCONTROL);
  590. }
  591. static int sata_fsl_port_start(struct ata_port *ap)
  592. {
  593. struct device *dev = ap->host->dev;
  594. struct sata_fsl_port_priv *pp;
  595. void *mem;
  596. dma_addr_t mem_dma;
  597. struct sata_fsl_host_priv *host_priv = ap->host->private_data;
  598. void __iomem *hcr_base = host_priv->hcr_base;
  599. u32 temp;
  600. pp = kzalloc(sizeof(*pp), GFP_KERNEL);
  601. if (!pp)
  602. return -ENOMEM;
  603. mem = dma_alloc_coherent(dev, SATA_FSL_PORT_PRIV_DMA_SZ, &mem_dma,
  604. GFP_KERNEL);
  605. if (!mem) {
  606. kfree(pp);
  607. return -ENOMEM;
  608. }
  609. pp->cmdslot = mem;
  610. pp->cmdslot_paddr = mem_dma;
  611. mem += SATA_FSL_CMD_SLOT_SIZE;
  612. mem_dma += SATA_FSL_CMD_SLOT_SIZE;
  613. pp->cmdentry = mem;
  614. pp->cmdentry_paddr = mem_dma;
  615. ap->private_data = pp;
  616. VPRINTK("CHBA = 0x%x, cmdentry_phys = 0x%x\n",
  617. pp->cmdslot_paddr, pp->cmdentry_paddr);
  618. /* Now, update the CHBA register in host controller cmd register set */
  619. iowrite32(pp->cmdslot_paddr & 0xffffffff, hcr_base + CHBA);
  620. /*
  621. * Now, we can bring the controller on-line & also initiate
  622. * the COMINIT sequence, we simply return here and the boot-probing
  623. * & device discovery process is re-initiated by libATA using a
  624. * Softreset EH (dummy) session. Hence, boot probing and device
  625. * discovey will be part of sata_fsl_softreset() callback.
  626. */
  627. temp = ioread32(hcr_base + HCONTROL);
  628. iowrite32((temp | HCONTROL_ONLINE_PHY_RST), hcr_base + HCONTROL);
  629. VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
  630. VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
  631. VPRINTK("CHBA = 0x%x\n", ioread32(hcr_base + CHBA));
  632. return 0;
  633. }
  634. static void sata_fsl_port_stop(struct ata_port *ap)
  635. {
  636. struct device *dev = ap->host->dev;
  637. struct sata_fsl_port_priv *pp = ap->private_data;
  638. struct sata_fsl_host_priv *host_priv = ap->host->private_data;
  639. void __iomem *hcr_base = host_priv->hcr_base;
  640. u32 temp;
  641. /*
  642. * Force host controller to go off-line, aborting current operations
  643. */
  644. temp = ioread32(hcr_base + HCONTROL);
  645. temp &= ~HCONTROL_ONLINE_PHY_RST;
  646. temp |= HCONTROL_FORCE_OFFLINE;
  647. iowrite32(temp, hcr_base + HCONTROL);
  648. /* Poll for controller to go offline - should happen immediately */
  649. ata_wait_register(ap, hcr_base + HSTATUS, ONLINE, ONLINE, 1, 1);
  650. ap->private_data = NULL;
  651. dma_free_coherent(dev, SATA_FSL_PORT_PRIV_DMA_SZ,
  652. pp->cmdslot, pp->cmdslot_paddr);
  653. kfree(pp);
  654. }
  655. static unsigned int sata_fsl_dev_classify(struct ata_port *ap)
  656. {
  657. struct sata_fsl_host_priv *host_priv = ap->host->private_data;
  658. void __iomem *hcr_base = host_priv->hcr_base;
  659. struct ata_taskfile tf;
  660. u32 temp;
  661. temp = ioread32(hcr_base + SIGNATURE);
  662. VPRINTK("raw sig = 0x%x\n", temp);
  663. VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
  664. VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
  665. tf.lbah = (temp >> 24) & 0xff;
  666. tf.lbam = (temp >> 16) & 0xff;
  667. tf.lbal = (temp >> 8) & 0xff;
  668. tf.nsect = temp & 0xff;
  669. return ata_dev_classify(&tf);
  670. }
  671. static int sata_fsl_hardreset(struct ata_link *link, unsigned int *class,
  672. unsigned long deadline)
  673. {
  674. struct ata_port *ap = link->ap;
  675. struct sata_fsl_host_priv *host_priv = ap->host->private_data;
  676. void __iomem *hcr_base = host_priv->hcr_base;
  677. u32 temp;
  678. int i = 0;
  679. unsigned long start_jiffies;
  680. DPRINTK("in xx_hardreset\n");
  681. try_offline_again:
  682. /*
  683. * Force host controller to go off-line, aborting current operations
  684. */
  685. temp = ioread32(hcr_base + HCONTROL);
  686. temp &= ~HCONTROL_ONLINE_PHY_RST;
  687. iowrite32(temp, hcr_base + HCONTROL);
  688. /* Poll for controller to go offline */
  689. temp = ata_wait_register(ap, hcr_base + HSTATUS, ONLINE, ONLINE,
  690. 1, 500);
  691. if (temp & ONLINE) {
  692. ata_port_err(ap, "Hardreset failed, not off-lined %d\n", i);
  693. /*
  694. * Try to offline controller atleast twice
  695. */
  696. i++;
  697. if (i == 2)
  698. goto err;
  699. else
  700. goto try_offline_again;
  701. }
  702. DPRINTK("hardreset, controller off-lined\n");
  703. VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
  704. VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
  705. /*
  706. * PHY reset should remain asserted for atleast 1ms
  707. */
  708. ata_msleep(ap, 1);
  709. sata_set_spd(link);
  710. /*
  711. * Now, bring the host controller online again, this can take time
  712. * as PHY reset and communication establishment, 1st D2H FIS and
  713. * device signature update is done, on safe side assume 500ms
  714. * NOTE : Host online status may be indicated immediately!!
  715. */
  716. temp = ioread32(hcr_base + HCONTROL);
  717. temp |= (HCONTROL_ONLINE_PHY_RST | HCONTROL_SNOOP_ENABLE);
  718. temp |= HCONTROL_PMP_ATTACHED;
  719. iowrite32(temp, hcr_base + HCONTROL);
  720. temp = ata_wait_register(ap, hcr_base + HSTATUS, ONLINE, 0, 1, 500);
  721. if (!(temp & ONLINE)) {
  722. ata_port_err(ap, "Hardreset failed, not on-lined\n");
  723. goto err;
  724. }
  725. DPRINTK("hardreset, controller off-lined & on-lined\n");
  726. VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
  727. VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
  728. /*
  729. * First, wait for the PHYRDY change to occur before waiting for
  730. * the signature, and also verify if SStatus indicates device
  731. * presence
  732. */
  733. temp = ata_wait_register(ap, hcr_base + HSTATUS, 0xFF, 0, 1, 500);
  734. if ((!(temp & 0x10)) || ata_link_offline(link)) {
  735. ata_port_warn(ap, "No Device OR PHYRDY change,Hstatus = 0x%x\n",
  736. ioread32(hcr_base + HSTATUS));
  737. *class = ATA_DEV_NONE;
  738. return 0;
  739. }
  740. /*
  741. * Wait for the first D2H from device,i.e,signature update notification
  742. */
  743. start_jiffies = jiffies;
  744. temp = ata_wait_register(ap, hcr_base + HSTATUS, 0xFF, 0x10,
  745. 500, jiffies_to_msecs(deadline - start_jiffies));
  746. if ((temp & 0xFF) != 0x18) {
  747. ata_port_warn(ap, "No Signature Update\n");
  748. *class = ATA_DEV_NONE;
  749. goto do_followup_srst;
  750. } else {
  751. ata_port_info(ap, "Signature Update detected @ %d msecs\n",
  752. jiffies_to_msecs(jiffies - start_jiffies));
  753. *class = sata_fsl_dev_classify(ap);
  754. return 0;
  755. }
  756. do_followup_srst:
  757. /*
  758. * request libATA to perform follow-up softreset
  759. */
  760. return -EAGAIN;
  761. err:
  762. return -EIO;
  763. }
  764. static int sata_fsl_softreset(struct ata_link *link, unsigned int *class,
  765. unsigned long deadline)
  766. {
  767. struct ata_port *ap = link->ap;
  768. struct sata_fsl_port_priv *pp = ap->private_data;
  769. struct sata_fsl_host_priv *host_priv = ap->host->private_data;
  770. void __iomem *hcr_base = host_priv->hcr_base;
  771. int pmp = sata_srst_pmp(link);
  772. u32 temp;
  773. struct ata_taskfile tf;
  774. u8 *cfis;
  775. u32 Serror;
  776. DPRINTK("in xx_softreset\n");
  777. if (ata_link_offline(link)) {
  778. DPRINTK("PHY reports no device\n");
  779. *class = ATA_DEV_NONE;
  780. return 0;
  781. }
  782. /*
  783. * Send a device reset (SRST) explicitly on command slot #0
  784. * Check : will the command queue (reg) be cleared during offlining ??
  785. * Also we will be online only if Phy commn. has been established
  786. * and device presence has been detected, therefore if we have
  787. * reached here, we can send a command to the target device
  788. */
  789. DPRINTK("Sending SRST/device reset\n");
  790. ata_tf_init(link->device, &tf);
  791. cfis = (u8 *) &pp->cmdentry->cfis;
  792. /* device reset/SRST is a control register update FIS, uses tag0 */
  793. sata_fsl_setup_cmd_hdr_entry(pp, 0,
  794. SRST_CMD | CMD_DESC_RES | CMD_DESC_SNOOP_ENABLE, 0, 0, 5);
  795. tf.ctl |= ATA_SRST; /* setup SRST bit in taskfile control reg */
  796. ata_tf_to_fis(&tf, pmp, 0, cfis);
  797. DPRINTK("Dumping cfis : 0x%x, 0x%x, 0x%x, 0x%x\n",
  798. cfis[0], cfis[1], cfis[2], cfis[3]);
  799. /*
  800. * Queue SRST command to the controller/device, ensure that no
  801. * other commands are active on the controller/device
  802. */
  803. DPRINTK("@Softreset, CQ = 0x%x, CA = 0x%x, CC = 0x%x\n",
  804. ioread32(CQ + hcr_base),
  805. ioread32(CA + hcr_base), ioread32(CC + hcr_base));
  806. iowrite32(0xFFFF, CC + hcr_base);
  807. if (pmp != SATA_PMP_CTRL_PORT)
  808. iowrite32(pmp, CQPMP + hcr_base);
  809. iowrite32(1, CQ + hcr_base);
  810. temp = ata_wait_register(ap, CQ + hcr_base, 0x1, 0x1, 1, 5000);
  811. if (temp & 0x1) {
  812. ata_port_warn(ap, "ATA_SRST issue failed\n");
  813. DPRINTK("Softreset@5000,CQ=0x%x,CA=0x%x,CC=0x%x\n",
  814. ioread32(CQ + hcr_base),
  815. ioread32(CA + hcr_base), ioread32(CC + hcr_base));
  816. sata_fsl_scr_read(&ap->link, SCR_ERROR, &Serror);
  817. DPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
  818. DPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
  819. DPRINTK("Serror = 0x%x\n", Serror);
  820. goto err;
  821. }
  822. ata_msleep(ap, 1);
  823. /*
  824. * SATA device enters reset state after receiving a Control register
  825. * FIS with SRST bit asserted and it awaits another H2D Control reg.
  826. * FIS with SRST bit cleared, then the device does internal diags &
  827. * initialization, followed by indicating it's initialization status
  828. * using ATA signature D2H register FIS to the host controller.
  829. */
  830. sata_fsl_setup_cmd_hdr_entry(pp, 0, CMD_DESC_RES | CMD_DESC_SNOOP_ENABLE,
  831. 0, 0, 5);
  832. tf.ctl &= ~ATA_SRST; /* 2nd H2D Ctl. register FIS */
  833. ata_tf_to_fis(&tf, pmp, 0, cfis);
  834. if (pmp != SATA_PMP_CTRL_PORT)
  835. iowrite32(pmp, CQPMP + hcr_base);
  836. iowrite32(1, CQ + hcr_base);
  837. ata_msleep(ap, 150); /* ?? */
  838. /*
  839. * The above command would have signalled an interrupt on command
  840. * complete, which needs special handling, by clearing the Nth
  841. * command bit of the CCreg
  842. */
  843. iowrite32(0x01, CC + hcr_base); /* We know it will be cmd#0 always */
  844. DPRINTK("SATA FSL : Now checking device signature\n");
  845. *class = ATA_DEV_NONE;
  846. /* Verify if SStatus indicates device presence */
  847. if (ata_link_online(link)) {
  848. /*
  849. * if we are here, device presence has been detected,
  850. * 1st D2H FIS would have been received, but sfis in
  851. * command desc. is not updated, but signature register
  852. * would have been updated
  853. */
  854. *class = sata_fsl_dev_classify(ap);
  855. DPRINTK("class = %d\n", *class);
  856. VPRINTK("ccreg = 0x%x\n", ioread32(hcr_base + CC));
  857. VPRINTK("cereg = 0x%x\n", ioread32(hcr_base + CE));
  858. }
  859. return 0;
  860. err:
  861. return -EIO;
  862. }
  863. static void sata_fsl_error_handler(struct ata_port *ap)
  864. {
  865. DPRINTK("in xx_error_handler\n");
  866. sata_pmp_error_handler(ap);
  867. }
  868. static void sata_fsl_post_internal_cmd(struct ata_queued_cmd *qc)
  869. {
  870. if (qc->flags & ATA_QCFLAG_FAILED)
  871. qc->err_mask |= AC_ERR_OTHER;
  872. if (qc->err_mask) {
  873. /* make DMA engine forget about the failed command */
  874. }
  875. }
  876. static void sata_fsl_error_intr(struct ata_port *ap)
  877. {
  878. struct sata_fsl_host_priv *host_priv = ap->host->private_data;
  879. void __iomem *hcr_base = host_priv->hcr_base;
  880. u32 hstatus, dereg=0, cereg = 0, SError = 0;
  881. unsigned int err_mask = 0, action = 0;
  882. int freeze = 0, abort=0;
  883. struct ata_link *link = NULL;
  884. struct ata_queued_cmd *qc = NULL;
  885. struct ata_eh_info *ehi;
  886. hstatus = ioread32(hcr_base + HSTATUS);
  887. cereg = ioread32(hcr_base + CE);
  888. /* first, analyze and record host port events */
  889. link = &ap->link;
  890. ehi = &link->eh_info;
  891. ata_ehi_clear_desc(ehi);
  892. /*
  893. * Handle & Clear SError
  894. */
  895. sata_fsl_scr_read(&ap->link, SCR_ERROR, &SError);
  896. if (unlikely(SError & 0xFFFF0000))
  897. sata_fsl_scr_write(&ap->link, SCR_ERROR, SError);
  898. DPRINTK("error_intr,hStat=0x%x,CE=0x%x,DE =0x%x,SErr=0x%x\n",
  899. hstatus, cereg, ioread32(hcr_base + DE), SError);
  900. /* handle fatal errors */
  901. if (hstatus & FATAL_ERROR_DECODE) {
  902. ehi->err_mask |= AC_ERR_ATA_BUS;
  903. ehi->action |= ATA_EH_SOFTRESET;
  904. freeze = 1;
  905. }
  906. /* Handle SDB FIS receive & notify update */
  907. if (hstatus & INT_ON_SNOTIFY_UPDATE)
  908. sata_async_notification(ap);
  909. /* Handle PHYRDY change notification */
  910. if (hstatus & INT_ON_PHYRDY_CHG) {
  911. DPRINTK("SATA FSL: PHYRDY change indication\n");
  912. /* Setup a soft-reset EH action */
  913. ata_ehi_hotplugged(ehi);
  914. ata_ehi_push_desc(ehi, "%s", "PHY RDY changed");
  915. freeze = 1;
  916. }
  917. /* handle single device errors */
  918. if (cereg) {
  919. /*
  920. * clear the command error, also clears queue to the device
  921. * in error, and we can (re)issue commands to this device.
  922. * When a device is in error all commands queued into the
  923. * host controller and at the device are considered aborted
  924. * and the queue for that device is stopped. Now, after
  925. * clearing the device error, we can issue commands to the
  926. * device to interrogate it to find the source of the error.
  927. */
  928. abort = 1;
  929. DPRINTK("single device error, CE=0x%x, DE=0x%x\n",
  930. ioread32(hcr_base + CE), ioread32(hcr_base + DE));
  931. /* find out the offending link and qc */
  932. if (ap->nr_pmp_links) {
  933. unsigned int dev_num;
  934. dereg = ioread32(hcr_base + DE);
  935. iowrite32(dereg, hcr_base + DE);
  936. iowrite32(cereg, hcr_base + CE);
  937. dev_num = ffs(dereg) - 1;
  938. if (dev_num < ap->nr_pmp_links && dereg != 0) {
  939. link = &ap->pmp_link[dev_num];
  940. ehi = &link->eh_info;
  941. qc = ata_qc_from_tag(ap, link->active_tag);
  942. /*
  943. * We should consider this as non fatal error,
  944. * and TF must be updated as done below.
  945. */
  946. err_mask |= AC_ERR_DEV;
  947. } else {
  948. err_mask |= AC_ERR_HSM;
  949. action |= ATA_EH_HARDRESET;
  950. freeze = 1;
  951. }
  952. } else {
  953. dereg = ioread32(hcr_base + DE);
  954. iowrite32(dereg, hcr_base + DE);
  955. iowrite32(cereg, hcr_base + CE);
  956. qc = ata_qc_from_tag(ap, link->active_tag);
  957. /*
  958. * We should consider this as non fatal error,
  959. * and TF must be updated as done below.
  960. */
  961. err_mask |= AC_ERR_DEV;
  962. }
  963. }
  964. /* record error info */
  965. if (qc)
  966. qc->err_mask |= err_mask;
  967. else
  968. ehi->err_mask |= err_mask;
  969. ehi->action |= action;
  970. /* freeze or abort */
  971. if (freeze)
  972. ata_port_freeze(ap);
  973. else if (abort) {
  974. if (qc)
  975. ata_link_abort(qc->dev->link);
  976. else
  977. ata_port_abort(ap);
  978. }
  979. }
  980. static void sata_fsl_host_intr(struct ata_port *ap)
  981. {
  982. struct sata_fsl_host_priv *host_priv = ap->host->private_data;
  983. void __iomem *hcr_base = host_priv->hcr_base;
  984. u32 hstatus, done_mask = 0;
  985. struct ata_queued_cmd *qc;
  986. u32 SError;
  987. u32 tag;
  988. u32 status_mask = INT_ON_ERROR;
  989. hstatus = ioread32(hcr_base + HSTATUS);
  990. sata_fsl_scr_read(&ap->link, SCR_ERROR, &SError);
  991. /* Read command completed register */
  992. done_mask = ioread32(hcr_base + CC);
  993. /* Workaround for data length mismatch errata */
  994. if (unlikely(hstatus & INT_ON_DATA_LENGTH_MISMATCH)) {
  995. ata_qc_for_each_with_internal(ap, qc, tag) {
  996. if (qc && ata_is_atapi(qc->tf.protocol)) {
  997. u32 hcontrol;
  998. /* Set HControl[27] to clear error registers */
  999. hcontrol = ioread32(hcr_base + HCONTROL);
  1000. iowrite32(hcontrol | CLEAR_ERROR,
  1001. hcr_base + HCONTROL);
  1002. /* Clear HControl[27] */
  1003. iowrite32(hcontrol & ~CLEAR_ERROR,
  1004. hcr_base + HCONTROL);
  1005. /* Clear SError[E] bit */
  1006. sata_fsl_scr_write(&ap->link, SCR_ERROR,
  1007. SError);
  1008. /* Ignore fatal error and device error */
  1009. status_mask &= ~(INT_ON_SINGL_DEVICE_ERR
  1010. | INT_ON_FATAL_ERR);
  1011. break;
  1012. }
  1013. }
  1014. }
  1015. if (unlikely(SError & 0xFFFF0000)) {
  1016. DPRINTK("serror @host_intr : 0x%x\n", SError);
  1017. sata_fsl_error_intr(ap);
  1018. }
  1019. if (unlikely(hstatus & status_mask)) {
  1020. DPRINTK("error interrupt!!\n");
  1021. sata_fsl_error_intr(ap);
  1022. return;
  1023. }
  1024. VPRINTK("Status of all queues :\n");
  1025. VPRINTK("done_mask/CC = 0x%x, CA = 0x%x, CE=0x%x,CQ=0x%x,apqa=0x%llx\n",
  1026. done_mask,
  1027. ioread32(hcr_base + CA),
  1028. ioread32(hcr_base + CE),
  1029. ioread32(hcr_base + CQ),
  1030. ap->qc_active);
  1031. if (done_mask & ap->qc_active) {
  1032. int i;
  1033. /* clear CC bit, this will also complete the interrupt */
  1034. iowrite32(done_mask, hcr_base + CC);
  1035. DPRINTK("Status of all queues :\n");
  1036. DPRINTK("done_mask/CC = 0x%x, CA = 0x%x, CE=0x%x\n",
  1037. done_mask, ioread32(hcr_base + CA),
  1038. ioread32(hcr_base + CE));
  1039. for (i = 0; i < SATA_FSL_QUEUE_DEPTH; i++) {
  1040. if (done_mask & (1 << i))
  1041. DPRINTK
  1042. ("completing ncq cmd,tag=%d,CC=0x%x,CA=0x%x\n",
  1043. i, ioread32(hcr_base + CC),
  1044. ioread32(hcr_base + CA));
  1045. }
  1046. ata_qc_complete_multiple(ap, ata_qc_get_active(ap) ^ done_mask);
  1047. return;
  1048. } else if ((ap->qc_active & (1ULL << ATA_TAG_INTERNAL))) {
  1049. iowrite32(1, hcr_base + CC);
  1050. qc = ata_qc_from_tag(ap, ATA_TAG_INTERNAL);
  1051. DPRINTK("completing non-ncq cmd, CC=0x%x\n",
  1052. ioread32(hcr_base + CC));
  1053. if (qc) {
  1054. ata_qc_complete(qc);
  1055. }
  1056. } else {
  1057. /* Spurious Interrupt!! */
  1058. DPRINTK("spurious interrupt!!, CC = 0x%x\n",
  1059. ioread32(hcr_base + CC));
  1060. iowrite32(done_mask, hcr_base + CC);
  1061. return;
  1062. }
  1063. }
  1064. static irqreturn_t sata_fsl_interrupt(int irq, void *dev_instance)
  1065. {
  1066. struct ata_host *host = dev_instance;
  1067. struct sata_fsl_host_priv *host_priv = host->private_data;
  1068. void __iomem *hcr_base = host_priv->hcr_base;
  1069. u32 interrupt_enables;
  1070. unsigned handled = 0;
  1071. struct ata_port *ap;
  1072. /* ack. any pending IRQs for this controller/port */
  1073. interrupt_enables = ioread32(hcr_base + HSTATUS);
  1074. interrupt_enables &= 0x3F;
  1075. DPRINTK("interrupt status 0x%x\n", interrupt_enables);
  1076. if (!interrupt_enables)
  1077. return IRQ_NONE;
  1078. spin_lock(&host->lock);
  1079. /* Assuming one port per host controller */
  1080. ap = host->ports[0];
  1081. if (ap) {
  1082. sata_fsl_host_intr(ap);
  1083. } else {
  1084. dev_warn(host->dev, "interrupt on disabled port 0\n");
  1085. }
  1086. iowrite32(interrupt_enables, hcr_base + HSTATUS);
  1087. handled = 1;
  1088. spin_unlock(&host->lock);
  1089. return IRQ_RETVAL(handled);
  1090. }
  1091. /*
  1092. * Multiple ports are represented by multiple SATA controllers with
  1093. * one port per controller
  1094. */
  1095. static int sata_fsl_init_controller(struct ata_host *host)
  1096. {
  1097. struct sata_fsl_host_priv *host_priv = host->private_data;
  1098. void __iomem *hcr_base = host_priv->hcr_base;
  1099. u32 temp;
  1100. /*
  1101. * NOTE : We cannot bring the controller online before setting
  1102. * the CHBA, hence main controller initialization is done as
  1103. * part of the port_start() callback
  1104. */
  1105. /* sata controller to operate in enterprise mode */
  1106. temp = ioread32(hcr_base + HCONTROL);
  1107. iowrite32(temp & ~HCONTROL_LEGACY, hcr_base + HCONTROL);
  1108. /* ack. any pending IRQs for this controller/port */
  1109. temp = ioread32(hcr_base + HSTATUS);
  1110. if (temp & 0x3F)
  1111. iowrite32((temp & 0x3F), hcr_base + HSTATUS);
  1112. /* Keep interrupts disabled on the controller */
  1113. temp = ioread32(hcr_base + HCONTROL);
  1114. iowrite32((temp & ~0x3F), hcr_base + HCONTROL);
  1115. /* Disable interrupt coalescing control(icc), for the moment */
  1116. DPRINTK("icc = 0x%x\n", ioread32(hcr_base + ICC));
  1117. iowrite32(0x01000000, hcr_base + ICC);
  1118. /* clear error registers, SError is cleared by libATA */
  1119. iowrite32(0x00000FFFF, hcr_base + CE);
  1120. iowrite32(0x00000FFFF, hcr_base + DE);
  1121. /*
  1122. * reset the number of command complete bits which will cause the
  1123. * interrupt to be signaled
  1124. */
  1125. fsl_sata_set_irq_coalescing(host, intr_coalescing_count,
  1126. intr_coalescing_ticks);
  1127. /*
  1128. * host controller will be brought on-line, during xx_port_start()
  1129. * callback, that should also initiate the OOB, COMINIT sequence
  1130. */
  1131. DPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
  1132. DPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
  1133. return 0;
  1134. }
  1135. static void sata_fsl_host_stop(struct ata_host *host)
  1136. {
  1137. struct sata_fsl_host_priv *host_priv = host->private_data;
  1138. iounmap(host_priv->hcr_base);
  1139. kfree(host_priv);
  1140. }
  1141. /*
  1142. * scsi mid-layer and libata interface structures
  1143. */
  1144. static struct scsi_host_template sata_fsl_sht = {
  1145. ATA_NCQ_SHT("sata_fsl"),
  1146. .can_queue = SATA_FSL_QUEUE_DEPTH,
  1147. .sg_tablesize = SATA_FSL_MAX_PRD_USABLE,
  1148. .dma_boundary = ATA_DMA_BOUNDARY,
  1149. };
  1150. static struct ata_port_operations sata_fsl_ops = {
  1151. .inherits = &sata_pmp_port_ops,
  1152. .qc_defer = ata_std_qc_defer,
  1153. .qc_prep = sata_fsl_qc_prep,
  1154. .qc_issue = sata_fsl_qc_issue,
  1155. .qc_fill_rtf = sata_fsl_qc_fill_rtf,
  1156. .scr_read = sata_fsl_scr_read,
  1157. .scr_write = sata_fsl_scr_write,
  1158. .freeze = sata_fsl_freeze,
  1159. .thaw = sata_fsl_thaw,
  1160. .softreset = sata_fsl_softreset,
  1161. .hardreset = sata_fsl_hardreset,
  1162. .pmp_softreset = sata_fsl_softreset,
  1163. .error_handler = sata_fsl_error_handler,
  1164. .post_internal_cmd = sata_fsl_post_internal_cmd,
  1165. .port_start = sata_fsl_port_start,
  1166. .port_stop = sata_fsl_port_stop,
  1167. .host_stop = sata_fsl_host_stop,
  1168. .pmp_attach = sata_fsl_pmp_attach,
  1169. .pmp_detach = sata_fsl_pmp_detach,
  1170. };
  1171. static const struct ata_port_info sata_fsl_port_info[] = {
  1172. {
  1173. .flags = SATA_FSL_HOST_FLAGS,
  1174. .pio_mask = ATA_PIO4,
  1175. .udma_mask = ATA_UDMA6,
  1176. .port_ops = &sata_fsl_ops,
  1177. },
  1178. };
  1179. static int sata_fsl_probe(struct platform_device *ofdev)
  1180. {
  1181. int retval = -ENXIO;
  1182. void __iomem *hcr_base = NULL;
  1183. void __iomem *ssr_base = NULL;
  1184. void __iomem *csr_base = NULL;
  1185. struct sata_fsl_host_priv *host_priv = NULL;
  1186. int irq;
  1187. struct ata_host *host = NULL;
  1188. u32 temp;
  1189. struct ata_port_info pi = sata_fsl_port_info[0];
  1190. const struct ata_port_info *ppi[] = { &pi, NULL };
  1191. dev_info(&ofdev->dev, "Sata FSL Platform/CSB Driver init\n");
  1192. hcr_base = of_iomap(ofdev->dev.of_node, 0);
  1193. if (!hcr_base)
  1194. goto error_exit_with_cleanup;
  1195. ssr_base = hcr_base + 0x100;
  1196. csr_base = hcr_base + 0x140;
  1197. if (!of_device_is_compatible(ofdev->dev.of_node, "fsl,mpc8315-sata")) {
  1198. temp = ioread32(csr_base + TRANSCFG);
  1199. temp = temp & 0xffffffe0;
  1200. iowrite32(temp | TRANSCFG_RX_WATER_MARK, csr_base + TRANSCFG);
  1201. }
  1202. DPRINTK("@reset i/o = 0x%x\n", ioread32(csr_base + TRANSCFG));
  1203. DPRINTK("sizeof(cmd_desc) = %d\n", sizeof(struct command_desc));
  1204. DPRINTK("sizeof(#define cmd_desc) = %d\n", SATA_FSL_CMD_DESC_SIZE);
  1205. host_priv = kzalloc(sizeof(struct sata_fsl_host_priv), GFP_KERNEL);
  1206. if (!host_priv)
  1207. goto error_exit_with_cleanup;
  1208. host_priv->hcr_base = hcr_base;
  1209. host_priv->ssr_base = ssr_base;
  1210. host_priv->csr_base = csr_base;
  1211. irq = platform_get_irq(ofdev, 0);
  1212. if (irq < 0) {
  1213. retval = irq;
  1214. goto error_exit_with_cleanup;
  1215. }
  1216. host_priv->irq = irq;
  1217. if (of_device_is_compatible(ofdev->dev.of_node, "fsl,pq-sata-v2"))
  1218. host_priv->data_snoop = DATA_SNOOP_ENABLE_V2;
  1219. else
  1220. host_priv->data_snoop = DATA_SNOOP_ENABLE_V1;
  1221. /* allocate host structure */
  1222. host = ata_host_alloc_pinfo(&ofdev->dev, ppi, SATA_FSL_MAX_PORTS);
  1223. if (!host) {
  1224. retval = -ENOMEM;
  1225. goto error_exit_with_cleanup;
  1226. }
  1227. /* host->iomap is not used currently */
  1228. host->private_data = host_priv;
  1229. /* initialize host controller */
  1230. sata_fsl_init_controller(host);
  1231. /*
  1232. * Now, register with libATA core, this will also initiate the
  1233. * device discovery process, invoking our port_start() handler &
  1234. * error_handler() to execute a dummy Softreset EH session
  1235. */
  1236. ata_host_activate(host, irq, sata_fsl_interrupt, SATA_FSL_IRQ_FLAG,
  1237. &sata_fsl_sht);
  1238. host_priv->intr_coalescing.show = fsl_sata_intr_coalescing_show;
  1239. host_priv->intr_coalescing.store = fsl_sata_intr_coalescing_store;
  1240. sysfs_attr_init(&host_priv->intr_coalescing.attr);
  1241. host_priv->intr_coalescing.attr.name = "intr_coalescing";
  1242. host_priv->intr_coalescing.attr.mode = S_IRUGO | S_IWUSR;
  1243. retval = device_create_file(host->dev, &host_priv->intr_coalescing);
  1244. if (retval)
  1245. goto error_exit_with_cleanup;
  1246. host_priv->rx_watermark.show = fsl_sata_rx_watermark_show;
  1247. host_priv->rx_watermark.store = fsl_sata_rx_watermark_store;
  1248. sysfs_attr_init(&host_priv->rx_watermark.attr);
  1249. host_priv->rx_watermark.attr.name = "rx_watermark";
  1250. host_priv->rx_watermark.attr.mode = S_IRUGO | S_IWUSR;
  1251. retval = device_create_file(host->dev, &host_priv->rx_watermark);
  1252. if (retval) {
  1253. device_remove_file(&ofdev->dev, &host_priv->intr_coalescing);
  1254. goto error_exit_with_cleanup;
  1255. }
  1256. return 0;
  1257. error_exit_with_cleanup:
  1258. if (host)
  1259. ata_host_detach(host);
  1260. if (hcr_base)
  1261. iounmap(hcr_base);
  1262. kfree(host_priv);
  1263. return retval;
  1264. }
  1265. static int sata_fsl_remove(struct platform_device *ofdev)
  1266. {
  1267. struct ata_host *host = platform_get_drvdata(ofdev);
  1268. struct sata_fsl_host_priv *host_priv = host->private_data;
  1269. device_remove_file(&ofdev->dev, &host_priv->intr_coalescing);
  1270. device_remove_file(&ofdev->dev, &host_priv->rx_watermark);
  1271. ata_host_detach(host);
  1272. return 0;
  1273. }
  1274. #ifdef CONFIG_PM_SLEEP
  1275. static int sata_fsl_suspend(struct platform_device *op, pm_message_t state)
  1276. {
  1277. struct ata_host *host = platform_get_drvdata(op);
  1278. return ata_host_suspend(host, state);
  1279. }
  1280. static int sata_fsl_resume(struct platform_device *op)
  1281. {
  1282. struct ata_host *host = platform_get_drvdata(op);
  1283. struct sata_fsl_host_priv *host_priv = host->private_data;
  1284. int ret;
  1285. void __iomem *hcr_base = host_priv->hcr_base;
  1286. struct ata_port *ap = host->ports[0];
  1287. struct sata_fsl_port_priv *pp = ap->private_data;
  1288. ret = sata_fsl_init_controller(host);
  1289. if (ret) {
  1290. dev_err(&op->dev, "Error initializing hardware\n");
  1291. return ret;
  1292. }
  1293. /* Recovery the CHBA register in host controller cmd register set */
  1294. iowrite32(pp->cmdslot_paddr & 0xffffffff, hcr_base + CHBA);
  1295. iowrite32((ioread32(hcr_base + HCONTROL)
  1296. | HCONTROL_ONLINE_PHY_RST
  1297. | HCONTROL_SNOOP_ENABLE
  1298. | HCONTROL_PMP_ATTACHED),
  1299. hcr_base + HCONTROL);
  1300. ata_host_resume(host);
  1301. return 0;
  1302. }
  1303. #endif
  1304. static const struct of_device_id fsl_sata_match[] = {
  1305. {
  1306. .compatible = "fsl,pq-sata",
  1307. },
  1308. {
  1309. .compatible = "fsl,pq-sata-v2",
  1310. },
  1311. {},
  1312. };
  1313. MODULE_DEVICE_TABLE(of, fsl_sata_match);
  1314. static struct platform_driver fsl_sata_driver = {
  1315. .driver = {
  1316. .name = "fsl-sata",
  1317. .of_match_table = fsl_sata_match,
  1318. },
  1319. .probe = sata_fsl_probe,
  1320. .remove = sata_fsl_remove,
  1321. #ifdef CONFIG_PM_SLEEP
  1322. .suspend = sata_fsl_suspend,
  1323. .resume = sata_fsl_resume,
  1324. #endif
  1325. };
  1326. module_platform_driver(fsl_sata_driver);
  1327. MODULE_LICENSE("GPL");
  1328. MODULE_AUTHOR("Ashish Kalra, Freescale Semiconductor");
  1329. MODULE_DESCRIPTION("Freescale 3.0Gbps SATA controller low level driver");
  1330. MODULE_VERSION("1.10");