pdc_adma.c 15 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * pdc_adma.c - Pacific Digital Corporation ADMA
  4. *
  5. * Maintained by: Tejun Heo <tj@kernel.org>
  6. *
  7. * Copyright 2005 Mark Lord
  8. *
  9. * libata documentation is available via 'make {ps|pdf}docs',
  10. * as Documentation/driver-api/libata.rst
  11. *
  12. * Supports ATA disks in single-packet ADMA mode.
  13. * Uses PIO for everything else.
  14. *
  15. * TODO: Use ADMA transfers for ATAPI devices, when possible.
  16. * This requires careful attention to a number of quirks of the chip.
  17. */
  18. #include <linux/kernel.h>
  19. #include <linux/module.h>
  20. #include <linux/gfp.h>
  21. #include <linux/pci.h>
  22. #include <linux/blkdev.h>
  23. #include <linux/delay.h>
  24. #include <linux/interrupt.h>
  25. #include <linux/device.h>
  26. #include <scsi/scsi_host.h>
  27. #include <linux/libata.h>
  28. #define DRV_NAME "pdc_adma"
  29. #define DRV_VERSION "1.0"
  30. /* macro to calculate base address for ATA regs */
  31. #define ADMA_ATA_REGS(base, port_no) ((base) + ((port_no) * 0x40))
  32. /* macro to calculate base address for ADMA regs */
  33. #define ADMA_REGS(base, port_no) ((base) + 0x80 + ((port_no) * 0x20))
  34. /* macro to obtain addresses from ata_port */
  35. #define ADMA_PORT_REGS(ap) \
  36. ADMA_REGS((ap)->host->iomap[ADMA_MMIO_BAR], ap->port_no)
  37. enum {
  38. ADMA_MMIO_BAR = 4,
  39. ADMA_PORTS = 2,
  40. ADMA_CPB_BYTES = 40,
  41. ADMA_PRD_BYTES = LIBATA_MAX_PRD * 16,
  42. ADMA_PKT_BYTES = ADMA_CPB_BYTES + ADMA_PRD_BYTES,
  43. ADMA_DMA_BOUNDARY = 0xffffffff,
  44. /* global register offsets */
  45. ADMA_MODE_LOCK = 0x00c7,
  46. /* per-channel register offsets */
  47. ADMA_CONTROL = 0x0000, /* ADMA control */
  48. ADMA_STATUS = 0x0002, /* ADMA status */
  49. ADMA_CPB_COUNT = 0x0004, /* CPB count */
  50. ADMA_CPB_CURRENT = 0x000c, /* current CPB address */
  51. ADMA_CPB_NEXT = 0x000c, /* next CPB address */
  52. ADMA_CPB_LOOKUP = 0x0010, /* CPB lookup table */
  53. ADMA_FIFO_IN = 0x0014, /* input FIFO threshold */
  54. ADMA_FIFO_OUT = 0x0016, /* output FIFO threshold */
  55. /* ADMA_CONTROL register bits */
  56. aNIEN = (1 << 8), /* irq mask: 1==masked */
  57. aGO = (1 << 7), /* packet trigger ("Go!") */
  58. aRSTADM = (1 << 5), /* ADMA logic reset */
  59. aPIOMD4 = 0x0003, /* PIO mode 4 */
  60. /* ADMA_STATUS register bits */
  61. aPSD = (1 << 6),
  62. aUIRQ = (1 << 4),
  63. aPERR = (1 << 0),
  64. /* CPB bits */
  65. cDONE = (1 << 0),
  66. cATERR = (1 << 3),
  67. cVLD = (1 << 0),
  68. cDAT = (1 << 2),
  69. cIEN = (1 << 3),
  70. /* PRD bits */
  71. pORD = (1 << 4),
  72. pDIRO = (1 << 5),
  73. pEND = (1 << 7),
  74. /* ATA register flags */
  75. rIGN = (1 << 5),
  76. rEND = (1 << 7),
  77. /* ATA register addresses */
  78. ADMA_REGS_CONTROL = 0x0e,
  79. ADMA_REGS_SECTOR_COUNT = 0x12,
  80. ADMA_REGS_LBA_LOW = 0x13,
  81. ADMA_REGS_LBA_MID = 0x14,
  82. ADMA_REGS_LBA_HIGH = 0x15,
  83. ADMA_REGS_DEVICE = 0x16,
  84. ADMA_REGS_COMMAND = 0x17,
  85. /* PCI device IDs */
  86. board_1841_idx = 0, /* ADMA 2-port controller */
  87. };
  88. typedef enum { adma_state_idle, adma_state_pkt, adma_state_mmio } adma_state_t;
  89. struct adma_port_priv {
  90. u8 *pkt;
  91. dma_addr_t pkt_dma;
  92. adma_state_t state;
  93. };
  94. static int adma_ata_init_one(struct pci_dev *pdev,
  95. const struct pci_device_id *ent);
  96. static int adma_port_start(struct ata_port *ap);
  97. static void adma_port_stop(struct ata_port *ap);
  98. static enum ata_completion_errors adma_qc_prep(struct ata_queued_cmd *qc);
  99. static unsigned int adma_qc_issue(struct ata_queued_cmd *qc);
  100. static int adma_check_atapi_dma(struct ata_queued_cmd *qc);
  101. static void adma_freeze(struct ata_port *ap);
  102. static void adma_thaw(struct ata_port *ap);
  103. static int adma_prereset(struct ata_link *link, unsigned long deadline);
  104. static struct scsi_host_template adma_ata_sht = {
  105. ATA_BASE_SHT(DRV_NAME),
  106. .sg_tablesize = LIBATA_MAX_PRD,
  107. .dma_boundary = ADMA_DMA_BOUNDARY,
  108. };
  109. static struct ata_port_operations adma_ata_ops = {
  110. .inherits = &ata_sff_port_ops,
  111. .lost_interrupt = ATA_OP_NULL,
  112. .check_atapi_dma = adma_check_atapi_dma,
  113. .qc_prep = adma_qc_prep,
  114. .qc_issue = adma_qc_issue,
  115. .freeze = adma_freeze,
  116. .thaw = adma_thaw,
  117. .prereset = adma_prereset,
  118. .port_start = adma_port_start,
  119. .port_stop = adma_port_stop,
  120. };
  121. static struct ata_port_info adma_port_info[] = {
  122. /* board_1841_idx */
  123. {
  124. .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_PIO_POLLING,
  125. .pio_mask = ATA_PIO4_ONLY,
  126. .udma_mask = ATA_UDMA4,
  127. .port_ops = &adma_ata_ops,
  128. },
  129. };
  130. static const struct pci_device_id adma_ata_pci_tbl[] = {
  131. { PCI_VDEVICE(PDC, 0x1841), board_1841_idx },
  132. { } /* terminate list */
  133. };
  134. static struct pci_driver adma_ata_pci_driver = {
  135. .name = DRV_NAME,
  136. .id_table = adma_ata_pci_tbl,
  137. .probe = adma_ata_init_one,
  138. .remove = ata_pci_remove_one,
  139. };
  140. static int adma_check_atapi_dma(struct ata_queued_cmd *qc)
  141. {
  142. return 1; /* ATAPI DMA not yet supported */
  143. }
  144. static void adma_reset_engine(struct ata_port *ap)
  145. {
  146. void __iomem *chan = ADMA_PORT_REGS(ap);
  147. /* reset ADMA to idle state */
  148. writew(aPIOMD4 | aNIEN | aRSTADM, chan + ADMA_CONTROL);
  149. udelay(2);
  150. writew(aPIOMD4, chan + ADMA_CONTROL);
  151. udelay(2);
  152. }
  153. static void adma_reinit_engine(struct ata_port *ap)
  154. {
  155. struct adma_port_priv *pp = ap->private_data;
  156. void __iomem *chan = ADMA_PORT_REGS(ap);
  157. /* mask/clear ATA interrupts */
  158. writeb(ATA_NIEN, ap->ioaddr.ctl_addr);
  159. ata_sff_check_status(ap);
  160. /* reset the ADMA engine */
  161. adma_reset_engine(ap);
  162. /* set in-FIFO threshold to 0x100 */
  163. writew(0x100, chan + ADMA_FIFO_IN);
  164. /* set CPB pointer */
  165. writel((u32)pp->pkt_dma, chan + ADMA_CPB_NEXT);
  166. /* set out-FIFO threshold to 0x100 */
  167. writew(0x100, chan + ADMA_FIFO_OUT);
  168. /* set CPB count */
  169. writew(1, chan + ADMA_CPB_COUNT);
  170. /* read/discard ADMA status */
  171. readb(chan + ADMA_STATUS);
  172. }
  173. static inline void adma_enter_reg_mode(struct ata_port *ap)
  174. {
  175. void __iomem *chan = ADMA_PORT_REGS(ap);
  176. writew(aPIOMD4, chan + ADMA_CONTROL);
  177. readb(chan + ADMA_STATUS); /* flush */
  178. }
  179. static void adma_freeze(struct ata_port *ap)
  180. {
  181. void __iomem *chan = ADMA_PORT_REGS(ap);
  182. /* mask/clear ATA interrupts */
  183. writeb(ATA_NIEN, ap->ioaddr.ctl_addr);
  184. ata_sff_check_status(ap);
  185. /* reset ADMA to idle state */
  186. writew(aPIOMD4 | aNIEN | aRSTADM, chan + ADMA_CONTROL);
  187. udelay(2);
  188. writew(aPIOMD4 | aNIEN, chan + ADMA_CONTROL);
  189. udelay(2);
  190. }
  191. static void adma_thaw(struct ata_port *ap)
  192. {
  193. adma_reinit_engine(ap);
  194. }
  195. static int adma_prereset(struct ata_link *link, unsigned long deadline)
  196. {
  197. struct ata_port *ap = link->ap;
  198. struct adma_port_priv *pp = ap->private_data;
  199. if (pp->state != adma_state_idle) /* healthy paranoia */
  200. pp->state = adma_state_mmio;
  201. adma_reinit_engine(ap);
  202. return ata_sff_prereset(link, deadline);
  203. }
  204. static int adma_fill_sg(struct ata_queued_cmd *qc)
  205. {
  206. struct scatterlist *sg;
  207. struct ata_port *ap = qc->ap;
  208. struct adma_port_priv *pp = ap->private_data;
  209. u8 *buf = pp->pkt, *last_buf = NULL;
  210. int i = (2 + buf[3]) * 8;
  211. u8 pFLAGS = pORD | ((qc->tf.flags & ATA_TFLAG_WRITE) ? pDIRO : 0);
  212. unsigned int si;
  213. for_each_sg(qc->sg, sg, qc->n_elem, si) {
  214. u32 addr;
  215. u32 len;
  216. addr = (u32)sg_dma_address(sg);
  217. *(__le32 *)(buf + i) = cpu_to_le32(addr);
  218. i += 4;
  219. len = sg_dma_len(sg) >> 3;
  220. *(__le32 *)(buf + i) = cpu_to_le32(len);
  221. i += 4;
  222. last_buf = &buf[i];
  223. buf[i++] = pFLAGS;
  224. buf[i++] = qc->dev->dma_mode & 0xf;
  225. buf[i++] = 0; /* pPKLW */
  226. buf[i++] = 0; /* reserved */
  227. *(__le32 *)(buf + i) =
  228. (pFLAGS & pEND) ? 0 : cpu_to_le32(pp->pkt_dma + i + 4);
  229. i += 4;
  230. VPRINTK("PRD[%u] = (0x%lX, 0x%X)\n", i/4,
  231. (unsigned long)addr, len);
  232. }
  233. if (likely(last_buf))
  234. *last_buf |= pEND;
  235. return i;
  236. }
  237. static enum ata_completion_errors adma_qc_prep(struct ata_queued_cmd *qc)
  238. {
  239. struct adma_port_priv *pp = qc->ap->private_data;
  240. u8 *buf = pp->pkt;
  241. u32 pkt_dma = (u32)pp->pkt_dma;
  242. int i = 0;
  243. VPRINTK("ENTER\n");
  244. adma_enter_reg_mode(qc->ap);
  245. if (qc->tf.protocol != ATA_PROT_DMA)
  246. return AC_ERR_OK;
  247. buf[i++] = 0; /* Response flags */
  248. buf[i++] = 0; /* reserved */
  249. buf[i++] = cVLD | cDAT | cIEN;
  250. i++; /* cLEN, gets filled in below */
  251. *(__le32 *)(buf+i) = cpu_to_le32(pkt_dma); /* cNCPB */
  252. i += 4; /* cNCPB */
  253. i += 4; /* cPRD, gets filled in below */
  254. buf[i++] = 0; /* reserved */
  255. buf[i++] = 0; /* reserved */
  256. buf[i++] = 0; /* reserved */
  257. buf[i++] = 0; /* reserved */
  258. /* ATA registers; must be a multiple of 4 */
  259. buf[i++] = qc->tf.device;
  260. buf[i++] = ADMA_REGS_DEVICE;
  261. if ((qc->tf.flags & ATA_TFLAG_LBA48)) {
  262. buf[i++] = qc->tf.hob_nsect;
  263. buf[i++] = ADMA_REGS_SECTOR_COUNT;
  264. buf[i++] = qc->tf.hob_lbal;
  265. buf[i++] = ADMA_REGS_LBA_LOW;
  266. buf[i++] = qc->tf.hob_lbam;
  267. buf[i++] = ADMA_REGS_LBA_MID;
  268. buf[i++] = qc->tf.hob_lbah;
  269. buf[i++] = ADMA_REGS_LBA_HIGH;
  270. }
  271. buf[i++] = qc->tf.nsect;
  272. buf[i++] = ADMA_REGS_SECTOR_COUNT;
  273. buf[i++] = qc->tf.lbal;
  274. buf[i++] = ADMA_REGS_LBA_LOW;
  275. buf[i++] = qc->tf.lbam;
  276. buf[i++] = ADMA_REGS_LBA_MID;
  277. buf[i++] = qc->tf.lbah;
  278. buf[i++] = ADMA_REGS_LBA_HIGH;
  279. buf[i++] = 0;
  280. buf[i++] = ADMA_REGS_CONTROL;
  281. buf[i++] = rIGN;
  282. buf[i++] = 0;
  283. buf[i++] = qc->tf.command;
  284. buf[i++] = ADMA_REGS_COMMAND | rEND;
  285. buf[3] = (i >> 3) - 2; /* cLEN */
  286. *(__le32 *)(buf+8) = cpu_to_le32(pkt_dma + i); /* cPRD */
  287. i = adma_fill_sg(qc);
  288. wmb(); /* flush PRDs and pkt to memory */
  289. #if 0
  290. /* dump out CPB + PRDs for debug */
  291. {
  292. int j, len = 0;
  293. static char obuf[2048];
  294. for (j = 0; j < i; ++j) {
  295. len += sprintf(obuf+len, "%02x ", buf[j]);
  296. if ((j & 7) == 7) {
  297. printk("%s\n", obuf);
  298. len = 0;
  299. }
  300. }
  301. if (len)
  302. printk("%s\n", obuf);
  303. }
  304. #endif
  305. return AC_ERR_OK;
  306. }
  307. static inline void adma_packet_start(struct ata_queued_cmd *qc)
  308. {
  309. struct ata_port *ap = qc->ap;
  310. void __iomem *chan = ADMA_PORT_REGS(ap);
  311. VPRINTK("ENTER, ap %p\n", ap);
  312. /* fire up the ADMA engine */
  313. writew(aPIOMD4 | aGO, chan + ADMA_CONTROL);
  314. }
  315. static unsigned int adma_qc_issue(struct ata_queued_cmd *qc)
  316. {
  317. struct adma_port_priv *pp = qc->ap->private_data;
  318. switch (qc->tf.protocol) {
  319. case ATA_PROT_DMA:
  320. pp->state = adma_state_pkt;
  321. adma_packet_start(qc);
  322. return 0;
  323. case ATAPI_PROT_DMA:
  324. BUG();
  325. break;
  326. default:
  327. break;
  328. }
  329. pp->state = adma_state_mmio;
  330. return ata_sff_qc_issue(qc);
  331. }
  332. static inline unsigned int adma_intr_pkt(struct ata_host *host)
  333. {
  334. unsigned int handled = 0, port_no;
  335. for (port_no = 0; port_no < host->n_ports; ++port_no) {
  336. struct ata_port *ap = host->ports[port_no];
  337. struct adma_port_priv *pp;
  338. struct ata_queued_cmd *qc;
  339. void __iomem *chan = ADMA_PORT_REGS(ap);
  340. u8 status = readb(chan + ADMA_STATUS);
  341. if (status == 0)
  342. continue;
  343. handled = 1;
  344. adma_enter_reg_mode(ap);
  345. pp = ap->private_data;
  346. if (!pp || pp->state != adma_state_pkt)
  347. continue;
  348. qc = ata_qc_from_tag(ap, ap->link.active_tag);
  349. if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING))) {
  350. if (status & aPERR)
  351. qc->err_mask |= AC_ERR_HOST_BUS;
  352. else if ((status & (aPSD | aUIRQ)))
  353. qc->err_mask |= AC_ERR_OTHER;
  354. if (pp->pkt[0] & cATERR)
  355. qc->err_mask |= AC_ERR_DEV;
  356. else if (pp->pkt[0] != cDONE)
  357. qc->err_mask |= AC_ERR_OTHER;
  358. if (!qc->err_mask)
  359. ata_qc_complete(qc);
  360. else {
  361. struct ata_eh_info *ehi = &ap->link.eh_info;
  362. ata_ehi_clear_desc(ehi);
  363. ata_ehi_push_desc(ehi,
  364. "ADMA-status 0x%02X", status);
  365. ata_ehi_push_desc(ehi,
  366. "pkt[0] 0x%02X", pp->pkt[0]);
  367. if (qc->err_mask == AC_ERR_DEV)
  368. ata_port_abort(ap);
  369. else
  370. ata_port_freeze(ap);
  371. }
  372. }
  373. }
  374. return handled;
  375. }
  376. static inline unsigned int adma_intr_mmio(struct ata_host *host)
  377. {
  378. unsigned int handled = 0, port_no;
  379. for (port_no = 0; port_no < host->n_ports; ++port_no) {
  380. struct ata_port *ap = host->ports[port_no];
  381. struct adma_port_priv *pp = ap->private_data;
  382. struct ata_queued_cmd *qc;
  383. if (!pp || pp->state != adma_state_mmio)
  384. continue;
  385. qc = ata_qc_from_tag(ap, ap->link.active_tag);
  386. if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING))) {
  387. /* check main status, clearing INTRQ */
  388. u8 status = ata_sff_check_status(ap);
  389. if ((status & ATA_BUSY))
  390. continue;
  391. DPRINTK("ata%u: protocol %d (dev_stat 0x%X)\n",
  392. ap->print_id, qc->tf.protocol, status);
  393. /* complete taskfile transaction */
  394. pp->state = adma_state_idle;
  395. qc->err_mask |= ac_err_mask(status);
  396. if (!qc->err_mask)
  397. ata_qc_complete(qc);
  398. else {
  399. struct ata_eh_info *ehi = &ap->link.eh_info;
  400. ata_ehi_clear_desc(ehi);
  401. ata_ehi_push_desc(ehi, "status 0x%02X", status);
  402. if (qc->err_mask == AC_ERR_DEV)
  403. ata_port_abort(ap);
  404. else
  405. ata_port_freeze(ap);
  406. }
  407. handled = 1;
  408. }
  409. }
  410. return handled;
  411. }
  412. static irqreturn_t adma_intr(int irq, void *dev_instance)
  413. {
  414. struct ata_host *host = dev_instance;
  415. unsigned int handled = 0;
  416. VPRINTK("ENTER\n");
  417. spin_lock(&host->lock);
  418. handled = adma_intr_pkt(host) | adma_intr_mmio(host);
  419. spin_unlock(&host->lock);
  420. VPRINTK("EXIT\n");
  421. return IRQ_RETVAL(handled);
  422. }
  423. static void adma_ata_setup_port(struct ata_ioports *port, void __iomem *base)
  424. {
  425. port->cmd_addr =
  426. port->data_addr = base + 0x000;
  427. port->error_addr =
  428. port->feature_addr = base + 0x004;
  429. port->nsect_addr = base + 0x008;
  430. port->lbal_addr = base + 0x00c;
  431. port->lbam_addr = base + 0x010;
  432. port->lbah_addr = base + 0x014;
  433. port->device_addr = base + 0x018;
  434. port->status_addr =
  435. port->command_addr = base + 0x01c;
  436. port->altstatus_addr =
  437. port->ctl_addr = base + 0x038;
  438. }
  439. static int adma_port_start(struct ata_port *ap)
  440. {
  441. struct device *dev = ap->host->dev;
  442. struct adma_port_priv *pp;
  443. adma_enter_reg_mode(ap);
  444. pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
  445. if (!pp)
  446. return -ENOMEM;
  447. pp->pkt = dmam_alloc_coherent(dev, ADMA_PKT_BYTES, &pp->pkt_dma,
  448. GFP_KERNEL);
  449. if (!pp->pkt)
  450. return -ENOMEM;
  451. /* paranoia? */
  452. if ((pp->pkt_dma & 7) != 0) {
  453. printk(KERN_ERR "bad alignment for pp->pkt_dma: %08x\n",
  454. (u32)pp->pkt_dma);
  455. return -ENOMEM;
  456. }
  457. ap->private_data = pp;
  458. adma_reinit_engine(ap);
  459. return 0;
  460. }
  461. static void adma_port_stop(struct ata_port *ap)
  462. {
  463. adma_reset_engine(ap);
  464. }
  465. static void adma_host_init(struct ata_host *host, unsigned int chip_id)
  466. {
  467. unsigned int port_no;
  468. /* enable/lock aGO operation */
  469. writeb(7, host->iomap[ADMA_MMIO_BAR] + ADMA_MODE_LOCK);
  470. /* reset the ADMA logic */
  471. for (port_no = 0; port_no < ADMA_PORTS; ++port_no)
  472. adma_reset_engine(host->ports[port_no]);
  473. }
  474. static int adma_ata_init_one(struct pci_dev *pdev,
  475. const struct pci_device_id *ent)
  476. {
  477. unsigned int board_idx = (unsigned int) ent->driver_data;
  478. const struct ata_port_info *ppi[] = { &adma_port_info[board_idx], NULL };
  479. struct ata_host *host;
  480. void __iomem *mmio_base;
  481. int rc, port_no;
  482. ata_print_version_once(&pdev->dev, DRV_VERSION);
  483. /* alloc host */
  484. host = ata_host_alloc_pinfo(&pdev->dev, ppi, ADMA_PORTS);
  485. if (!host)
  486. return -ENOMEM;
  487. /* acquire resources and fill host */
  488. rc = pcim_enable_device(pdev);
  489. if (rc)
  490. return rc;
  491. if ((pci_resource_flags(pdev, 4) & IORESOURCE_MEM) == 0)
  492. return -ENODEV;
  493. rc = pcim_iomap_regions(pdev, 1 << ADMA_MMIO_BAR, DRV_NAME);
  494. if (rc)
  495. return rc;
  496. host->iomap = pcim_iomap_table(pdev);
  497. mmio_base = host->iomap[ADMA_MMIO_BAR];
  498. rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
  499. if (rc) {
  500. dev_err(&pdev->dev, "32-bit DMA enable failed\n");
  501. return rc;
  502. }
  503. for (port_no = 0; port_no < ADMA_PORTS; ++port_no) {
  504. struct ata_port *ap = host->ports[port_no];
  505. void __iomem *port_base = ADMA_ATA_REGS(mmio_base, port_no);
  506. unsigned int offset = port_base - mmio_base;
  507. adma_ata_setup_port(&ap->ioaddr, port_base);
  508. ata_port_pbar_desc(ap, ADMA_MMIO_BAR, -1, "mmio");
  509. ata_port_pbar_desc(ap, ADMA_MMIO_BAR, offset, "port");
  510. }
  511. /* initialize adapter */
  512. adma_host_init(host, board_idx);
  513. pci_set_master(pdev);
  514. return ata_host_activate(host, pdev->irq, adma_intr, IRQF_SHARED,
  515. &adma_ata_sht);
  516. }
  517. module_pci_driver(adma_ata_pci_driver);
  518. MODULE_AUTHOR("Mark Lord");
  519. MODULE_DESCRIPTION("Pacific Digital Corporation ADMA low-level driver");
  520. MODULE_LICENSE("GPL");
  521. MODULE_DEVICE_TABLE(pci, adma_ata_pci_tbl);
  522. MODULE_VERSION(DRV_VERSION);