pata_via.c 20 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720
  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * pata_via.c - VIA PATA for new ATA layer
  4. * (C) 2005-2006 Red Hat Inc
  5. *
  6. * Documentation
  7. * Most chipset documentation available under NDA only
  8. *
  9. * VIA version guide
  10. * VIA VT82C561 - early design, uses ata_generic currently
  11. * VIA VT82C576 - MWDMA, 33Mhz
  12. * VIA VT82C586 - MWDMA, 33Mhz
  13. * VIA VT82C586a - Added UDMA to 33Mhz
  14. * VIA VT82C586b - UDMA33
  15. * VIA VT82C596a - Nonfunctional UDMA66
  16. * VIA VT82C596b - Working UDMA66
  17. * VIA VT82C686 - Nonfunctional UDMA66
  18. * VIA VT82C686a - Working UDMA66
  19. * VIA VT82C686b - Updated to UDMA100
  20. * VIA VT8231 - UDMA100
  21. * VIA VT8233 - UDMA100
  22. * VIA VT8233a - UDMA133
  23. * VIA VT8233c - UDMA100
  24. * VIA VT8235 - UDMA133
  25. * VIA VT8237 - UDMA133
  26. * VIA VT8237A - UDMA133
  27. * VIA VT8237S - UDMA133
  28. * VIA VT8251 - UDMA133
  29. *
  30. * Most registers remain compatible across chips. Others start reserved
  31. * and acquire sensible semantics if set to 1 (eg cable detect). A few
  32. * exceptions exist, notably around the FIFO settings.
  33. *
  34. * One additional quirk of the VIA design is that like ALi they use few
  35. * PCI IDs for a lot of chips.
  36. *
  37. * Based heavily on:
  38. *
  39. * Version 3.38
  40. *
  41. * VIA IDE driver for Linux. Supported southbridges:
  42. *
  43. * vt82c576, vt82c586, vt82c586a, vt82c586b, vt82c596a, vt82c596b,
  44. * vt82c686, vt82c686a, vt82c686b, vt8231, vt8233, vt8233c, vt8233a,
  45. * vt8235, vt8237
  46. *
  47. * Copyright (c) 2000-2002 Vojtech Pavlik
  48. *
  49. * Based on the work of:
  50. * Michel Aubry
  51. * Jeff Garzik
  52. * Andre Hedrick
  53. */
  54. #include <linux/kernel.h>
  55. #include <linux/module.h>
  56. #include <linux/pci.h>
  57. #include <linux/blkdev.h>
  58. #include <linux/delay.h>
  59. #include <linux/gfp.h>
  60. #include <scsi/scsi_host.h>
  61. #include <linux/libata.h>
  62. #include <linux/dmi.h>
  63. #define DRV_NAME "pata_via"
  64. #define DRV_VERSION "0.3.4"
  65. enum {
  66. VIA_BAD_PREQ = 0x01, /* Crashes if PREQ# till DDACK# set */
  67. VIA_BAD_CLK66 = 0x02, /* 66 MHz clock doesn't work correctly */
  68. VIA_SET_FIFO = 0x04, /* Needs to have FIFO split set */
  69. VIA_NO_UNMASK = 0x08, /* Doesn't work with IRQ unmasking on */
  70. VIA_BAD_ID = 0x10, /* Has wrong vendor ID (0x1107) */
  71. VIA_BAD_AST = 0x20, /* Don't touch Address Setup Timing */
  72. VIA_NO_ENABLES = 0x40, /* Has no enablebits */
  73. VIA_SATA_PATA = 0x80, /* SATA/PATA combined configuration */
  74. };
  75. enum {
  76. VIA_IDFLAG_SINGLE = (1 << 0), /* single channel controller) */
  77. };
  78. /*
  79. * VIA SouthBridge chips.
  80. */
  81. static const struct via_isa_bridge {
  82. const char *name;
  83. u16 id;
  84. u8 rev_min;
  85. u8 rev_max;
  86. u8 udma_mask;
  87. u8 flags;
  88. } via_isa_bridges[] = {
  89. { "vx855", PCI_DEVICE_ID_VIA_VX855, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST | VIA_SATA_PATA },
  90. { "vx800", PCI_DEVICE_ID_VIA_VX800, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST | VIA_SATA_PATA },
  91. { "vt8261", PCI_DEVICE_ID_VIA_8261, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
  92. { "vt8237s", PCI_DEVICE_ID_VIA_8237S, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
  93. { "vt8251", PCI_DEVICE_ID_VIA_8251, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
  94. { "cx700", PCI_DEVICE_ID_VIA_CX700, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST | VIA_SATA_PATA },
  95. { "vt6410", PCI_DEVICE_ID_VIA_6410, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST | VIA_NO_ENABLES },
  96. { "vt6415", PCI_DEVICE_ID_VIA_6415, 0x00, 0xff, ATA_UDMA6, VIA_BAD_AST | VIA_NO_ENABLES },
  97. { "vt8237a", PCI_DEVICE_ID_VIA_8237A, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
  98. { "vt8237", PCI_DEVICE_ID_VIA_8237, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
  99. { "vt8235", PCI_DEVICE_ID_VIA_8235, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
  100. { "vt8233a", PCI_DEVICE_ID_VIA_8233A, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
  101. { "vt8233c", PCI_DEVICE_ID_VIA_8233C_0, 0x00, 0x2f, ATA_UDMA5, },
  102. { "vt8233", PCI_DEVICE_ID_VIA_8233_0, 0x00, 0x2f, ATA_UDMA5, },
  103. { "vt8231", PCI_DEVICE_ID_VIA_8231, 0x00, 0x2f, ATA_UDMA5, },
  104. { "vt82c686b", PCI_DEVICE_ID_VIA_82C686, 0x40, 0x4f, ATA_UDMA5, },
  105. { "vt82c686a", PCI_DEVICE_ID_VIA_82C686, 0x10, 0x2f, ATA_UDMA4, },
  106. { "vt82c686", PCI_DEVICE_ID_VIA_82C686, 0x00, 0x0f, ATA_UDMA2, VIA_BAD_CLK66 },
  107. { "vt82c596b", PCI_DEVICE_ID_VIA_82C596, 0x10, 0x2f, ATA_UDMA4, },
  108. { "vt82c596a", PCI_DEVICE_ID_VIA_82C596, 0x00, 0x0f, ATA_UDMA2, VIA_BAD_CLK66 },
  109. { "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x47, 0x4f, ATA_UDMA2, VIA_SET_FIFO },
  110. { "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x40, 0x46, ATA_UDMA2, VIA_SET_FIFO | VIA_BAD_PREQ },
  111. { "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x30, 0x3f, ATA_UDMA2, VIA_SET_FIFO },
  112. { "vt82c586a", PCI_DEVICE_ID_VIA_82C586_0, 0x20, 0x2f, ATA_UDMA2, VIA_SET_FIFO },
  113. { "vt82c586", PCI_DEVICE_ID_VIA_82C586_0, 0x00, 0x0f, 0x00, VIA_SET_FIFO },
  114. { "vt82c576", PCI_DEVICE_ID_VIA_82C576, 0x00, 0x2f, 0x00, VIA_SET_FIFO | VIA_NO_UNMASK },
  115. { "vt82c576", PCI_DEVICE_ID_VIA_82C576, 0x00, 0x2f, 0x00, VIA_SET_FIFO | VIA_NO_UNMASK | VIA_BAD_ID },
  116. { "vtxxxx", PCI_DEVICE_ID_VIA_ANON, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
  117. { NULL }
  118. };
  119. static const struct dmi_system_id no_atapi_dma_dmi_table[] = {
  120. {
  121. .ident = "AVERATEC 3200",
  122. .matches = {
  123. DMI_MATCH(DMI_BOARD_VENDOR, "AVERATEC"),
  124. DMI_MATCH(DMI_BOARD_NAME, "3200"),
  125. },
  126. },
  127. { }
  128. };
  129. struct via_port {
  130. u8 cached_device;
  131. };
  132. /*
  133. * Cable special cases
  134. */
  135. static const struct dmi_system_id cable_dmi_table[] = {
  136. {
  137. .ident = "Acer Ferrari 3400",
  138. .matches = {
  139. DMI_MATCH(DMI_BOARD_VENDOR, "Acer,Inc."),
  140. DMI_MATCH(DMI_BOARD_NAME, "Ferrari 3400"),
  141. },
  142. },
  143. { }
  144. };
  145. static int via_cable_override(struct pci_dev *pdev)
  146. {
  147. /* Systems by DMI */
  148. if (dmi_check_system(cable_dmi_table))
  149. return 1;
  150. /* Arima W730-K8/Targa Visionary 811/... */
  151. if (pdev->subsystem_vendor == 0x161F && pdev->subsystem_device == 0x2032)
  152. return 1;
  153. return 0;
  154. }
  155. /**
  156. * via_cable_detect - cable detection
  157. * @ap: ATA port
  158. *
  159. * Perform cable detection. Actually for the VIA case the BIOS
  160. * already did this for us. We read the values provided by the
  161. * BIOS. If you are using an 8235 in a non-PC configuration you
  162. * may need to update this code.
  163. *
  164. * Hotplug also impacts on this.
  165. */
  166. static int via_cable_detect(struct ata_port *ap) {
  167. const struct via_isa_bridge *config = ap->host->private_data;
  168. struct pci_dev *pdev = to_pci_dev(ap->host->dev);
  169. u32 ata66;
  170. if (via_cable_override(pdev))
  171. return ATA_CBL_PATA40_SHORT;
  172. if ((config->flags & VIA_SATA_PATA) && ap->port_no == 0)
  173. return ATA_CBL_SATA;
  174. /* Early chips are 40 wire */
  175. if (config->udma_mask < ATA_UDMA4)
  176. return ATA_CBL_PATA40;
  177. /* UDMA 66 chips have only drive side logic */
  178. else if (config->udma_mask < ATA_UDMA5)
  179. return ATA_CBL_PATA_UNK;
  180. /* UDMA 100 or later */
  181. pci_read_config_dword(pdev, 0x50, &ata66);
  182. /* Check both the drive cable reporting bits, we might not have
  183. two drives */
  184. if (ata66 & (0x10100000 >> (16 * ap->port_no)))
  185. return ATA_CBL_PATA80;
  186. /* Check with ACPI so we can spot BIOS reported SATA bridges */
  187. if (ata_acpi_init_gtm(ap) &&
  188. ata_acpi_cbl_80wire(ap, ata_acpi_init_gtm(ap)))
  189. return ATA_CBL_PATA80;
  190. return ATA_CBL_PATA40;
  191. }
  192. static int via_pre_reset(struct ata_link *link, unsigned long deadline)
  193. {
  194. struct ata_port *ap = link->ap;
  195. const struct via_isa_bridge *config = ap->host->private_data;
  196. if (!(config->flags & VIA_NO_ENABLES)) {
  197. static const struct pci_bits via_enable_bits[] = {
  198. { 0x40, 1, 0x02, 0x02 },
  199. { 0x40, 1, 0x01, 0x01 }
  200. };
  201. struct pci_dev *pdev = to_pci_dev(ap->host->dev);
  202. if (!pci_test_config_bits(pdev, &via_enable_bits[ap->port_no]))
  203. return -ENOENT;
  204. }
  205. return ata_sff_prereset(link, deadline);
  206. }
  207. /**
  208. * via_do_set_mode - set transfer mode data
  209. * @ap: ATA interface
  210. * @adev: ATA device
  211. * @mode: ATA mode being programmed
  212. * @set_ast: Set to program address setup
  213. * @udma_type: UDMA mode/format of registers
  214. *
  215. * Program the VIA registers for DMA and PIO modes. Uses the ata timing
  216. * support in order to compute modes.
  217. *
  218. * FIXME: Hotplug will require we serialize multiple mode changes
  219. * on the two channels.
  220. */
  221. static void via_do_set_mode(struct ata_port *ap, struct ata_device *adev,
  222. int mode, int set_ast, int udma_type)
  223. {
  224. struct pci_dev *pdev = to_pci_dev(ap->host->dev);
  225. struct ata_device *peer = ata_dev_pair(adev);
  226. struct ata_timing t, p;
  227. static int via_clock = 33333; /* Bus clock in kHZ */
  228. unsigned long T = 1000000000 / via_clock;
  229. unsigned long UT = T;
  230. int ut;
  231. int offset = 3 - (2*ap->port_no) - adev->devno;
  232. switch (udma_type) {
  233. case ATA_UDMA4:
  234. UT = T / 2; break;
  235. case ATA_UDMA5:
  236. UT = T / 3; break;
  237. case ATA_UDMA6:
  238. UT = T / 4; break;
  239. }
  240. /* Calculate the timing values we require */
  241. ata_timing_compute(adev, mode, &t, T, UT);
  242. /* We share 8bit timing so we must merge the constraints */
  243. if (peer) {
  244. if (peer->pio_mode) {
  245. ata_timing_compute(peer, peer->pio_mode, &p, T, UT);
  246. ata_timing_merge(&p, &t, &t, ATA_TIMING_8BIT);
  247. }
  248. }
  249. /* Address setup is programmable but breaks on UDMA133 setups */
  250. if (set_ast) {
  251. u8 setup; /* 2 bits per drive */
  252. int shift = 2 * offset;
  253. pci_read_config_byte(pdev, 0x4C, &setup);
  254. setup &= ~(3 << shift);
  255. setup |= (clamp_val(t.setup, 1, 4) - 1) << shift;
  256. pci_write_config_byte(pdev, 0x4C, setup);
  257. }
  258. /* Load the PIO mode bits */
  259. pci_write_config_byte(pdev, 0x4F - ap->port_no,
  260. ((clamp_val(t.act8b, 1, 16) - 1) << 4) | (clamp_val(t.rec8b, 1, 16) - 1));
  261. pci_write_config_byte(pdev, 0x48 + offset,
  262. ((clamp_val(t.active, 1, 16) - 1) << 4) | (clamp_val(t.recover, 1, 16) - 1));
  263. /* Load the UDMA bits according to type */
  264. switch (udma_type) {
  265. case ATA_UDMA2:
  266. default:
  267. ut = t.udma ? (0xe0 | (clamp_val(t.udma, 2, 5) - 2)) : 0x03;
  268. break;
  269. case ATA_UDMA4:
  270. ut = t.udma ? (0xe8 | (clamp_val(t.udma, 2, 9) - 2)) : 0x0f;
  271. break;
  272. case ATA_UDMA5:
  273. ut = t.udma ? (0xe0 | (clamp_val(t.udma, 2, 9) - 2)) : 0x07;
  274. break;
  275. case ATA_UDMA6:
  276. ut = t.udma ? (0xe0 | (clamp_val(t.udma, 2, 9) - 2)) : 0x07;
  277. break;
  278. }
  279. /* Set UDMA unless device is not UDMA capable */
  280. if (udma_type) {
  281. u8 udma_etc;
  282. pci_read_config_byte(pdev, 0x50 + offset, &udma_etc);
  283. /* clear transfer mode bit */
  284. udma_etc &= ~0x20;
  285. if (t.udma) {
  286. /* preserve 80-wire cable detection bit */
  287. udma_etc &= 0x10;
  288. udma_etc |= ut;
  289. }
  290. pci_write_config_byte(pdev, 0x50 + offset, udma_etc);
  291. }
  292. }
  293. static void via_set_piomode(struct ata_port *ap, struct ata_device *adev)
  294. {
  295. const struct via_isa_bridge *config = ap->host->private_data;
  296. int set_ast = (config->flags & VIA_BAD_AST) ? 0 : 1;
  297. via_do_set_mode(ap, adev, adev->pio_mode, set_ast, config->udma_mask);
  298. }
  299. static void via_set_dmamode(struct ata_port *ap, struct ata_device *adev)
  300. {
  301. const struct via_isa_bridge *config = ap->host->private_data;
  302. int set_ast = (config->flags & VIA_BAD_AST) ? 0 : 1;
  303. via_do_set_mode(ap, adev, adev->dma_mode, set_ast, config->udma_mask);
  304. }
  305. /**
  306. * via_mode_filter - filter buggy device/mode pairs
  307. * @dev: ATA device
  308. * @mask: Mode bitmask
  309. *
  310. * We need to apply some minimal filtering for old controllers and at least
  311. * one breed of Transcend SSD. Return the updated mask.
  312. */
  313. static unsigned long via_mode_filter(struct ata_device *dev, unsigned long mask)
  314. {
  315. struct ata_host *host = dev->link->ap->host;
  316. const struct via_isa_bridge *config = host->private_data;
  317. unsigned char model_num[ATA_ID_PROD_LEN + 1];
  318. if (config->id == PCI_DEVICE_ID_VIA_82C586_0) {
  319. ata_id_c_string(dev->id, model_num, ATA_ID_PROD, sizeof(model_num));
  320. if (strcmp(model_num, "TS64GSSD25-M") == 0) {
  321. ata_dev_warn(dev,
  322. "disabling UDMA mode due to reported lockups with this device\n");
  323. mask &= ~ ATA_MASK_UDMA;
  324. }
  325. }
  326. if (dev->class == ATA_DEV_ATAPI &&
  327. dmi_check_system(no_atapi_dma_dmi_table)) {
  328. ata_dev_warn(dev, "controller locks up on ATAPI DMA, forcing PIO\n");
  329. mask &= ATA_MASK_PIO;
  330. }
  331. return mask;
  332. }
  333. /**
  334. * via_tf_load - send taskfile registers to host controller
  335. * @ap: Port to which output is sent
  336. * @tf: ATA taskfile register set
  337. *
  338. * Outputs ATA taskfile to standard ATA host controller.
  339. *
  340. * Note: This is to fix the internal bug of via chipsets, which
  341. * will reset the device register after changing the IEN bit on
  342. * ctl register
  343. */
  344. static void via_tf_load(struct ata_port *ap, const struct ata_taskfile *tf)
  345. {
  346. struct ata_ioports *ioaddr = &ap->ioaddr;
  347. struct via_port *vp = ap->private_data;
  348. unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
  349. int newctl = 0;
  350. if (tf->ctl != ap->last_ctl) {
  351. iowrite8(tf->ctl, ioaddr->ctl_addr);
  352. ap->last_ctl = tf->ctl;
  353. ata_wait_idle(ap);
  354. newctl = 1;
  355. }
  356. if (tf->flags & ATA_TFLAG_DEVICE) {
  357. iowrite8(tf->device, ioaddr->device_addr);
  358. vp->cached_device = tf->device;
  359. } else if (newctl)
  360. iowrite8(vp->cached_device, ioaddr->device_addr);
  361. if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
  362. WARN_ON_ONCE(!ioaddr->ctl_addr);
  363. iowrite8(tf->hob_feature, ioaddr->feature_addr);
  364. iowrite8(tf->hob_nsect, ioaddr->nsect_addr);
  365. iowrite8(tf->hob_lbal, ioaddr->lbal_addr);
  366. iowrite8(tf->hob_lbam, ioaddr->lbam_addr);
  367. iowrite8(tf->hob_lbah, ioaddr->lbah_addr);
  368. VPRINTK("hob: feat 0x%X nsect 0x%X, lba 0x%X 0x%X 0x%X\n",
  369. tf->hob_feature,
  370. tf->hob_nsect,
  371. tf->hob_lbal,
  372. tf->hob_lbam,
  373. tf->hob_lbah);
  374. }
  375. if (is_addr) {
  376. iowrite8(tf->feature, ioaddr->feature_addr);
  377. iowrite8(tf->nsect, ioaddr->nsect_addr);
  378. iowrite8(tf->lbal, ioaddr->lbal_addr);
  379. iowrite8(tf->lbam, ioaddr->lbam_addr);
  380. iowrite8(tf->lbah, ioaddr->lbah_addr);
  381. VPRINTK("feat 0x%X nsect 0x%X lba 0x%X 0x%X 0x%X\n",
  382. tf->feature,
  383. tf->nsect,
  384. tf->lbal,
  385. tf->lbam,
  386. tf->lbah);
  387. }
  388. ata_wait_idle(ap);
  389. }
  390. static int via_port_start(struct ata_port *ap)
  391. {
  392. struct via_port *vp;
  393. struct pci_dev *pdev = to_pci_dev(ap->host->dev);
  394. int ret = ata_bmdma_port_start(ap);
  395. if (ret < 0)
  396. return ret;
  397. vp = devm_kzalloc(&pdev->dev, sizeof(struct via_port), GFP_KERNEL);
  398. if (vp == NULL)
  399. return -ENOMEM;
  400. ap->private_data = vp;
  401. return 0;
  402. }
  403. static struct scsi_host_template via_sht = {
  404. ATA_BMDMA_SHT(DRV_NAME),
  405. };
  406. static struct ata_port_operations via_port_ops = {
  407. .inherits = &ata_bmdma_port_ops,
  408. .cable_detect = via_cable_detect,
  409. .set_piomode = via_set_piomode,
  410. .set_dmamode = via_set_dmamode,
  411. .prereset = via_pre_reset,
  412. .sff_tf_load = via_tf_load,
  413. .port_start = via_port_start,
  414. .mode_filter = via_mode_filter,
  415. };
  416. static struct ata_port_operations via_port_ops_noirq = {
  417. .inherits = &via_port_ops,
  418. .sff_data_xfer = ata_sff_data_xfer32,
  419. };
  420. /**
  421. * via_config_fifo - set up the FIFO
  422. * @pdev: PCI device
  423. * @flags: configuration flags
  424. *
  425. * Set the FIFO properties for this device if necessary. Used both on
  426. * set up and on and the resume path
  427. */
  428. static void via_config_fifo(struct pci_dev *pdev, unsigned int flags)
  429. {
  430. u8 enable;
  431. /* 0x40 low bits indicate enabled channels */
  432. pci_read_config_byte(pdev, 0x40 , &enable);
  433. enable &= 3;
  434. if (flags & VIA_SET_FIFO) {
  435. static const u8 fifo_setting[4] = {0x00, 0x60, 0x00, 0x20};
  436. u8 fifo;
  437. pci_read_config_byte(pdev, 0x43, &fifo);
  438. /* Clear PREQ# until DDACK# for errata */
  439. if (flags & VIA_BAD_PREQ)
  440. fifo &= 0x7F;
  441. else
  442. fifo &= 0x9f;
  443. /* Turn on FIFO for enabled channels */
  444. fifo |= fifo_setting[enable];
  445. pci_write_config_byte(pdev, 0x43, fifo);
  446. }
  447. }
  448. static void via_fixup(struct pci_dev *pdev, const struct via_isa_bridge *config)
  449. {
  450. u32 timing;
  451. /* Initialise the FIFO for the enabled channels. */
  452. via_config_fifo(pdev, config->flags);
  453. if (config->udma_mask == ATA_UDMA4) {
  454. /* The 66 MHz devices require we enable the clock */
  455. pci_read_config_dword(pdev, 0x50, &timing);
  456. timing |= 0x80008;
  457. pci_write_config_dword(pdev, 0x50, timing);
  458. }
  459. if (config->flags & VIA_BAD_CLK66) {
  460. /* Disable the 66MHz clock on problem devices */
  461. pci_read_config_dword(pdev, 0x50, &timing);
  462. timing &= ~0x80008;
  463. pci_write_config_dword(pdev, 0x50, timing);
  464. }
  465. }
  466. /**
  467. * via_init_one - discovery callback
  468. * @pdev: PCI device
  469. * @id: PCI table info
  470. *
  471. * A VIA IDE interface has been discovered. Figure out what revision
  472. * and perform configuration work before handing it to the ATA layer
  473. */
  474. static int via_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
  475. {
  476. /* Early VIA without UDMA support */
  477. static const struct ata_port_info via_mwdma_info = {
  478. .flags = ATA_FLAG_SLAVE_POSS,
  479. .pio_mask = ATA_PIO4,
  480. .mwdma_mask = ATA_MWDMA2,
  481. .port_ops = &via_port_ops
  482. };
  483. /* Ditto with IRQ masking required */
  484. static const struct ata_port_info via_mwdma_info_borked = {
  485. .flags = ATA_FLAG_SLAVE_POSS,
  486. .pio_mask = ATA_PIO4,
  487. .mwdma_mask = ATA_MWDMA2,
  488. .port_ops = &via_port_ops_noirq,
  489. };
  490. /* VIA UDMA 33 devices (and borked 66) */
  491. static const struct ata_port_info via_udma33_info = {
  492. .flags = ATA_FLAG_SLAVE_POSS,
  493. .pio_mask = ATA_PIO4,
  494. .mwdma_mask = ATA_MWDMA2,
  495. .udma_mask = ATA_UDMA2,
  496. .port_ops = &via_port_ops
  497. };
  498. /* VIA UDMA 66 devices */
  499. static const struct ata_port_info via_udma66_info = {
  500. .flags = ATA_FLAG_SLAVE_POSS,
  501. .pio_mask = ATA_PIO4,
  502. .mwdma_mask = ATA_MWDMA2,
  503. .udma_mask = ATA_UDMA4,
  504. .port_ops = &via_port_ops
  505. };
  506. /* VIA UDMA 100 devices */
  507. static const struct ata_port_info via_udma100_info = {
  508. .flags = ATA_FLAG_SLAVE_POSS,
  509. .pio_mask = ATA_PIO4,
  510. .mwdma_mask = ATA_MWDMA2,
  511. .udma_mask = ATA_UDMA5,
  512. .port_ops = &via_port_ops
  513. };
  514. /* UDMA133 with bad AST (All current 133) */
  515. static const struct ata_port_info via_udma133_info = {
  516. .flags = ATA_FLAG_SLAVE_POSS,
  517. .pio_mask = ATA_PIO4,
  518. .mwdma_mask = ATA_MWDMA2,
  519. .udma_mask = ATA_UDMA6, /* FIXME: should check north bridge */
  520. .port_ops = &via_port_ops
  521. };
  522. const struct ata_port_info *ppi[] = { NULL, NULL };
  523. struct pci_dev *isa;
  524. const struct via_isa_bridge *config;
  525. u8 enable;
  526. unsigned long flags = id->driver_data;
  527. int rc;
  528. ata_print_version_once(&pdev->dev, DRV_VERSION);
  529. rc = pcim_enable_device(pdev);
  530. if (rc)
  531. return rc;
  532. if (flags & VIA_IDFLAG_SINGLE)
  533. ppi[1] = &ata_dummy_port_info;
  534. /* To find out how the IDE will behave and what features we
  535. actually have to look at the bridge not the IDE controller */
  536. for (config = via_isa_bridges; config->id != PCI_DEVICE_ID_VIA_ANON;
  537. config++)
  538. if ((isa = pci_get_device(PCI_VENDOR_ID_VIA +
  539. !!(config->flags & VIA_BAD_ID),
  540. config->id, NULL))) {
  541. u8 rev = isa->revision;
  542. pci_dev_put(isa);
  543. if ((id->device == 0x0415 || id->device == 0x3164) &&
  544. (config->id != id->device))
  545. continue;
  546. if (rev >= config->rev_min && rev <= config->rev_max)
  547. break;
  548. }
  549. if (!(config->flags & VIA_NO_ENABLES)) {
  550. /* 0x40 low bits indicate enabled channels */
  551. pci_read_config_byte(pdev, 0x40 , &enable);
  552. enable &= 3;
  553. if (enable == 0)
  554. return -ENODEV;
  555. }
  556. /* Clock set up */
  557. switch (config->udma_mask) {
  558. case 0x00:
  559. if (config->flags & VIA_NO_UNMASK)
  560. ppi[0] = &via_mwdma_info_borked;
  561. else
  562. ppi[0] = &via_mwdma_info;
  563. break;
  564. case ATA_UDMA2:
  565. ppi[0] = &via_udma33_info;
  566. break;
  567. case ATA_UDMA4:
  568. ppi[0] = &via_udma66_info;
  569. break;
  570. case ATA_UDMA5:
  571. ppi[0] = &via_udma100_info;
  572. break;
  573. case ATA_UDMA6:
  574. ppi[0] = &via_udma133_info;
  575. break;
  576. default:
  577. WARN_ON(1);
  578. return -ENODEV;
  579. }
  580. via_fixup(pdev, config);
  581. /* We have established the device type, now fire it up */
  582. return ata_pci_bmdma_init_one(pdev, ppi, &via_sht, (void *)config, 0);
  583. }
  584. #ifdef CONFIG_PM_SLEEP
  585. /**
  586. * via_reinit_one - reinit after resume
  587. * @pdev; PCI device
  588. *
  589. * Called when the VIA PATA device is resumed. We must then
  590. * reconfigure the fifo and other setup we may have altered. In
  591. * addition the kernel needs to have the resume methods on PCI
  592. * quirk supported.
  593. */
  594. static int via_reinit_one(struct pci_dev *pdev)
  595. {
  596. struct ata_host *host = pci_get_drvdata(pdev);
  597. int rc;
  598. rc = ata_pci_device_do_resume(pdev);
  599. if (rc)
  600. return rc;
  601. via_fixup(pdev, host->private_data);
  602. ata_host_resume(host);
  603. return 0;
  604. }
  605. #endif
  606. static const struct pci_device_id via[] = {
  607. { PCI_VDEVICE(VIA, 0x0415), },
  608. { PCI_VDEVICE(VIA, 0x0571), },
  609. { PCI_VDEVICE(VIA, 0x0581), },
  610. { PCI_VDEVICE(VIA, 0x1571), },
  611. { PCI_VDEVICE(VIA, 0x3164), },
  612. { PCI_VDEVICE(VIA, 0x5324), },
  613. { PCI_VDEVICE(VIA, 0xC409), VIA_IDFLAG_SINGLE },
  614. { PCI_VDEVICE(VIA, 0x9001), VIA_IDFLAG_SINGLE },
  615. { },
  616. };
  617. static struct pci_driver via_pci_driver = {
  618. .name = DRV_NAME,
  619. .id_table = via,
  620. .probe = via_init_one,
  621. .remove = ata_pci_remove_one,
  622. #ifdef CONFIG_PM_SLEEP
  623. .suspend = ata_pci_device_suspend,
  624. .resume = via_reinit_one,
  625. #endif
  626. };
  627. module_pci_driver(via_pci_driver);
  628. MODULE_AUTHOR("Alan Cox");
  629. MODULE_DESCRIPTION("low-level driver for VIA PATA");
  630. MODULE_LICENSE("GPL");
  631. MODULE_DEVICE_TABLE(pci, via);
  632. MODULE_VERSION(DRV_VERSION);