pata_sl82c105.c 9.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * pata_sl82c105.c - SL82C105 PATA for new ATA layer
  4. * (C) 2005 Red Hat Inc
  5. * (C) 2011 Bartlomiej Zolnierkiewicz
  6. *
  7. * Based in part on linux/drivers/ide/pci/sl82c105.c
  8. * SL82C105/Winbond 553 IDE driver
  9. *
  10. * and in part on the documentation and errata sheet
  11. *
  12. *
  13. * Note: The controller like many controllers has shared timings for
  14. * PIO and DMA. We thus flip to the DMA timings in dma_start and flip back
  15. * in the dma_stop function. Thus we actually don't need a set_dmamode
  16. * method as the PIO method is always called and will set the right PIO
  17. * timing parameters.
  18. */
  19. #include <linux/kernel.h>
  20. #include <linux/module.h>
  21. #include <linux/pci.h>
  22. #include <linux/blkdev.h>
  23. #include <linux/delay.h>
  24. #include <scsi/scsi_host.h>
  25. #include <linux/libata.h>
  26. #define DRV_NAME "pata_sl82c105"
  27. #define DRV_VERSION "0.3.3"
  28. enum {
  29. /*
  30. * SL82C105 PCI config register 0x40 bits.
  31. */
  32. CTRL_IDE_IRQB = (1 << 30),
  33. CTRL_IDE_IRQA = (1 << 28),
  34. CTRL_LEGIRQ = (1 << 11),
  35. CTRL_P1F16 = (1 << 5),
  36. CTRL_P1EN = (1 << 4),
  37. CTRL_P0F16 = (1 << 1),
  38. CTRL_P0EN = (1 << 0)
  39. };
  40. /**
  41. * sl82c105_pre_reset - probe begin
  42. * @link: ATA link
  43. * @deadline: deadline jiffies for the operation
  44. *
  45. * Set up cable type and use generic probe init
  46. */
  47. static int sl82c105_pre_reset(struct ata_link *link, unsigned long deadline)
  48. {
  49. static const struct pci_bits sl82c105_enable_bits[] = {
  50. { 0x40, 1, 0x01, 0x01 },
  51. { 0x40, 1, 0x10, 0x10 }
  52. };
  53. struct ata_port *ap = link->ap;
  54. struct pci_dev *pdev = to_pci_dev(ap->host->dev);
  55. if (ap->port_no && !pci_test_config_bits(pdev, &sl82c105_enable_bits[ap->port_no]))
  56. return -ENOENT;
  57. return ata_sff_prereset(link, deadline);
  58. }
  59. /**
  60. * sl82c105_configure_piomode - set chip PIO timing
  61. * @ap: ATA interface
  62. * @adev: ATA device
  63. * @pio: PIO mode
  64. *
  65. * Called to do the PIO mode setup. Our timing registers are shared
  66. * so a configure_dmamode call will undo any work we do here and vice
  67. * versa
  68. */
  69. static void sl82c105_configure_piomode(struct ata_port *ap, struct ata_device *adev, int pio)
  70. {
  71. struct pci_dev *pdev = to_pci_dev(ap->host->dev);
  72. static u16 pio_timing[5] = {
  73. 0x50D, 0x407, 0x304, 0x242, 0x240
  74. };
  75. u16 dummy;
  76. int timing = 0x44 + (8 * ap->port_no) + (4 * adev->devno);
  77. pci_write_config_word(pdev, timing, pio_timing[pio]);
  78. /* Can we lose this oddity of the old driver */
  79. pci_read_config_word(pdev, timing, &dummy);
  80. }
  81. /**
  82. * sl82c105_set_piomode - set initial PIO mode data
  83. * @ap: ATA interface
  84. * @adev: ATA device
  85. *
  86. * Called to do the PIO mode setup. Our timing registers are shared
  87. * but we want to set the PIO timing by default.
  88. */
  89. static void sl82c105_set_piomode(struct ata_port *ap, struct ata_device *adev)
  90. {
  91. sl82c105_configure_piomode(ap, adev, adev->pio_mode - XFER_PIO_0);
  92. }
  93. /**
  94. * sl82c105_configure_dmamode - set DMA mode in chip
  95. * @ap: ATA interface
  96. * @adev: ATA device
  97. *
  98. * Load DMA cycle times into the chip ready for a DMA transfer
  99. * to occur.
  100. */
  101. static void sl82c105_configure_dmamode(struct ata_port *ap, struct ata_device *adev)
  102. {
  103. struct pci_dev *pdev = to_pci_dev(ap->host->dev);
  104. static u16 dma_timing[3] = {
  105. 0x707, 0x201, 0x200
  106. };
  107. u16 dummy;
  108. int timing = 0x44 + (8 * ap->port_no) + (4 * adev->devno);
  109. int dma = adev->dma_mode - XFER_MW_DMA_0;
  110. pci_write_config_word(pdev, timing, dma_timing[dma]);
  111. /* Can we lose this oddity of the old driver */
  112. pci_read_config_word(pdev, timing, &dummy);
  113. }
  114. /**
  115. * sl82c105_reset_engine - Reset the DMA engine
  116. * @ap: ATA interface
  117. *
  118. * The sl82c105 has some serious problems with the DMA engine
  119. * when transfers don't run as expected or ATAPI is used. The
  120. * recommended fix is to reset the engine each use using a chip
  121. * test register.
  122. */
  123. static void sl82c105_reset_engine(struct ata_port *ap)
  124. {
  125. struct pci_dev *pdev = to_pci_dev(ap->host->dev);
  126. u16 val;
  127. pci_read_config_word(pdev, 0x7E, &val);
  128. pci_write_config_word(pdev, 0x7E, val | 4);
  129. pci_write_config_word(pdev, 0x7E, val & ~4);
  130. }
  131. /**
  132. * sl82c105_bmdma_start - DMA engine begin
  133. * @qc: ATA command
  134. *
  135. * Reset the DMA engine each use as recommended by the errata
  136. * document.
  137. *
  138. * FIXME: if we switch clock at BMDMA start/end we might get better
  139. * PIO performance on DMA capable devices.
  140. */
  141. static void sl82c105_bmdma_start(struct ata_queued_cmd *qc)
  142. {
  143. struct ata_port *ap = qc->ap;
  144. udelay(100);
  145. sl82c105_reset_engine(ap);
  146. udelay(100);
  147. /* Set the clocks for DMA */
  148. sl82c105_configure_dmamode(ap, qc->dev);
  149. /* Activate DMA */
  150. ata_bmdma_start(qc);
  151. }
  152. /**
  153. * sl82c105_bmdma_end - DMA engine stop
  154. * @qc: ATA command
  155. *
  156. * Reset the DMA engine each use as recommended by the errata
  157. * document.
  158. *
  159. * This function is also called to turn off DMA when a timeout occurs
  160. * during DMA operation. In both cases we need to reset the engine,
  161. * so no actual eng_timeout handler is required.
  162. *
  163. * We assume bmdma_stop is always called if bmdma_start as called. If
  164. * not then we may need to wrap qc_issue.
  165. */
  166. static void sl82c105_bmdma_stop(struct ata_queued_cmd *qc)
  167. {
  168. struct ata_port *ap = qc->ap;
  169. ata_bmdma_stop(qc);
  170. sl82c105_reset_engine(ap);
  171. udelay(100);
  172. /* This will redo the initial setup of the DMA device to matching
  173. PIO timings */
  174. sl82c105_set_piomode(ap, qc->dev);
  175. }
  176. /**
  177. * sl82c105_qc_defer - implement serialization
  178. * @qc: command
  179. *
  180. * We must issue one command per host not per channel because
  181. * of the reset bug.
  182. *
  183. * Q: is the scsi host lock sufficient ?
  184. */
  185. static int sl82c105_qc_defer(struct ata_queued_cmd *qc)
  186. {
  187. struct ata_host *host = qc->ap->host;
  188. struct ata_port *alt = host->ports[1 ^ qc->ap->port_no];
  189. int rc;
  190. /* First apply the usual rules */
  191. rc = ata_std_qc_defer(qc);
  192. if (rc != 0)
  193. return rc;
  194. /* Now apply serialization rules. Only allow a command if the
  195. other channel state machine is idle */
  196. if (alt && alt->qc_active)
  197. return ATA_DEFER_PORT;
  198. return 0;
  199. }
  200. static bool sl82c105_sff_irq_check(struct ata_port *ap)
  201. {
  202. struct pci_dev *pdev = to_pci_dev(ap->host->dev);
  203. u32 val, mask = ap->port_no ? CTRL_IDE_IRQB : CTRL_IDE_IRQA;
  204. pci_read_config_dword(pdev, 0x40, &val);
  205. return val & mask;
  206. }
  207. static struct scsi_host_template sl82c105_sht = {
  208. ATA_BMDMA_SHT(DRV_NAME),
  209. };
  210. static struct ata_port_operations sl82c105_port_ops = {
  211. .inherits = &ata_bmdma_port_ops,
  212. .qc_defer = sl82c105_qc_defer,
  213. .bmdma_start = sl82c105_bmdma_start,
  214. .bmdma_stop = sl82c105_bmdma_stop,
  215. .cable_detect = ata_cable_40wire,
  216. .set_piomode = sl82c105_set_piomode,
  217. .prereset = sl82c105_pre_reset,
  218. .sff_irq_check = sl82c105_sff_irq_check,
  219. };
  220. /**
  221. * sl82c105_bridge_revision - find bridge version
  222. * @pdev: PCI device for the ATA function
  223. *
  224. * Locates the PCI bridge associated with the ATA function and
  225. * providing it is a Winbond 553 reports the revision. If it cannot
  226. * find a revision or the right device it returns -1
  227. */
  228. static int sl82c105_bridge_revision(struct pci_dev *pdev)
  229. {
  230. struct pci_dev *bridge;
  231. /*
  232. * The bridge should be part of the same device, but function 0.
  233. */
  234. bridge = pci_get_slot(pdev->bus,
  235. PCI_DEVFN(PCI_SLOT(pdev->devfn), 0));
  236. if (!bridge)
  237. return -1;
  238. /*
  239. * Make sure it is a Winbond 553 and is an ISA bridge.
  240. */
  241. if (bridge->vendor != PCI_VENDOR_ID_WINBOND ||
  242. bridge->device != PCI_DEVICE_ID_WINBOND_83C553 ||
  243. bridge->class >> 8 != PCI_CLASS_BRIDGE_ISA) {
  244. pci_dev_put(bridge);
  245. return -1;
  246. }
  247. /*
  248. * We need to find function 0's revision, not function 1
  249. */
  250. pci_dev_put(bridge);
  251. return bridge->revision;
  252. }
  253. static void sl82c105_fixup(struct pci_dev *pdev)
  254. {
  255. u32 val;
  256. pci_read_config_dword(pdev, 0x40, &val);
  257. val |= CTRL_P0EN | CTRL_P0F16 | CTRL_P1F16;
  258. pci_write_config_dword(pdev, 0x40, val);
  259. }
  260. static int sl82c105_init_one(struct pci_dev *dev, const struct pci_device_id *id)
  261. {
  262. static const struct ata_port_info info_dma = {
  263. .flags = ATA_FLAG_SLAVE_POSS,
  264. .pio_mask = ATA_PIO4,
  265. .mwdma_mask = ATA_MWDMA2,
  266. .port_ops = &sl82c105_port_ops
  267. };
  268. static const struct ata_port_info info_early = {
  269. .flags = ATA_FLAG_SLAVE_POSS,
  270. .pio_mask = ATA_PIO4,
  271. .port_ops = &sl82c105_port_ops
  272. };
  273. /* for now use only the first port */
  274. const struct ata_port_info *ppi[] = { &info_early,
  275. NULL };
  276. int rev;
  277. int rc;
  278. rc = pcim_enable_device(dev);
  279. if (rc)
  280. return rc;
  281. rev = sl82c105_bridge_revision(dev);
  282. if (rev == -1)
  283. dev_warn(&dev->dev,
  284. "pata_sl82c105: Unable to find bridge, disabling DMA\n");
  285. else if (rev <= 5)
  286. dev_warn(&dev->dev,
  287. "pata_sl82c105: Early bridge revision, no DMA available\n");
  288. else
  289. ppi[0] = &info_dma;
  290. sl82c105_fixup(dev);
  291. return ata_pci_bmdma_init_one(dev, ppi, &sl82c105_sht, NULL, 0);
  292. }
  293. #ifdef CONFIG_PM_SLEEP
  294. static int sl82c105_reinit_one(struct pci_dev *pdev)
  295. {
  296. struct ata_host *host = pci_get_drvdata(pdev);
  297. int rc;
  298. rc = ata_pci_device_do_resume(pdev);
  299. if (rc)
  300. return rc;
  301. sl82c105_fixup(pdev);
  302. ata_host_resume(host);
  303. return 0;
  304. }
  305. #endif
  306. static const struct pci_device_id sl82c105[] = {
  307. { PCI_VDEVICE(WINBOND, PCI_DEVICE_ID_WINBOND_82C105), },
  308. { },
  309. };
  310. static struct pci_driver sl82c105_pci_driver = {
  311. .name = DRV_NAME,
  312. .id_table = sl82c105,
  313. .probe = sl82c105_init_one,
  314. .remove = ata_pci_remove_one,
  315. #ifdef CONFIG_PM_SLEEP
  316. .suspend = ata_pci_device_suspend,
  317. .resume = sl82c105_reinit_one,
  318. #endif
  319. };
  320. module_pci_driver(sl82c105_pci_driver);
  321. MODULE_AUTHOR("Alan Cox");
  322. MODULE_DESCRIPTION("low-level driver for Sl82c105");
  323. MODULE_LICENSE("GPL");
  324. MODULE_DEVICE_TABLE(pci, sl82c105);
  325. MODULE_VERSION(DRV_VERSION);