pata_sil680.c 11 KB

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  1. /*
  2. * pata_sil680.c - SIL680 PATA for new ATA layer
  3. * (C) 2005 Red Hat Inc
  4. *
  5. * based upon
  6. *
  7. * linux/drivers/ide/pci/siimage.c Version 1.07 Nov 30, 2003
  8. *
  9. * Copyright (C) 2001-2002 Andre Hedrick <andre@linux-ide.org>
  10. * Copyright (C) 2003 Red Hat <alan@redhat.com>
  11. *
  12. * May be copied or modified under the terms of the GNU General Public License
  13. *
  14. * Documentation publicly available.
  15. *
  16. * If you have strange problems with nVidia chipset systems please
  17. * see the SI support documentation and update your system BIOS
  18. * if necessary
  19. *
  20. * TODO
  21. * If we know all our devices are LBA28 (or LBA28 sized) we could use
  22. * the command fifo mode.
  23. */
  24. #include <linux/kernel.h>
  25. #include <linux/module.h>
  26. #include <linux/pci.h>
  27. #include <linux/blkdev.h>
  28. #include <linux/delay.h>
  29. #include <scsi/scsi_host.h>
  30. #include <linux/libata.h>
  31. #define DRV_NAME "pata_sil680"
  32. #define DRV_VERSION "0.4.9"
  33. #define SIL680_MMIO_BAR 5
  34. /**
  35. * sil680_selreg - return register base
  36. * @ap: ATA interface
  37. * @r: config offset
  38. *
  39. * Turn a config register offset into the right address in PCI space
  40. * to access the control register in question.
  41. *
  42. * Thankfully this is a configuration operation so isn't performance
  43. * criticial.
  44. */
  45. static unsigned long sil680_selreg(struct ata_port *ap, int r)
  46. {
  47. unsigned long base = 0xA0 + r;
  48. base += (ap->port_no << 4);
  49. return base;
  50. }
  51. /**
  52. * sil680_seldev - return register base
  53. * @ap: ATA interface
  54. * @r: config offset
  55. *
  56. * Turn a config register offset into the right address in PCI space
  57. * to access the control register in question including accounting for
  58. * the unit shift.
  59. */
  60. static unsigned long sil680_seldev(struct ata_port *ap, struct ata_device *adev, int r)
  61. {
  62. unsigned long base = 0xA0 + r;
  63. base += (ap->port_no << 4);
  64. base |= adev->devno ? 2 : 0;
  65. return base;
  66. }
  67. /**
  68. * sil680_cable_detect - cable detection
  69. * @ap: ATA port
  70. *
  71. * Perform cable detection. The SIL680 stores this in PCI config
  72. * space for us.
  73. */
  74. static int sil680_cable_detect(struct ata_port *ap)
  75. {
  76. struct pci_dev *pdev = to_pci_dev(ap->host->dev);
  77. unsigned long addr = sil680_selreg(ap, 0);
  78. u8 ata66;
  79. pci_read_config_byte(pdev, addr, &ata66);
  80. if (ata66 & 1)
  81. return ATA_CBL_PATA80;
  82. else
  83. return ATA_CBL_PATA40;
  84. }
  85. /**
  86. * sil680_set_piomode - set PIO mode data
  87. * @ap: ATA interface
  88. * @adev: ATA device
  89. *
  90. * Program the SIL680 registers for PIO mode. Note that the task speed
  91. * registers are shared between the devices so we must pick the lowest
  92. * mode for command work.
  93. */
  94. static void sil680_set_piomode(struct ata_port *ap, struct ata_device *adev)
  95. {
  96. static const u16 speed_p[5] = {
  97. 0x328A, 0x2283, 0x1104, 0x10C3, 0x10C1
  98. };
  99. static const u16 speed_t[5] = {
  100. 0x328A, 0x2283, 0x1281, 0x10C3, 0x10C1
  101. };
  102. unsigned long tfaddr = sil680_selreg(ap, 0x02);
  103. unsigned long addr = sil680_seldev(ap, adev, 0x04);
  104. unsigned long addr_mask = 0x80 + 4 * ap->port_no;
  105. struct pci_dev *pdev = to_pci_dev(ap->host->dev);
  106. int pio = adev->pio_mode - XFER_PIO_0;
  107. int lowest_pio = pio;
  108. int port_shift = 4 * adev->devno;
  109. u16 reg;
  110. u8 mode;
  111. struct ata_device *pair = ata_dev_pair(adev);
  112. if (pair != NULL && adev->pio_mode > pair->pio_mode)
  113. lowest_pio = pair->pio_mode - XFER_PIO_0;
  114. pci_write_config_word(pdev, addr, speed_p[pio]);
  115. pci_write_config_word(pdev, tfaddr, speed_t[lowest_pio]);
  116. pci_read_config_word(pdev, tfaddr-2, &reg);
  117. pci_read_config_byte(pdev, addr_mask, &mode);
  118. reg &= ~0x0200; /* Clear IORDY */
  119. mode &= ~(3 << port_shift); /* Clear IORDY and DMA bits */
  120. if (ata_pio_need_iordy(adev)) {
  121. reg |= 0x0200; /* Enable IORDY */
  122. mode |= 1 << port_shift;
  123. }
  124. pci_write_config_word(pdev, tfaddr-2, reg);
  125. pci_write_config_byte(pdev, addr_mask, mode);
  126. }
  127. /**
  128. * sil680_set_dmamode - set DMA mode data
  129. * @ap: ATA interface
  130. * @adev: ATA device
  131. *
  132. * Program the MWDMA/UDMA modes for the sil680 chipset.
  133. *
  134. * The MWDMA mode values are pulled from a lookup table
  135. * while the chipset uses mode number for UDMA.
  136. */
  137. static void sil680_set_dmamode(struct ata_port *ap, struct ata_device *adev)
  138. {
  139. static const u8 ultra_table[2][7] = {
  140. { 0x0C, 0x07, 0x05, 0x04, 0x02, 0x01, 0xFF }, /* 100MHz */
  141. { 0x0F, 0x0B, 0x07, 0x05, 0x03, 0x02, 0x01 }, /* 133Mhz */
  142. };
  143. static const u16 dma_table[3] = { 0x2208, 0x10C2, 0x10C1 };
  144. struct pci_dev *pdev = to_pci_dev(ap->host->dev);
  145. unsigned long ma = sil680_seldev(ap, adev, 0x08);
  146. unsigned long ua = sil680_seldev(ap, adev, 0x0C);
  147. unsigned long addr_mask = 0x80 + 4 * ap->port_no;
  148. int port_shift = adev->devno * 4;
  149. u8 scsc, mode;
  150. u16 multi, ultra;
  151. pci_read_config_byte(pdev, 0x8A, &scsc);
  152. pci_read_config_byte(pdev, addr_mask, &mode);
  153. pci_read_config_word(pdev, ma, &multi);
  154. pci_read_config_word(pdev, ua, &ultra);
  155. /* Mask timing bits */
  156. ultra &= ~0x3F;
  157. mode &= ~(0x03 << port_shift);
  158. /* Extract scsc */
  159. scsc = (scsc & 0x30) ? 1 : 0;
  160. if (adev->dma_mode >= XFER_UDMA_0) {
  161. multi = 0x10C1;
  162. ultra |= ultra_table[scsc][adev->dma_mode - XFER_UDMA_0];
  163. mode |= (0x03 << port_shift);
  164. } else {
  165. multi = dma_table[adev->dma_mode - XFER_MW_DMA_0];
  166. mode |= (0x02 << port_shift);
  167. }
  168. pci_write_config_byte(pdev, addr_mask, mode);
  169. pci_write_config_word(pdev, ma, multi);
  170. pci_write_config_word(pdev, ua, ultra);
  171. }
  172. /**
  173. * sil680_sff_exec_command - issue ATA command to host controller
  174. * @ap: port to which command is being issued
  175. * @tf: ATA taskfile register set
  176. *
  177. * Issues ATA command, with proper synchronization with interrupt
  178. * handler / other threads. Use our MMIO space for PCI posting to avoid
  179. * a hideously slow cycle all the way to the device.
  180. *
  181. * LOCKING:
  182. * spin_lock_irqsave(host lock)
  183. */
  184. static void sil680_sff_exec_command(struct ata_port *ap,
  185. const struct ata_taskfile *tf)
  186. {
  187. DPRINTK("ata%u: cmd 0x%X\n", ap->print_id, tf->command);
  188. iowrite8(tf->command, ap->ioaddr.command_addr);
  189. ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
  190. }
  191. static bool sil680_sff_irq_check(struct ata_port *ap)
  192. {
  193. struct pci_dev *pdev = to_pci_dev(ap->host->dev);
  194. unsigned long addr = sil680_selreg(ap, 1);
  195. u8 val;
  196. pci_read_config_byte(pdev, addr, &val);
  197. return val & 0x08;
  198. }
  199. static struct scsi_host_template sil680_sht = {
  200. ATA_BMDMA_SHT(DRV_NAME),
  201. };
  202. static struct ata_port_operations sil680_port_ops = {
  203. .inherits = &ata_bmdma32_port_ops,
  204. .sff_exec_command = sil680_sff_exec_command,
  205. .sff_irq_check = sil680_sff_irq_check,
  206. .cable_detect = sil680_cable_detect,
  207. .set_piomode = sil680_set_piomode,
  208. .set_dmamode = sil680_set_dmamode,
  209. };
  210. /**
  211. * sil680_init_chip - chip setup
  212. * @pdev: PCI device
  213. *
  214. * Perform all the chip setup which must be done both when the device
  215. * is powered up on boot and when we resume in case we resumed from RAM.
  216. * Returns the final clock settings.
  217. */
  218. static u8 sil680_init_chip(struct pci_dev *pdev, int *try_mmio)
  219. {
  220. u8 tmpbyte = 0;
  221. /* FIXME: double check */
  222. pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE,
  223. pdev->revision ? 1 : 255);
  224. pci_write_config_byte(pdev, 0x80, 0x00);
  225. pci_write_config_byte(pdev, 0x84, 0x00);
  226. pci_read_config_byte(pdev, 0x8A, &tmpbyte);
  227. dev_dbg(&pdev->dev, "sil680: BA5_EN = %d clock = %02X\n",
  228. tmpbyte & 1, tmpbyte & 0x30);
  229. *try_mmio = 0;
  230. #ifdef CONFIG_PPC
  231. if (machine_is(cell))
  232. *try_mmio = (tmpbyte & 1) || pci_resource_start(pdev, 5);
  233. #endif
  234. switch (tmpbyte & 0x30) {
  235. case 0x00:
  236. /* 133 clock attempt to force it on */
  237. pci_write_config_byte(pdev, 0x8A, tmpbyte|0x10);
  238. break;
  239. case 0x30:
  240. /* if clocking is disabled */
  241. /* 133 clock attempt to force it on */
  242. pci_write_config_byte(pdev, 0x8A, tmpbyte & ~0x20);
  243. break;
  244. case 0x10:
  245. /* 133 already */
  246. break;
  247. case 0x20:
  248. /* BIOS set PCI x2 clocking */
  249. break;
  250. }
  251. pci_read_config_byte(pdev, 0x8A, &tmpbyte);
  252. dev_dbg(&pdev->dev, "sil680: BA5_EN = %d clock = %02X\n",
  253. tmpbyte & 1, tmpbyte & 0x30);
  254. pci_write_config_byte(pdev, 0xA1, 0x72);
  255. pci_write_config_word(pdev, 0xA2, 0x328A);
  256. pci_write_config_dword(pdev, 0xA4, 0x62DD62DD);
  257. pci_write_config_dword(pdev, 0xA8, 0x43924392);
  258. pci_write_config_dword(pdev, 0xAC, 0x40094009);
  259. pci_write_config_byte(pdev, 0xB1, 0x72);
  260. pci_write_config_word(pdev, 0xB2, 0x328A);
  261. pci_write_config_dword(pdev, 0xB4, 0x62DD62DD);
  262. pci_write_config_dword(pdev, 0xB8, 0x43924392);
  263. pci_write_config_dword(pdev, 0xBC, 0x40094009);
  264. switch (tmpbyte & 0x30) {
  265. case 0x00:
  266. printk(KERN_INFO "sil680: 100MHz clock.\n");
  267. break;
  268. case 0x10:
  269. printk(KERN_INFO "sil680: 133MHz clock.\n");
  270. break;
  271. case 0x20:
  272. printk(KERN_INFO "sil680: Using PCI clock.\n");
  273. break;
  274. /* This last case is _NOT_ ok */
  275. case 0x30:
  276. printk(KERN_ERR "sil680: Clock disabled ?\n");
  277. }
  278. return tmpbyte & 0x30;
  279. }
  280. static int sil680_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
  281. {
  282. static const struct ata_port_info info = {
  283. .flags = ATA_FLAG_SLAVE_POSS,
  284. .pio_mask = ATA_PIO4,
  285. .mwdma_mask = ATA_MWDMA2,
  286. .udma_mask = ATA_UDMA6,
  287. .port_ops = &sil680_port_ops
  288. };
  289. static const struct ata_port_info info_slow = {
  290. .flags = ATA_FLAG_SLAVE_POSS,
  291. .pio_mask = ATA_PIO4,
  292. .mwdma_mask = ATA_MWDMA2,
  293. .udma_mask = ATA_UDMA5,
  294. .port_ops = &sil680_port_ops
  295. };
  296. const struct ata_port_info *ppi[] = { &info, NULL };
  297. struct ata_host *host;
  298. void __iomem *mmio_base;
  299. int rc, try_mmio;
  300. ata_print_version_once(&pdev->dev, DRV_VERSION);
  301. rc = pcim_enable_device(pdev);
  302. if (rc)
  303. return rc;
  304. switch (sil680_init_chip(pdev, &try_mmio)) {
  305. case 0:
  306. ppi[0] = &info_slow;
  307. break;
  308. case 0x30:
  309. return -ENODEV;
  310. }
  311. if (!try_mmio)
  312. goto use_ioports;
  313. /* Try to acquire MMIO resources and fallback to PIO if
  314. * that fails
  315. */
  316. rc = pcim_iomap_regions(pdev, 1 << SIL680_MMIO_BAR, DRV_NAME);
  317. if (rc)
  318. goto use_ioports;
  319. /* Allocate host and set it up */
  320. host = ata_host_alloc_pinfo(&pdev->dev, ppi, 2);
  321. if (!host)
  322. return -ENOMEM;
  323. host->iomap = pcim_iomap_table(pdev);
  324. /* Setup DMA masks */
  325. rc = dma_set_mask_and_coherent(&pdev->dev, ATA_DMA_MASK);
  326. if (rc)
  327. return rc;
  328. pci_set_master(pdev);
  329. /* Get MMIO base and initialize port addresses */
  330. mmio_base = host->iomap[SIL680_MMIO_BAR];
  331. host->ports[0]->ioaddr.bmdma_addr = mmio_base + 0x00;
  332. host->ports[0]->ioaddr.cmd_addr = mmio_base + 0x80;
  333. host->ports[0]->ioaddr.ctl_addr = mmio_base + 0x8a;
  334. host->ports[0]->ioaddr.altstatus_addr = mmio_base + 0x8a;
  335. ata_sff_std_ports(&host->ports[0]->ioaddr);
  336. host->ports[1]->ioaddr.bmdma_addr = mmio_base + 0x08;
  337. host->ports[1]->ioaddr.cmd_addr = mmio_base + 0xc0;
  338. host->ports[1]->ioaddr.ctl_addr = mmio_base + 0xca;
  339. host->ports[1]->ioaddr.altstatus_addr = mmio_base + 0xca;
  340. ata_sff_std_ports(&host->ports[1]->ioaddr);
  341. /* Register & activate */
  342. return ata_host_activate(host, pdev->irq, ata_bmdma_interrupt,
  343. IRQF_SHARED, &sil680_sht);
  344. use_ioports:
  345. return ata_pci_bmdma_init_one(pdev, ppi, &sil680_sht, NULL, 0);
  346. }
  347. #ifdef CONFIG_PM_SLEEP
  348. static int sil680_reinit_one(struct pci_dev *pdev)
  349. {
  350. struct ata_host *host = pci_get_drvdata(pdev);
  351. int try_mmio, rc;
  352. rc = ata_pci_device_do_resume(pdev);
  353. if (rc)
  354. return rc;
  355. sil680_init_chip(pdev, &try_mmio);
  356. ata_host_resume(host);
  357. return 0;
  358. }
  359. #endif
  360. static const struct pci_device_id sil680[] = {
  361. { PCI_VDEVICE(CMD, PCI_DEVICE_ID_SII_680), },
  362. { },
  363. };
  364. static struct pci_driver sil680_pci_driver = {
  365. .name = DRV_NAME,
  366. .id_table = sil680,
  367. .probe = sil680_init_one,
  368. .remove = ata_pci_remove_one,
  369. #ifdef CONFIG_PM_SLEEP
  370. .suspend = ata_pci_device_suspend,
  371. .resume = sil680_reinit_one,
  372. #endif
  373. };
  374. module_pci_driver(sil680_pci_driver);
  375. MODULE_AUTHOR("Alan Cox");
  376. MODULE_DESCRIPTION("low-level driver for SI680 PATA");
  377. MODULE_LICENSE("GPL");
  378. MODULE_DEVICE_TABLE(pci, sil680);
  379. MODULE_VERSION(DRV_VERSION);