pata_samsung_cf.c 17 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2010 Samsung Electronics Co., Ltd.
  4. * http://www.samsung.com
  5. *
  6. * PATA driver for Samsung SoCs.
  7. * Supports CF Interface in True IDE mode. Currently only PIO mode has been
  8. * implemented; UDMA support has to be added.
  9. *
  10. * Based on:
  11. * PATA driver for AT91SAM9260 Static Memory Controller
  12. * PATA driver for Toshiba SCC controller
  13. */
  14. #include <linux/kernel.h>
  15. #include <linux/module.h>
  16. #include <linux/mod_devicetable.h>
  17. #include <linux/init.h>
  18. #include <linux/clk.h>
  19. #include <linux/libata.h>
  20. #include <linux/platform_device.h>
  21. #include <linux/slab.h>
  22. #include <linux/platform_data/ata-samsung_cf.h>
  23. #define DRV_NAME "pata_samsung_cf"
  24. #define DRV_VERSION "0.1"
  25. #define S3C_CFATA_REG(x) (x)
  26. #define S3C_CFATA_MUX S3C_CFATA_REG(0x0)
  27. #define S3C_ATA_CTRL S3C_CFATA_REG(0x0)
  28. #define S3C_ATA_CMD S3C_CFATA_REG(0x8)
  29. #define S3C_ATA_IRQ S3C_CFATA_REG(0x10)
  30. #define S3C_ATA_IRQ_MSK S3C_CFATA_REG(0x14)
  31. #define S3C_ATA_CFG S3C_CFATA_REG(0x18)
  32. #define S3C_ATA_PIO_TIME S3C_CFATA_REG(0x2c)
  33. #define S3C_ATA_PIO_DTR S3C_CFATA_REG(0x54)
  34. #define S3C_ATA_PIO_FED S3C_CFATA_REG(0x58)
  35. #define S3C_ATA_PIO_SCR S3C_CFATA_REG(0x5c)
  36. #define S3C_ATA_PIO_LLR S3C_CFATA_REG(0x60)
  37. #define S3C_ATA_PIO_LMR S3C_CFATA_REG(0x64)
  38. #define S3C_ATA_PIO_LHR S3C_CFATA_REG(0x68)
  39. #define S3C_ATA_PIO_DVR S3C_CFATA_REG(0x6c)
  40. #define S3C_ATA_PIO_CSD S3C_CFATA_REG(0x70)
  41. #define S3C_ATA_PIO_DAD S3C_CFATA_REG(0x74)
  42. #define S3C_ATA_PIO_RDATA S3C_CFATA_REG(0x7c)
  43. #define S3C_CFATA_MUX_TRUEIDE 0x01
  44. #define S3C_ATA_CFG_SWAP 0x40
  45. #define S3C_ATA_CFG_IORDYEN 0x02
  46. enum s3c_cpu_type {
  47. TYPE_S3C64XX,
  48. TYPE_S5PV210,
  49. };
  50. /*
  51. * struct s3c_ide_info - S3C PATA instance.
  52. * @clk: The clock resource for this controller.
  53. * @ide_addr: The area mapped for the hardware registers.
  54. * @sfr_addr: The area mapped for the special function registers.
  55. * @irq: The IRQ number we are using.
  56. * @cpu_type: The exact type of this controller.
  57. * @fifo_status_reg: The ATA_FIFO_STATUS register offset.
  58. */
  59. struct s3c_ide_info {
  60. struct clk *clk;
  61. void __iomem *ide_addr;
  62. void __iomem *sfr_addr;
  63. int irq;
  64. enum s3c_cpu_type cpu_type;
  65. unsigned int fifo_status_reg;
  66. };
  67. static void pata_s3c_set_endian(void __iomem *s3c_ide_regbase, u8 mode)
  68. {
  69. u32 reg = readl(s3c_ide_regbase + S3C_ATA_CFG);
  70. reg = mode ? (reg & ~S3C_ATA_CFG_SWAP) : (reg | S3C_ATA_CFG_SWAP);
  71. writel(reg, s3c_ide_regbase + S3C_ATA_CFG);
  72. }
  73. static void pata_s3c_cfg_mode(void __iomem *s3c_ide_sfrbase)
  74. {
  75. /* Select true-ide as the internal operating mode */
  76. writel(readl(s3c_ide_sfrbase + S3C_CFATA_MUX) | S3C_CFATA_MUX_TRUEIDE,
  77. s3c_ide_sfrbase + S3C_CFATA_MUX);
  78. }
  79. static unsigned long
  80. pata_s3c_setup_timing(struct s3c_ide_info *info, const struct ata_timing *ata)
  81. {
  82. int t1 = ata->setup;
  83. int t2 = ata->act8b;
  84. int t2i = ata->rec8b;
  85. ulong piotime;
  86. piotime = ((t2i & 0xff) << 12) | ((t2 & 0xff) << 4) | (t1 & 0xf);
  87. return piotime;
  88. }
  89. static void pata_s3c_set_piomode(struct ata_port *ap, struct ata_device *adev)
  90. {
  91. struct s3c_ide_info *info = ap->host->private_data;
  92. struct ata_timing timing;
  93. int cycle_time;
  94. ulong ata_cfg = readl(info->ide_addr + S3C_ATA_CFG);
  95. ulong piotime;
  96. /* Enables IORDY if mode requires it */
  97. if (ata_pio_need_iordy(adev))
  98. ata_cfg |= S3C_ATA_CFG_IORDYEN;
  99. else
  100. ata_cfg &= ~S3C_ATA_CFG_IORDYEN;
  101. cycle_time = (int)(1000000000UL / clk_get_rate(info->clk));
  102. ata_timing_compute(adev, adev->pio_mode, &timing,
  103. cycle_time * 1000, 0);
  104. piotime = pata_s3c_setup_timing(info, &timing);
  105. writel(ata_cfg, info->ide_addr + S3C_ATA_CFG);
  106. writel(piotime, info->ide_addr + S3C_ATA_PIO_TIME);
  107. }
  108. /*
  109. * Waits until the IDE controller is able to perform next read/write
  110. * operation to the disk. Needed for 64XX series boards only.
  111. */
  112. static int wait_for_host_ready(struct s3c_ide_info *info)
  113. {
  114. ulong timeout;
  115. void __iomem *fifo_reg = info->ide_addr + info->fifo_status_reg;
  116. /* wait for maximum of 20 msec */
  117. timeout = jiffies + msecs_to_jiffies(20);
  118. while (time_before(jiffies, timeout)) {
  119. if ((readl(fifo_reg) >> 28) == 0)
  120. return 0;
  121. }
  122. return -EBUSY;
  123. }
  124. /*
  125. * Writes to one of the task file registers.
  126. */
  127. static void ata_outb(struct ata_host *host, u8 addr, void __iomem *reg)
  128. {
  129. struct s3c_ide_info *info = host->private_data;
  130. wait_for_host_ready(info);
  131. writeb(addr, reg);
  132. }
  133. /*
  134. * Reads from one of the task file registers.
  135. */
  136. static u8 ata_inb(struct ata_host *host, void __iomem *reg)
  137. {
  138. struct s3c_ide_info *info = host->private_data;
  139. u8 temp;
  140. wait_for_host_ready(info);
  141. (void) readb(reg);
  142. wait_for_host_ready(info);
  143. temp = readb(info->ide_addr + S3C_ATA_PIO_RDATA);
  144. return temp;
  145. }
  146. /*
  147. * pata_s3c_tf_load - send taskfile registers to host controller
  148. */
  149. static void pata_s3c_tf_load(struct ata_port *ap,
  150. const struct ata_taskfile *tf)
  151. {
  152. struct ata_ioports *ioaddr = &ap->ioaddr;
  153. unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
  154. if (tf->ctl != ap->last_ctl) {
  155. ata_outb(ap->host, tf->ctl, ioaddr->ctl_addr);
  156. ap->last_ctl = tf->ctl;
  157. ata_wait_idle(ap);
  158. }
  159. if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
  160. ata_outb(ap->host, tf->hob_feature, ioaddr->feature_addr);
  161. ata_outb(ap->host, tf->hob_nsect, ioaddr->nsect_addr);
  162. ata_outb(ap->host, tf->hob_lbal, ioaddr->lbal_addr);
  163. ata_outb(ap->host, tf->hob_lbam, ioaddr->lbam_addr);
  164. ata_outb(ap->host, tf->hob_lbah, ioaddr->lbah_addr);
  165. }
  166. if (is_addr) {
  167. ata_outb(ap->host, tf->feature, ioaddr->feature_addr);
  168. ata_outb(ap->host, tf->nsect, ioaddr->nsect_addr);
  169. ata_outb(ap->host, tf->lbal, ioaddr->lbal_addr);
  170. ata_outb(ap->host, tf->lbam, ioaddr->lbam_addr);
  171. ata_outb(ap->host, tf->lbah, ioaddr->lbah_addr);
  172. }
  173. if (tf->flags & ATA_TFLAG_DEVICE)
  174. ata_outb(ap->host, tf->device, ioaddr->device_addr);
  175. ata_wait_idle(ap);
  176. }
  177. /*
  178. * pata_s3c_tf_read - input device's ATA taskfile shadow registers
  179. */
  180. static void pata_s3c_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
  181. {
  182. struct ata_ioports *ioaddr = &ap->ioaddr;
  183. tf->feature = ata_inb(ap->host, ioaddr->error_addr);
  184. tf->nsect = ata_inb(ap->host, ioaddr->nsect_addr);
  185. tf->lbal = ata_inb(ap->host, ioaddr->lbal_addr);
  186. tf->lbam = ata_inb(ap->host, ioaddr->lbam_addr);
  187. tf->lbah = ata_inb(ap->host, ioaddr->lbah_addr);
  188. tf->device = ata_inb(ap->host, ioaddr->device_addr);
  189. if (tf->flags & ATA_TFLAG_LBA48) {
  190. ata_outb(ap->host, tf->ctl | ATA_HOB, ioaddr->ctl_addr);
  191. tf->hob_feature = ata_inb(ap->host, ioaddr->error_addr);
  192. tf->hob_nsect = ata_inb(ap->host, ioaddr->nsect_addr);
  193. tf->hob_lbal = ata_inb(ap->host, ioaddr->lbal_addr);
  194. tf->hob_lbam = ata_inb(ap->host, ioaddr->lbam_addr);
  195. tf->hob_lbah = ata_inb(ap->host, ioaddr->lbah_addr);
  196. ata_outb(ap->host, tf->ctl, ioaddr->ctl_addr);
  197. ap->last_ctl = tf->ctl;
  198. }
  199. }
  200. /*
  201. * pata_s3c_exec_command - issue ATA command to host controller
  202. */
  203. static void pata_s3c_exec_command(struct ata_port *ap,
  204. const struct ata_taskfile *tf)
  205. {
  206. ata_outb(ap->host, tf->command, ap->ioaddr.command_addr);
  207. ata_sff_pause(ap);
  208. }
  209. /*
  210. * pata_s3c_check_status - Read device status register
  211. */
  212. static u8 pata_s3c_check_status(struct ata_port *ap)
  213. {
  214. return ata_inb(ap->host, ap->ioaddr.status_addr);
  215. }
  216. /*
  217. * pata_s3c_check_altstatus - Read alternate device status register
  218. */
  219. static u8 pata_s3c_check_altstatus(struct ata_port *ap)
  220. {
  221. return ata_inb(ap->host, ap->ioaddr.altstatus_addr);
  222. }
  223. /*
  224. * pata_s3c_data_xfer - Transfer data by PIO
  225. */
  226. static unsigned int pata_s3c_data_xfer(struct ata_queued_cmd *qc,
  227. unsigned char *buf, unsigned int buflen, int rw)
  228. {
  229. struct ata_port *ap = qc->dev->link->ap;
  230. struct s3c_ide_info *info = ap->host->private_data;
  231. void __iomem *data_addr = ap->ioaddr.data_addr;
  232. unsigned int words = buflen >> 1, i;
  233. u16 *data_ptr = (u16 *)buf;
  234. /* Requires wait same as in ata_inb/ata_outb */
  235. if (rw == READ)
  236. for (i = 0; i < words; i++, data_ptr++) {
  237. wait_for_host_ready(info);
  238. (void) readw(data_addr);
  239. wait_for_host_ready(info);
  240. *data_ptr = readw(info->ide_addr
  241. + S3C_ATA_PIO_RDATA);
  242. }
  243. else
  244. for (i = 0; i < words; i++, data_ptr++) {
  245. wait_for_host_ready(info);
  246. writew(*data_ptr, data_addr);
  247. }
  248. if (buflen & 0x01)
  249. dev_err(ap->dev, "unexpected trailing data\n");
  250. return words << 1;
  251. }
  252. /*
  253. * pata_s3c_dev_select - Select device on ATA bus
  254. */
  255. static void pata_s3c_dev_select(struct ata_port *ap, unsigned int device)
  256. {
  257. u8 tmp = ATA_DEVICE_OBS;
  258. if (device != 0)
  259. tmp |= ATA_DEV1;
  260. ata_outb(ap->host, tmp, ap->ioaddr.device_addr);
  261. ata_sff_pause(ap);
  262. }
  263. /*
  264. * pata_s3c_devchk - PATA device presence detection
  265. */
  266. static unsigned int pata_s3c_devchk(struct ata_port *ap,
  267. unsigned int device)
  268. {
  269. struct ata_ioports *ioaddr = &ap->ioaddr;
  270. u8 nsect, lbal;
  271. pata_s3c_dev_select(ap, device);
  272. ata_outb(ap->host, 0x55, ioaddr->nsect_addr);
  273. ata_outb(ap->host, 0xaa, ioaddr->lbal_addr);
  274. ata_outb(ap->host, 0xaa, ioaddr->nsect_addr);
  275. ata_outb(ap->host, 0x55, ioaddr->lbal_addr);
  276. ata_outb(ap->host, 0x55, ioaddr->nsect_addr);
  277. ata_outb(ap->host, 0xaa, ioaddr->lbal_addr);
  278. nsect = ata_inb(ap->host, ioaddr->nsect_addr);
  279. lbal = ata_inb(ap->host, ioaddr->lbal_addr);
  280. if ((nsect == 0x55) && (lbal == 0xaa))
  281. return 1; /* we found a device */
  282. return 0; /* nothing found */
  283. }
  284. /*
  285. * pata_s3c_wait_after_reset - wait for devices to become ready after reset
  286. */
  287. static int pata_s3c_wait_after_reset(struct ata_link *link,
  288. unsigned long deadline)
  289. {
  290. int rc;
  291. ata_msleep(link->ap, ATA_WAIT_AFTER_RESET);
  292. /* always check readiness of the master device */
  293. rc = ata_sff_wait_ready(link, deadline);
  294. /* -ENODEV means the odd clown forgot the D7 pulldown resistor
  295. * and TF status is 0xff, bail out on it too.
  296. */
  297. if (rc)
  298. return rc;
  299. return 0;
  300. }
  301. /*
  302. * pata_s3c_bus_softreset - PATA device software reset
  303. */
  304. static int pata_s3c_bus_softreset(struct ata_port *ap,
  305. unsigned long deadline)
  306. {
  307. struct ata_ioports *ioaddr = &ap->ioaddr;
  308. /* software reset. causes dev0 to be selected */
  309. ata_outb(ap->host, ap->ctl, ioaddr->ctl_addr);
  310. udelay(20);
  311. ata_outb(ap->host, ap->ctl | ATA_SRST, ioaddr->ctl_addr);
  312. udelay(20);
  313. ata_outb(ap->host, ap->ctl, ioaddr->ctl_addr);
  314. ap->last_ctl = ap->ctl;
  315. return pata_s3c_wait_after_reset(&ap->link, deadline);
  316. }
  317. /*
  318. * pata_s3c_softreset - reset host port via ATA SRST
  319. */
  320. static int pata_s3c_softreset(struct ata_link *link, unsigned int *classes,
  321. unsigned long deadline)
  322. {
  323. struct ata_port *ap = link->ap;
  324. unsigned int devmask = 0;
  325. int rc;
  326. u8 err;
  327. /* determine if device 0 is present */
  328. if (pata_s3c_devchk(ap, 0))
  329. devmask |= (1 << 0);
  330. /* select device 0 again */
  331. pata_s3c_dev_select(ap, 0);
  332. /* issue bus reset */
  333. rc = pata_s3c_bus_softreset(ap, deadline);
  334. /* if link is occupied, -ENODEV too is an error */
  335. if (rc && rc != -ENODEV) {
  336. ata_link_err(link, "SRST failed (errno=%d)\n", rc);
  337. return rc;
  338. }
  339. /* determine by signature whether we have ATA or ATAPI devices */
  340. classes[0] = ata_sff_dev_classify(&ap->link.device[0],
  341. devmask & (1 << 0), &err);
  342. return 0;
  343. }
  344. /*
  345. * pata_s3c_set_devctl - Write device control register
  346. */
  347. static void pata_s3c_set_devctl(struct ata_port *ap, u8 ctl)
  348. {
  349. ata_outb(ap->host, ctl, ap->ioaddr.ctl_addr);
  350. }
  351. static struct scsi_host_template pata_s3c_sht = {
  352. ATA_PIO_SHT(DRV_NAME),
  353. };
  354. static struct ata_port_operations pata_s3c_port_ops = {
  355. .inherits = &ata_sff_port_ops,
  356. .sff_check_status = pata_s3c_check_status,
  357. .sff_check_altstatus = pata_s3c_check_altstatus,
  358. .sff_tf_load = pata_s3c_tf_load,
  359. .sff_tf_read = pata_s3c_tf_read,
  360. .sff_data_xfer = pata_s3c_data_xfer,
  361. .sff_exec_command = pata_s3c_exec_command,
  362. .sff_dev_select = pata_s3c_dev_select,
  363. .sff_set_devctl = pata_s3c_set_devctl,
  364. .softreset = pata_s3c_softreset,
  365. .set_piomode = pata_s3c_set_piomode,
  366. };
  367. static struct ata_port_operations pata_s5p_port_ops = {
  368. .inherits = &ata_sff_port_ops,
  369. .set_piomode = pata_s3c_set_piomode,
  370. };
  371. static void pata_s3c_enable(void __iomem *s3c_ide_regbase, bool state)
  372. {
  373. u32 temp = readl(s3c_ide_regbase + S3C_ATA_CTRL);
  374. temp = state ? (temp | 1) : (temp & ~1);
  375. writel(temp, s3c_ide_regbase + S3C_ATA_CTRL);
  376. }
  377. static irqreturn_t pata_s3c_irq(int irq, void *dev_instance)
  378. {
  379. struct ata_host *host = dev_instance;
  380. struct s3c_ide_info *info = host->private_data;
  381. u32 reg;
  382. reg = readl(info->ide_addr + S3C_ATA_IRQ);
  383. writel(reg, info->ide_addr + S3C_ATA_IRQ);
  384. return ata_sff_interrupt(irq, dev_instance);
  385. }
  386. static void pata_s3c_hwinit(struct s3c_ide_info *info,
  387. struct s3c_ide_platdata *pdata)
  388. {
  389. switch (info->cpu_type) {
  390. case TYPE_S3C64XX:
  391. /* Configure as big endian */
  392. pata_s3c_cfg_mode(info->sfr_addr);
  393. pata_s3c_set_endian(info->ide_addr, 1);
  394. pata_s3c_enable(info->ide_addr, true);
  395. msleep(100);
  396. /* Remove IRQ Status */
  397. writel(0x1f, info->ide_addr + S3C_ATA_IRQ);
  398. writel(0x1b, info->ide_addr + S3C_ATA_IRQ_MSK);
  399. break;
  400. case TYPE_S5PV210:
  401. /* Configure as little endian */
  402. pata_s3c_set_endian(info->ide_addr, 0);
  403. pata_s3c_enable(info->ide_addr, true);
  404. msleep(100);
  405. /* Remove IRQ Status */
  406. writel(0x3f, info->ide_addr + S3C_ATA_IRQ);
  407. writel(0x3f, info->ide_addr + S3C_ATA_IRQ_MSK);
  408. break;
  409. default:
  410. BUG();
  411. }
  412. }
  413. static int __init pata_s3c_probe(struct platform_device *pdev)
  414. {
  415. struct s3c_ide_platdata *pdata = dev_get_platdata(&pdev->dev);
  416. struct device *dev = &pdev->dev;
  417. struct s3c_ide_info *info;
  418. struct resource *res;
  419. struct ata_port *ap;
  420. struct ata_host *host;
  421. enum s3c_cpu_type cpu_type;
  422. int ret;
  423. cpu_type = platform_get_device_id(pdev)->driver_data;
  424. info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL);
  425. if (!info)
  426. return -ENOMEM;
  427. info->irq = platform_get_irq(pdev, 0);
  428. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  429. info->ide_addr = devm_ioremap_resource(dev, res);
  430. if (IS_ERR(info->ide_addr))
  431. return PTR_ERR(info->ide_addr);
  432. info->clk = devm_clk_get(&pdev->dev, "cfcon");
  433. if (IS_ERR(info->clk)) {
  434. dev_err(dev, "failed to get access to cf controller clock\n");
  435. ret = PTR_ERR(info->clk);
  436. info->clk = NULL;
  437. return ret;
  438. }
  439. clk_enable(info->clk);
  440. /* init ata host */
  441. host = ata_host_alloc(dev, 1);
  442. if (!host) {
  443. dev_err(dev, "failed to allocate ide host\n");
  444. ret = -ENOMEM;
  445. goto stop_clk;
  446. }
  447. ap = host->ports[0];
  448. ap->pio_mask = ATA_PIO4;
  449. if (cpu_type == TYPE_S3C64XX) {
  450. ap->ops = &pata_s3c_port_ops;
  451. info->sfr_addr = info->ide_addr + 0x1800;
  452. info->ide_addr += 0x1900;
  453. info->fifo_status_reg = 0x94;
  454. } else {
  455. ap->ops = &pata_s5p_port_ops;
  456. info->fifo_status_reg = 0x84;
  457. }
  458. info->cpu_type = cpu_type;
  459. if (info->irq <= 0) {
  460. ap->flags |= ATA_FLAG_PIO_POLLING;
  461. info->irq = 0;
  462. ata_port_desc(ap, "no IRQ, using PIO polling\n");
  463. }
  464. ap->ioaddr.cmd_addr = info->ide_addr + S3C_ATA_CMD;
  465. ap->ioaddr.data_addr = info->ide_addr + S3C_ATA_PIO_DTR;
  466. ap->ioaddr.error_addr = info->ide_addr + S3C_ATA_PIO_FED;
  467. ap->ioaddr.feature_addr = info->ide_addr + S3C_ATA_PIO_FED;
  468. ap->ioaddr.nsect_addr = info->ide_addr + S3C_ATA_PIO_SCR;
  469. ap->ioaddr.lbal_addr = info->ide_addr + S3C_ATA_PIO_LLR;
  470. ap->ioaddr.lbam_addr = info->ide_addr + S3C_ATA_PIO_LMR;
  471. ap->ioaddr.lbah_addr = info->ide_addr + S3C_ATA_PIO_LHR;
  472. ap->ioaddr.device_addr = info->ide_addr + S3C_ATA_PIO_DVR;
  473. ap->ioaddr.status_addr = info->ide_addr + S3C_ATA_PIO_CSD;
  474. ap->ioaddr.command_addr = info->ide_addr + S3C_ATA_PIO_CSD;
  475. ap->ioaddr.altstatus_addr = info->ide_addr + S3C_ATA_PIO_DAD;
  476. ap->ioaddr.ctl_addr = info->ide_addr + S3C_ATA_PIO_DAD;
  477. ata_port_desc(ap, "mmio cmd 0x%llx ",
  478. (unsigned long long)res->start);
  479. host->private_data = info;
  480. if (pdata && pdata->setup_gpio)
  481. pdata->setup_gpio();
  482. /* Set endianness and enable the interface */
  483. pata_s3c_hwinit(info, pdata);
  484. ret = ata_host_activate(host, info->irq,
  485. info->irq ? pata_s3c_irq : NULL,
  486. 0, &pata_s3c_sht);
  487. if (ret)
  488. goto stop_clk;
  489. return 0;
  490. stop_clk:
  491. clk_disable(info->clk);
  492. return ret;
  493. }
  494. static int __exit pata_s3c_remove(struct platform_device *pdev)
  495. {
  496. struct ata_host *host = platform_get_drvdata(pdev);
  497. struct s3c_ide_info *info = host->private_data;
  498. ata_host_detach(host);
  499. clk_disable(info->clk);
  500. return 0;
  501. }
  502. #ifdef CONFIG_PM_SLEEP
  503. static int pata_s3c_suspend(struct device *dev)
  504. {
  505. struct ata_host *host = dev_get_drvdata(dev);
  506. return ata_host_suspend(host, PMSG_SUSPEND);
  507. }
  508. static int pata_s3c_resume(struct device *dev)
  509. {
  510. struct ata_host *host = dev_get_drvdata(dev);
  511. struct s3c_ide_platdata *pdata = dev_get_platdata(dev);
  512. struct s3c_ide_info *info = host->private_data;
  513. pata_s3c_hwinit(info, pdata);
  514. ata_host_resume(host);
  515. return 0;
  516. }
  517. static const struct dev_pm_ops pata_s3c_pm_ops = {
  518. .suspend = pata_s3c_suspend,
  519. .resume = pata_s3c_resume,
  520. };
  521. #endif
  522. /* driver device registration */
  523. static const struct platform_device_id pata_s3c_driver_ids[] = {
  524. {
  525. .name = "s3c64xx-pata",
  526. .driver_data = TYPE_S3C64XX,
  527. }, {
  528. .name = "s5pv210-pata",
  529. .driver_data = TYPE_S5PV210,
  530. },
  531. { }
  532. };
  533. MODULE_DEVICE_TABLE(platform, pata_s3c_driver_ids);
  534. static struct platform_driver pata_s3c_driver = {
  535. .remove = __exit_p(pata_s3c_remove),
  536. .id_table = pata_s3c_driver_ids,
  537. .driver = {
  538. .name = DRV_NAME,
  539. #ifdef CONFIG_PM_SLEEP
  540. .pm = &pata_s3c_pm_ops,
  541. #endif
  542. },
  543. };
  544. module_platform_driver_probe(pata_s3c_driver, pata_s3c_probe);
  545. MODULE_AUTHOR("Abhilash Kesavan, <a.kesavan@samsung.com>");
  546. MODULE_DESCRIPTION("low-level driver for Samsung PATA controller");
  547. MODULE_LICENSE("GPL");
  548. MODULE_VERSION(DRV_VERSION);