pata_pdc202xx_old.c 10.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * pata_pdc202xx_old.c - Promise PDC202xx PATA for new ATA layer
  4. * (C) 2005 Red Hat Inc
  5. * Alan Cox <alan@lxorguk.ukuu.org.uk>
  6. * (C) 2007,2009,2010 Bartlomiej Zolnierkiewicz
  7. *
  8. * Based in part on linux/drivers/ide/pci/pdc202xx_old.c
  9. *
  10. * First cut with LBA48/ATAPI
  11. *
  12. * TODO:
  13. * Channel interlock/reset on both required ?
  14. */
  15. #include <linux/kernel.h>
  16. #include <linux/module.h>
  17. #include <linux/pci.h>
  18. #include <linux/blkdev.h>
  19. #include <linux/delay.h>
  20. #include <scsi/scsi_host.h>
  21. #include <linux/libata.h>
  22. #define DRV_NAME "pata_pdc202xx_old"
  23. #define DRV_VERSION "0.4.3"
  24. static int pdc2026x_cable_detect(struct ata_port *ap)
  25. {
  26. struct pci_dev *pdev = to_pci_dev(ap->host->dev);
  27. u16 cis;
  28. pci_read_config_word(pdev, 0x50, &cis);
  29. if (cis & (1 << (10 + ap->port_no)))
  30. return ATA_CBL_PATA40;
  31. return ATA_CBL_PATA80;
  32. }
  33. static void pdc202xx_exec_command(struct ata_port *ap,
  34. const struct ata_taskfile *tf)
  35. {
  36. DPRINTK("ata%u: cmd 0x%X\n", ap->print_id, tf->command);
  37. iowrite8(tf->command, ap->ioaddr.command_addr);
  38. ndelay(400);
  39. }
  40. static bool pdc202xx_irq_check(struct ata_port *ap)
  41. {
  42. struct pci_dev *pdev = to_pci_dev(ap->host->dev);
  43. unsigned long master = pci_resource_start(pdev, 4);
  44. u8 sc1d = inb(master + 0x1d);
  45. if (ap->port_no) {
  46. /*
  47. * bit 7: error, bit 6: interrupting,
  48. * bit 5: FIFO full, bit 4: FIFO empty
  49. */
  50. return sc1d & 0x40;
  51. } else {
  52. /*
  53. * bit 3: error, bit 2: interrupting,
  54. * bit 1: FIFO full, bit 0: FIFO empty
  55. */
  56. return sc1d & 0x04;
  57. }
  58. }
  59. /**
  60. * pdc202xx_configure_piomode - set chip PIO timing
  61. * @ap: ATA interface
  62. * @adev: ATA device
  63. * @pio: PIO mode
  64. *
  65. * Called to do the PIO mode setup. Our timing registers are shared
  66. * so a configure_dmamode call will undo any work we do here and vice
  67. * versa
  68. */
  69. static void pdc202xx_configure_piomode(struct ata_port *ap, struct ata_device *adev, int pio)
  70. {
  71. struct pci_dev *pdev = to_pci_dev(ap->host->dev);
  72. int port = 0x60 + 8 * ap->port_no + 4 * adev->devno;
  73. static u16 pio_timing[5] = {
  74. 0x0913, 0x050C , 0x0308, 0x0206, 0x0104
  75. };
  76. u8 r_ap, r_bp;
  77. pci_read_config_byte(pdev, port, &r_ap);
  78. pci_read_config_byte(pdev, port + 1, &r_bp);
  79. r_ap &= ~0x3F; /* Preserve ERRDY_EN, SYNC_IN */
  80. r_bp &= ~0x1F;
  81. r_ap |= (pio_timing[pio] >> 8);
  82. r_bp |= (pio_timing[pio] & 0xFF);
  83. if (ata_pio_need_iordy(adev))
  84. r_ap |= 0x20; /* IORDY enable */
  85. if (adev->class == ATA_DEV_ATA)
  86. r_ap |= 0x10; /* FIFO enable */
  87. pci_write_config_byte(pdev, port, r_ap);
  88. pci_write_config_byte(pdev, port + 1, r_bp);
  89. }
  90. /**
  91. * pdc202xx_set_piomode - set initial PIO mode data
  92. * @ap: ATA interface
  93. * @adev: ATA device
  94. *
  95. * Called to do the PIO mode setup. Our timing registers are shared
  96. * but we want to set the PIO timing by default.
  97. */
  98. static void pdc202xx_set_piomode(struct ata_port *ap, struct ata_device *adev)
  99. {
  100. pdc202xx_configure_piomode(ap, adev, adev->pio_mode - XFER_PIO_0);
  101. }
  102. /**
  103. * pdc202xx_configure_dmamode - set DMA mode in chip
  104. * @ap: ATA interface
  105. * @adev: ATA device
  106. *
  107. * Load DMA cycle times into the chip ready for a DMA transfer
  108. * to occur.
  109. */
  110. static void pdc202xx_set_dmamode(struct ata_port *ap, struct ata_device *adev)
  111. {
  112. struct pci_dev *pdev = to_pci_dev(ap->host->dev);
  113. int port = 0x60 + 8 * ap->port_no + 4 * adev->devno;
  114. static u8 udma_timing[6][2] = {
  115. { 0x60, 0x03 }, /* 33 Mhz Clock */
  116. { 0x40, 0x02 },
  117. { 0x20, 0x01 },
  118. { 0x40, 0x02 }, /* 66 Mhz Clock */
  119. { 0x20, 0x01 },
  120. { 0x20, 0x01 }
  121. };
  122. static u8 mdma_timing[3][2] = {
  123. { 0xe0, 0x0f },
  124. { 0x60, 0x04 },
  125. { 0x60, 0x03 },
  126. };
  127. u8 r_bp, r_cp;
  128. pci_read_config_byte(pdev, port + 1, &r_bp);
  129. pci_read_config_byte(pdev, port + 2, &r_cp);
  130. r_bp &= ~0xE0;
  131. r_cp &= ~0x0F;
  132. if (adev->dma_mode >= XFER_UDMA_0) {
  133. int speed = adev->dma_mode - XFER_UDMA_0;
  134. r_bp |= udma_timing[speed][0];
  135. r_cp |= udma_timing[speed][1];
  136. } else {
  137. int speed = adev->dma_mode - XFER_MW_DMA_0;
  138. r_bp |= mdma_timing[speed][0];
  139. r_cp |= mdma_timing[speed][1];
  140. }
  141. pci_write_config_byte(pdev, port + 1, r_bp);
  142. pci_write_config_byte(pdev, port + 2, r_cp);
  143. }
  144. /**
  145. * pdc2026x_bmdma_start - DMA engine begin
  146. * @qc: ATA command
  147. *
  148. * In UDMA3 or higher we have to clock switch for the duration of the
  149. * DMA transfer sequence.
  150. *
  151. * Note: The host lock held by the libata layer protects
  152. * us from two channels both trying to set DMA bits at once
  153. */
  154. static void pdc2026x_bmdma_start(struct ata_queued_cmd *qc)
  155. {
  156. struct ata_port *ap = qc->ap;
  157. struct ata_device *adev = qc->dev;
  158. struct ata_taskfile *tf = &qc->tf;
  159. int sel66 = ap->port_no ? 0x08: 0x02;
  160. void __iomem *master = ap->host->ports[0]->ioaddr.bmdma_addr;
  161. void __iomem *clock = master + 0x11;
  162. void __iomem *atapi_reg = master + 0x20 + (4 * ap->port_no);
  163. u32 len;
  164. /* Check we keep host level locking here */
  165. if (adev->dma_mode > XFER_UDMA_2)
  166. iowrite8(ioread8(clock) | sel66, clock);
  167. else
  168. iowrite8(ioread8(clock) & ~sel66, clock);
  169. /* The DMA clocks may have been trashed by a reset. FIXME: make conditional
  170. and move to qc_issue ? */
  171. pdc202xx_set_dmamode(ap, qc->dev);
  172. /* Cases the state machine will not complete correctly without help */
  173. if ((tf->flags & ATA_TFLAG_LBA48) || tf->protocol == ATAPI_PROT_DMA) {
  174. len = qc->nbytes / 2;
  175. if (tf->flags & ATA_TFLAG_WRITE)
  176. len |= 0x06000000;
  177. else
  178. len |= 0x05000000;
  179. iowrite32(len, atapi_reg);
  180. }
  181. /* Activate DMA */
  182. ata_bmdma_start(qc);
  183. }
  184. /**
  185. * pdc2026x_bmdma_end - DMA engine stop
  186. * @qc: ATA command
  187. *
  188. * After a DMA completes we need to put the clock back to 33MHz for
  189. * PIO timings.
  190. *
  191. * Note: The host lock held by the libata layer protects
  192. * us from two channels both trying to set DMA bits at once
  193. */
  194. static void pdc2026x_bmdma_stop(struct ata_queued_cmd *qc)
  195. {
  196. struct ata_port *ap = qc->ap;
  197. struct ata_device *adev = qc->dev;
  198. struct ata_taskfile *tf = &qc->tf;
  199. int sel66 = ap->port_no ? 0x08: 0x02;
  200. /* The clock bits are in the same register for both channels */
  201. void __iomem *master = ap->host->ports[0]->ioaddr.bmdma_addr;
  202. void __iomem *clock = master + 0x11;
  203. void __iomem *atapi_reg = master + 0x20 + (4 * ap->port_no);
  204. /* Cases the state machine will not complete correctly */
  205. if (tf->protocol == ATAPI_PROT_DMA || (tf->flags & ATA_TFLAG_LBA48)) {
  206. iowrite32(0, atapi_reg);
  207. iowrite8(ioread8(clock) & ~sel66, clock);
  208. }
  209. /* Flip back to 33Mhz for PIO */
  210. if (adev->dma_mode > XFER_UDMA_2)
  211. iowrite8(ioread8(clock) & ~sel66, clock);
  212. ata_bmdma_stop(qc);
  213. pdc202xx_set_piomode(ap, adev);
  214. }
  215. /**
  216. * pdc2026x_dev_config - device setup hook
  217. * @adev: newly found device
  218. *
  219. * Perform chip specific early setup. We need to lock the transfer
  220. * sizes to 8bit to avoid making the state engine on the 2026x cards
  221. * barf.
  222. */
  223. static void pdc2026x_dev_config(struct ata_device *adev)
  224. {
  225. adev->max_sectors = 256;
  226. }
  227. static int pdc2026x_port_start(struct ata_port *ap)
  228. {
  229. void __iomem *bmdma = ap->ioaddr.bmdma_addr;
  230. if (bmdma) {
  231. /* Enable burst mode */
  232. u8 burst = ioread8(bmdma + 0x1f);
  233. iowrite8(burst | 0x01, bmdma + 0x1f);
  234. }
  235. return ata_bmdma_port_start(ap);
  236. }
  237. /**
  238. * pdc2026x_check_atapi_dma - Check whether ATAPI DMA can be supported for this command
  239. * @qc: Metadata associated with taskfile to check
  240. *
  241. * Just say no - not supported on older Promise.
  242. *
  243. * LOCKING:
  244. * None (inherited from caller).
  245. *
  246. * RETURNS: 0 when ATAPI DMA can be used
  247. * 1 otherwise
  248. */
  249. static int pdc2026x_check_atapi_dma(struct ata_queued_cmd *qc)
  250. {
  251. return 1;
  252. }
  253. static struct scsi_host_template pdc202xx_sht = {
  254. ATA_BMDMA_SHT(DRV_NAME),
  255. };
  256. static struct ata_port_operations pdc2024x_port_ops = {
  257. .inherits = &ata_bmdma_port_ops,
  258. .cable_detect = ata_cable_40wire,
  259. .set_piomode = pdc202xx_set_piomode,
  260. .set_dmamode = pdc202xx_set_dmamode,
  261. .sff_exec_command = pdc202xx_exec_command,
  262. .sff_irq_check = pdc202xx_irq_check,
  263. };
  264. static struct ata_port_operations pdc2026x_port_ops = {
  265. .inherits = &pdc2024x_port_ops,
  266. .check_atapi_dma = pdc2026x_check_atapi_dma,
  267. .bmdma_start = pdc2026x_bmdma_start,
  268. .bmdma_stop = pdc2026x_bmdma_stop,
  269. .cable_detect = pdc2026x_cable_detect,
  270. .dev_config = pdc2026x_dev_config,
  271. .port_start = pdc2026x_port_start,
  272. .sff_exec_command = pdc202xx_exec_command,
  273. .sff_irq_check = pdc202xx_irq_check,
  274. };
  275. static int pdc202xx_init_one(struct pci_dev *dev, const struct pci_device_id *id)
  276. {
  277. static const struct ata_port_info info[3] = {
  278. {
  279. .flags = ATA_FLAG_SLAVE_POSS,
  280. .pio_mask = ATA_PIO4,
  281. .mwdma_mask = ATA_MWDMA2,
  282. .udma_mask = ATA_UDMA2,
  283. .port_ops = &pdc2024x_port_ops
  284. },
  285. {
  286. .flags = ATA_FLAG_SLAVE_POSS,
  287. .pio_mask = ATA_PIO4,
  288. .mwdma_mask = ATA_MWDMA2,
  289. .udma_mask = ATA_UDMA4,
  290. .port_ops = &pdc2026x_port_ops
  291. },
  292. {
  293. .flags = ATA_FLAG_SLAVE_POSS,
  294. .pio_mask = ATA_PIO4,
  295. .mwdma_mask = ATA_MWDMA2,
  296. .udma_mask = ATA_UDMA5,
  297. .port_ops = &pdc2026x_port_ops
  298. }
  299. };
  300. const struct ata_port_info *ppi[] = { &info[id->driver_data], NULL };
  301. if (dev->device == PCI_DEVICE_ID_PROMISE_20265) {
  302. struct pci_dev *bridge = dev->bus->self;
  303. /* Don't grab anything behind a Promise I2O RAID */
  304. if (bridge && bridge->vendor == PCI_VENDOR_ID_INTEL) {
  305. if (bridge->device == PCI_DEVICE_ID_INTEL_I960)
  306. return -ENODEV;
  307. if (bridge->device == PCI_DEVICE_ID_INTEL_I960RM)
  308. return -ENODEV;
  309. }
  310. }
  311. return ata_pci_bmdma_init_one(dev, ppi, &pdc202xx_sht, NULL, 0);
  312. }
  313. static const struct pci_device_id pdc202xx[] = {
  314. { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20246), 0 },
  315. { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20262), 1 },
  316. { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20263), 1 },
  317. { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20265), 2 },
  318. { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20267), 2 },
  319. { },
  320. };
  321. static struct pci_driver pdc202xx_pci_driver = {
  322. .name = DRV_NAME,
  323. .id_table = pdc202xx,
  324. .probe = pdc202xx_init_one,
  325. .remove = ata_pci_remove_one,
  326. #ifdef CONFIG_PM_SLEEP
  327. .suspend = ata_pci_device_suspend,
  328. .resume = ata_pci_device_resume,
  329. #endif
  330. };
  331. module_pci_driver(pdc202xx_pci_driver);
  332. MODULE_AUTHOR("Alan Cox");
  333. MODULE_DESCRIPTION("low-level driver for Promise 2024x and 20262-20267");
  334. MODULE_LICENSE("GPL");
  335. MODULE_DEVICE_TABLE(pci, pdc202xx);
  336. MODULE_VERSION(DRV_VERSION);