pata_pdc2027x.c 21 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775
  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Promise PATA TX2/TX4/TX2000/133 IDE driver for pdc20268 to pdc20277.
  4. *
  5. * Ported to libata by:
  6. * Albert Lee <albertcc@tw.ibm.com> IBM Corporation
  7. *
  8. * Copyright (C) 1998-2002 Andre Hedrick <andre@linux-ide.org>
  9. * Portions Copyright (C) 1999 Promise Technology, Inc.
  10. *
  11. * Author: Frank Tiernan (frankt@promise.com)
  12. * Released under terms of General Public License
  13. *
  14. * libata documentation is available via 'make {ps|pdf}docs',
  15. * as Documentation/driver-api/libata.rst
  16. *
  17. * Hardware information only available under NDA.
  18. */
  19. #include <linux/kernel.h>
  20. #include <linux/module.h>
  21. #include <linux/pci.h>
  22. #include <linux/blkdev.h>
  23. #include <linux/delay.h>
  24. #include <linux/device.h>
  25. #include <linux/ktime.h>
  26. #include <scsi/scsi.h>
  27. #include <scsi/scsi_host.h>
  28. #include <scsi/scsi_cmnd.h>
  29. #include <linux/libata.h>
  30. #define DRV_NAME "pata_pdc2027x"
  31. #define DRV_VERSION "1.0"
  32. #undef PDC_DEBUG
  33. #ifdef PDC_DEBUG
  34. #define PDPRINTK(fmt, args...) printk(KERN_ERR "%s: " fmt, __func__, ## args)
  35. #else
  36. #define PDPRINTK(fmt, args...)
  37. #endif
  38. enum {
  39. PDC_MMIO_BAR = 5,
  40. PDC_UDMA_100 = 0,
  41. PDC_UDMA_133 = 1,
  42. PDC_100_MHZ = 100000000,
  43. PDC_133_MHZ = 133333333,
  44. PDC_SYS_CTL = 0x1100,
  45. PDC_ATA_CTL = 0x1104,
  46. PDC_GLOBAL_CTL = 0x1108,
  47. PDC_CTCR0 = 0x110C,
  48. PDC_CTCR1 = 0x1110,
  49. PDC_BYTE_COUNT = 0x1120,
  50. PDC_PLL_CTL = 0x1202,
  51. };
  52. static int pdc2027x_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
  53. #ifdef CONFIG_PM_SLEEP
  54. static int pdc2027x_reinit_one(struct pci_dev *pdev);
  55. #endif
  56. static int pdc2027x_prereset(struct ata_link *link, unsigned long deadline);
  57. static void pdc2027x_set_piomode(struct ata_port *ap, struct ata_device *adev);
  58. static void pdc2027x_set_dmamode(struct ata_port *ap, struct ata_device *adev);
  59. static int pdc2027x_check_atapi_dma(struct ata_queued_cmd *qc);
  60. static unsigned long pdc2027x_mode_filter(struct ata_device *adev, unsigned long mask);
  61. static int pdc2027x_cable_detect(struct ata_port *ap);
  62. static int pdc2027x_set_mode(struct ata_link *link, struct ata_device **r_failed);
  63. /*
  64. * ATA Timing Tables based on 133MHz controller clock.
  65. * These tables are only used when the controller is in 133MHz clock.
  66. * If the controller is in 100MHz clock, the ASIC hardware will
  67. * set the timing registers automatically when "set feature" command
  68. * is issued to the device. However, if the controller clock is 133MHz,
  69. * the following tables must be used.
  70. */
  71. static const struct pdc2027x_pio_timing {
  72. u8 value0, value1, value2;
  73. } pdc2027x_pio_timing_tbl[] = {
  74. { 0xfb, 0x2b, 0xac }, /* PIO mode 0 */
  75. { 0x46, 0x29, 0xa4 }, /* PIO mode 1 */
  76. { 0x23, 0x26, 0x64 }, /* PIO mode 2 */
  77. { 0x27, 0x0d, 0x35 }, /* PIO mode 3, IORDY on, Prefetch off */
  78. { 0x23, 0x09, 0x25 }, /* PIO mode 4, IORDY on, Prefetch off */
  79. };
  80. static const struct pdc2027x_mdma_timing {
  81. u8 value0, value1;
  82. } pdc2027x_mdma_timing_tbl[] = {
  83. { 0xdf, 0x5f }, /* MDMA mode 0 */
  84. { 0x6b, 0x27 }, /* MDMA mode 1 */
  85. { 0x69, 0x25 }, /* MDMA mode 2 */
  86. };
  87. static const struct pdc2027x_udma_timing {
  88. u8 value0, value1, value2;
  89. } pdc2027x_udma_timing_tbl[] = {
  90. { 0x4a, 0x0f, 0xd5 }, /* UDMA mode 0 */
  91. { 0x3a, 0x0a, 0xd0 }, /* UDMA mode 1 */
  92. { 0x2a, 0x07, 0xcd }, /* UDMA mode 2 */
  93. { 0x1a, 0x05, 0xcd }, /* UDMA mode 3 */
  94. { 0x1a, 0x03, 0xcd }, /* UDMA mode 4 */
  95. { 0x1a, 0x02, 0xcb }, /* UDMA mode 5 */
  96. { 0x1a, 0x01, 0xcb }, /* UDMA mode 6 */
  97. };
  98. static const struct pci_device_id pdc2027x_pci_tbl[] = {
  99. { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20268), PDC_UDMA_100 },
  100. { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20269), PDC_UDMA_133 },
  101. { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20270), PDC_UDMA_100 },
  102. { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20271), PDC_UDMA_133 },
  103. { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20275), PDC_UDMA_133 },
  104. { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20276), PDC_UDMA_133 },
  105. { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20277), PDC_UDMA_133 },
  106. { } /* terminate list */
  107. };
  108. static struct pci_driver pdc2027x_pci_driver = {
  109. .name = DRV_NAME,
  110. .id_table = pdc2027x_pci_tbl,
  111. .probe = pdc2027x_init_one,
  112. .remove = ata_pci_remove_one,
  113. #ifdef CONFIG_PM_SLEEP
  114. .suspend = ata_pci_device_suspend,
  115. .resume = pdc2027x_reinit_one,
  116. #endif
  117. };
  118. static struct scsi_host_template pdc2027x_sht = {
  119. ATA_BMDMA_SHT(DRV_NAME),
  120. };
  121. static struct ata_port_operations pdc2027x_pata100_ops = {
  122. .inherits = &ata_bmdma_port_ops,
  123. .check_atapi_dma = pdc2027x_check_atapi_dma,
  124. .cable_detect = pdc2027x_cable_detect,
  125. .prereset = pdc2027x_prereset,
  126. };
  127. static struct ata_port_operations pdc2027x_pata133_ops = {
  128. .inherits = &pdc2027x_pata100_ops,
  129. .mode_filter = pdc2027x_mode_filter,
  130. .set_piomode = pdc2027x_set_piomode,
  131. .set_dmamode = pdc2027x_set_dmamode,
  132. .set_mode = pdc2027x_set_mode,
  133. };
  134. static struct ata_port_info pdc2027x_port_info[] = {
  135. /* PDC_UDMA_100 */
  136. {
  137. .flags = ATA_FLAG_SLAVE_POSS,
  138. .pio_mask = ATA_PIO4,
  139. .mwdma_mask = ATA_MWDMA2,
  140. .udma_mask = ATA_UDMA5,
  141. .port_ops = &pdc2027x_pata100_ops,
  142. },
  143. /* PDC_UDMA_133 */
  144. {
  145. .flags = ATA_FLAG_SLAVE_POSS,
  146. .pio_mask = ATA_PIO4,
  147. .mwdma_mask = ATA_MWDMA2,
  148. .udma_mask = ATA_UDMA6,
  149. .port_ops = &pdc2027x_pata133_ops,
  150. },
  151. };
  152. MODULE_AUTHOR("Andre Hedrick, Frank Tiernan, Albert Lee");
  153. MODULE_DESCRIPTION("libata driver module for Promise PDC20268 to PDC20277");
  154. MODULE_LICENSE("GPL");
  155. MODULE_VERSION(DRV_VERSION);
  156. MODULE_DEVICE_TABLE(pci, pdc2027x_pci_tbl);
  157. /**
  158. * port_mmio - Get the MMIO address of PDC2027x extended registers
  159. * @ap: Port
  160. * @offset: offset from mmio base
  161. */
  162. static inline void __iomem *port_mmio(struct ata_port *ap, unsigned int offset)
  163. {
  164. return ap->host->iomap[PDC_MMIO_BAR] + ap->port_no * 0x100 + offset;
  165. }
  166. /**
  167. * dev_mmio - Get the MMIO address of PDC2027x extended registers
  168. * @ap: Port
  169. * @adev: device
  170. * @offset: offset from mmio base
  171. */
  172. static inline void __iomem *dev_mmio(struct ata_port *ap, struct ata_device *adev, unsigned int offset)
  173. {
  174. u8 adj = (adev->devno) ? 0x08 : 0x00;
  175. return port_mmio(ap, offset) + adj;
  176. }
  177. /**
  178. * pdc2027x_pata_cable_detect - Probe host controller cable detect info
  179. * @ap: Port for which cable detect info is desired
  180. *
  181. * Read 80c cable indicator from Promise extended register.
  182. * This register is latched when the system is reset.
  183. *
  184. * LOCKING:
  185. * None (inherited from caller).
  186. */
  187. static int pdc2027x_cable_detect(struct ata_port *ap)
  188. {
  189. u32 cgcr;
  190. /* check cable detect results */
  191. cgcr = ioread32(port_mmio(ap, PDC_GLOBAL_CTL));
  192. if (cgcr & (1 << 26))
  193. goto cbl40;
  194. PDPRINTK("No cable or 80-conductor cable on port %d\n", ap->port_no);
  195. return ATA_CBL_PATA80;
  196. cbl40:
  197. printk(KERN_INFO DRV_NAME ": 40-conductor cable detected on port %d\n", ap->port_no);
  198. return ATA_CBL_PATA40;
  199. }
  200. /**
  201. * pdc2027x_port_enabled - Check PDC ATA control register to see whether the port is enabled.
  202. * @ap: Port to check
  203. */
  204. static inline int pdc2027x_port_enabled(struct ata_port *ap)
  205. {
  206. return ioread8(port_mmio(ap, PDC_ATA_CTL)) & 0x02;
  207. }
  208. /**
  209. * pdc2027x_prereset - prereset for PATA host controller
  210. * @link: Target link
  211. * @deadline: deadline jiffies for the operation
  212. *
  213. * Probeinit including cable detection.
  214. *
  215. * LOCKING:
  216. * None (inherited from caller).
  217. */
  218. static int pdc2027x_prereset(struct ata_link *link, unsigned long deadline)
  219. {
  220. /* Check whether port enabled */
  221. if (!pdc2027x_port_enabled(link->ap))
  222. return -ENOENT;
  223. return ata_sff_prereset(link, deadline);
  224. }
  225. /**
  226. * pdc2720x_mode_filter - mode selection filter
  227. * @adev: ATA device
  228. * @mask: list of modes proposed
  229. *
  230. * Block UDMA on devices that cause trouble with this controller.
  231. */
  232. static unsigned long pdc2027x_mode_filter(struct ata_device *adev, unsigned long mask)
  233. {
  234. unsigned char model_num[ATA_ID_PROD_LEN + 1];
  235. struct ata_device *pair = ata_dev_pair(adev);
  236. if (adev->class != ATA_DEV_ATA || adev->devno == 0 || pair == NULL)
  237. return mask;
  238. /* Check for slave of a Maxtor at UDMA6 */
  239. ata_id_c_string(pair->id, model_num, ATA_ID_PROD,
  240. ATA_ID_PROD_LEN + 1);
  241. /* If the master is a maxtor in UDMA6 then the slave should not use UDMA 6 */
  242. if (strstr(model_num, "Maxtor") == NULL && pair->dma_mode == XFER_UDMA_6)
  243. mask &= ~ (1 << (6 + ATA_SHIFT_UDMA));
  244. return mask;
  245. }
  246. /**
  247. * pdc2027x_set_piomode - Initialize host controller PATA PIO timings
  248. * @ap: Port to configure
  249. * @adev: um
  250. *
  251. * Set PIO mode for device.
  252. *
  253. * LOCKING:
  254. * None (inherited from caller).
  255. */
  256. static void pdc2027x_set_piomode(struct ata_port *ap, struct ata_device *adev)
  257. {
  258. unsigned int pio = adev->pio_mode - XFER_PIO_0;
  259. u32 ctcr0, ctcr1;
  260. PDPRINTK("adev->pio_mode[%X]\n", adev->pio_mode);
  261. /* Sanity check */
  262. if (pio > 4) {
  263. printk(KERN_ERR DRV_NAME ": Unknown pio mode [%d] ignored\n", pio);
  264. return;
  265. }
  266. /* Set the PIO timing registers using value table for 133MHz */
  267. PDPRINTK("Set pio regs... \n");
  268. ctcr0 = ioread32(dev_mmio(ap, adev, PDC_CTCR0));
  269. ctcr0 &= 0xffff0000;
  270. ctcr0 |= pdc2027x_pio_timing_tbl[pio].value0 |
  271. (pdc2027x_pio_timing_tbl[pio].value1 << 8);
  272. iowrite32(ctcr0, dev_mmio(ap, adev, PDC_CTCR0));
  273. ctcr1 = ioread32(dev_mmio(ap, adev, PDC_CTCR1));
  274. ctcr1 &= 0x00ffffff;
  275. ctcr1 |= (pdc2027x_pio_timing_tbl[pio].value2 << 24);
  276. iowrite32(ctcr1, dev_mmio(ap, adev, PDC_CTCR1));
  277. PDPRINTK("Set pio regs done\n");
  278. PDPRINTK("Set to pio mode[%u] \n", pio);
  279. }
  280. /**
  281. * pdc2027x_set_dmamode - Initialize host controller PATA UDMA timings
  282. * @ap: Port to configure
  283. * @adev: um
  284. *
  285. * Set UDMA mode for device.
  286. *
  287. * LOCKING:
  288. * None (inherited from caller).
  289. */
  290. static void pdc2027x_set_dmamode(struct ata_port *ap, struct ata_device *adev)
  291. {
  292. unsigned int dma_mode = adev->dma_mode;
  293. u32 ctcr0, ctcr1;
  294. if ((dma_mode >= XFER_UDMA_0) &&
  295. (dma_mode <= XFER_UDMA_6)) {
  296. /* Set the UDMA timing registers with value table for 133MHz */
  297. unsigned int udma_mode = dma_mode & 0x07;
  298. if (dma_mode == XFER_UDMA_2) {
  299. /*
  300. * Turn off tHOLD.
  301. * If tHOLD is '1', the hardware will add half clock for data hold time.
  302. * This code segment seems to be no effect. tHOLD will be overwritten below.
  303. */
  304. ctcr1 = ioread32(dev_mmio(ap, adev, PDC_CTCR1));
  305. iowrite32(ctcr1 & ~(1 << 7), dev_mmio(ap, adev, PDC_CTCR1));
  306. }
  307. PDPRINTK("Set udma regs... \n");
  308. ctcr1 = ioread32(dev_mmio(ap, adev, PDC_CTCR1));
  309. ctcr1 &= 0xff000000;
  310. ctcr1 |= pdc2027x_udma_timing_tbl[udma_mode].value0 |
  311. (pdc2027x_udma_timing_tbl[udma_mode].value1 << 8) |
  312. (pdc2027x_udma_timing_tbl[udma_mode].value2 << 16);
  313. iowrite32(ctcr1, dev_mmio(ap, adev, PDC_CTCR1));
  314. PDPRINTK("Set udma regs done\n");
  315. PDPRINTK("Set to udma mode[%u] \n", udma_mode);
  316. } else if ((dma_mode >= XFER_MW_DMA_0) &&
  317. (dma_mode <= XFER_MW_DMA_2)) {
  318. /* Set the MDMA timing registers with value table for 133MHz */
  319. unsigned int mdma_mode = dma_mode & 0x07;
  320. PDPRINTK("Set mdma regs... \n");
  321. ctcr0 = ioread32(dev_mmio(ap, adev, PDC_CTCR0));
  322. ctcr0 &= 0x0000ffff;
  323. ctcr0 |= (pdc2027x_mdma_timing_tbl[mdma_mode].value0 << 16) |
  324. (pdc2027x_mdma_timing_tbl[mdma_mode].value1 << 24);
  325. iowrite32(ctcr0, dev_mmio(ap, adev, PDC_CTCR0));
  326. PDPRINTK("Set mdma regs done\n");
  327. PDPRINTK("Set to mdma mode[%u] \n", mdma_mode);
  328. } else {
  329. printk(KERN_ERR DRV_NAME ": Unknown dma mode [%u] ignored\n", dma_mode);
  330. }
  331. }
  332. /**
  333. * pdc2027x_set_mode - Set the timing registers back to correct values.
  334. * @link: link to configure
  335. * @r_failed: Returned device for failure
  336. *
  337. * The pdc2027x hardware will look at "SET FEATURES" and change the timing registers
  338. * automatically. The values set by the hardware might be incorrect, under 133Mhz PLL.
  339. * This function overwrites the possibly incorrect values set by the hardware to be correct.
  340. */
  341. static int pdc2027x_set_mode(struct ata_link *link, struct ata_device **r_failed)
  342. {
  343. struct ata_port *ap = link->ap;
  344. struct ata_device *dev;
  345. int rc;
  346. rc = ata_do_set_mode(link, r_failed);
  347. if (rc < 0)
  348. return rc;
  349. ata_for_each_dev(dev, link, ENABLED) {
  350. pdc2027x_set_piomode(ap, dev);
  351. /*
  352. * Enable prefetch if the device support PIO only.
  353. */
  354. if (dev->xfer_shift == ATA_SHIFT_PIO) {
  355. u32 ctcr1 = ioread32(dev_mmio(ap, dev, PDC_CTCR1));
  356. ctcr1 |= (1 << 25);
  357. iowrite32(ctcr1, dev_mmio(ap, dev, PDC_CTCR1));
  358. PDPRINTK("Turn on prefetch\n");
  359. } else {
  360. pdc2027x_set_dmamode(ap, dev);
  361. }
  362. }
  363. return 0;
  364. }
  365. /**
  366. * pdc2027x_check_atapi_dma - Check whether ATAPI DMA can be supported for this command
  367. * @qc: Metadata associated with taskfile to check
  368. *
  369. * LOCKING:
  370. * None (inherited from caller).
  371. *
  372. * RETURNS: 0 when ATAPI DMA can be used
  373. * 1 otherwise
  374. */
  375. static int pdc2027x_check_atapi_dma(struct ata_queued_cmd *qc)
  376. {
  377. struct scsi_cmnd *cmd = qc->scsicmd;
  378. u8 *scsicmd = cmd->cmnd;
  379. int rc = 1; /* atapi dma off by default */
  380. /*
  381. * This workaround is from Promise's GPL driver.
  382. * If ATAPI DMA is used for commands not in the
  383. * following white list, say MODE_SENSE and REQUEST_SENSE,
  384. * pdc2027x might hit the irq lost problem.
  385. */
  386. switch (scsicmd[0]) {
  387. case READ_10:
  388. case WRITE_10:
  389. case READ_12:
  390. case WRITE_12:
  391. case READ_6:
  392. case WRITE_6:
  393. case 0xad: /* READ_DVD_STRUCTURE */
  394. case 0xbe: /* READ_CD */
  395. /* ATAPI DMA is ok */
  396. rc = 0;
  397. break;
  398. default:
  399. ;
  400. }
  401. return rc;
  402. }
  403. /**
  404. * pdc_read_counter - Read the ctr counter
  405. * @host: target ATA host
  406. */
  407. static long pdc_read_counter(struct ata_host *host)
  408. {
  409. void __iomem *mmio_base = host->iomap[PDC_MMIO_BAR];
  410. long counter;
  411. int retry = 1;
  412. u32 bccrl, bccrh, bccrlv, bccrhv;
  413. retry:
  414. bccrl = ioread32(mmio_base + PDC_BYTE_COUNT) & 0x7fff;
  415. bccrh = ioread32(mmio_base + PDC_BYTE_COUNT + 0x100) & 0x7fff;
  416. /* Read the counter values again for verification */
  417. bccrlv = ioread32(mmio_base + PDC_BYTE_COUNT) & 0x7fff;
  418. bccrhv = ioread32(mmio_base + PDC_BYTE_COUNT + 0x100) & 0x7fff;
  419. counter = (bccrh << 15) | bccrl;
  420. PDPRINTK("bccrh [%X] bccrl [%X]\n", bccrh, bccrl);
  421. PDPRINTK("bccrhv[%X] bccrlv[%X]\n", bccrhv, bccrlv);
  422. /*
  423. * The 30-bit decreasing counter are read by 2 pieces.
  424. * Incorrect value may be read when both bccrh and bccrl are changing.
  425. * Ex. When 7900 decrease to 78FF, wrong value 7800 might be read.
  426. */
  427. if (retry && !(bccrh == bccrhv && bccrl >= bccrlv)) {
  428. retry--;
  429. PDPRINTK("rereading counter\n");
  430. goto retry;
  431. }
  432. return counter;
  433. }
  434. /**
  435. * adjust_pll - Adjust the PLL input clock in Hz.
  436. *
  437. * @pdc_controller: controller specific information
  438. * @host: target ATA host
  439. * @pll_clock: The input of PLL in HZ
  440. */
  441. static void pdc_adjust_pll(struct ata_host *host, long pll_clock, unsigned int board_idx)
  442. {
  443. void __iomem *mmio_base = host->iomap[PDC_MMIO_BAR];
  444. u16 pll_ctl;
  445. long pll_clock_khz = pll_clock / 1000;
  446. long pout_required = board_idx? PDC_133_MHZ:PDC_100_MHZ;
  447. long ratio = pout_required / pll_clock_khz;
  448. int F, R;
  449. /* Sanity check */
  450. if (unlikely(pll_clock_khz < 5000L || pll_clock_khz > 70000L)) {
  451. printk(KERN_ERR DRV_NAME ": Invalid PLL input clock %ldkHz, give up!\n", pll_clock_khz);
  452. return;
  453. }
  454. #ifdef PDC_DEBUG
  455. PDPRINTK("pout_required is %ld\n", pout_required);
  456. /* Show the current clock value of PLL control register
  457. * (maybe already configured by the firmware)
  458. */
  459. pll_ctl = ioread16(mmio_base + PDC_PLL_CTL);
  460. PDPRINTK("pll_ctl[%X]\n", pll_ctl);
  461. #endif
  462. /*
  463. * Calculate the ratio of F, R and OD
  464. * POUT = (F + 2) / (( R + 2) * NO)
  465. */
  466. if (ratio < 8600L) { /* 8.6x */
  467. /* Using NO = 0x01, R = 0x0D */
  468. R = 0x0d;
  469. } else if (ratio < 12900L) { /* 12.9x */
  470. /* Using NO = 0x01, R = 0x08 */
  471. R = 0x08;
  472. } else if (ratio < 16100L) { /* 16.1x */
  473. /* Using NO = 0x01, R = 0x06 */
  474. R = 0x06;
  475. } else if (ratio < 64000L) { /* 64x */
  476. R = 0x00;
  477. } else {
  478. /* Invalid ratio */
  479. printk(KERN_ERR DRV_NAME ": Invalid ratio %ld, give up!\n", ratio);
  480. return;
  481. }
  482. F = (ratio * (R+2)) / 1000 - 2;
  483. if (unlikely(F < 0 || F > 127)) {
  484. /* Invalid F */
  485. printk(KERN_ERR DRV_NAME ": F[%d] invalid!\n", F);
  486. return;
  487. }
  488. PDPRINTK("F[%d] R[%d] ratio*1000[%ld]\n", F, R, ratio);
  489. pll_ctl = (R << 8) | F;
  490. PDPRINTK("Writing pll_ctl[%X]\n", pll_ctl);
  491. iowrite16(pll_ctl, mmio_base + PDC_PLL_CTL);
  492. ioread16(mmio_base + PDC_PLL_CTL); /* flush */
  493. /* Wait the PLL circuit to be stable */
  494. msleep(30);
  495. #ifdef PDC_DEBUG
  496. /*
  497. * Show the current clock value of PLL control register
  498. * (maybe configured by the firmware)
  499. */
  500. pll_ctl = ioread16(mmio_base + PDC_PLL_CTL);
  501. PDPRINTK("pll_ctl[%X]\n", pll_ctl);
  502. #endif
  503. return;
  504. }
  505. /**
  506. * detect_pll_input_clock - Detect the PLL input clock in Hz.
  507. * @host: target ATA host
  508. * Ex. 16949000 on 33MHz PCI bus for pdc20275.
  509. * Half of the PCI clock.
  510. */
  511. static long pdc_detect_pll_input_clock(struct ata_host *host)
  512. {
  513. void __iomem *mmio_base = host->iomap[PDC_MMIO_BAR];
  514. u32 scr;
  515. long start_count, end_count;
  516. ktime_t start_time, end_time;
  517. long pll_clock, usec_elapsed;
  518. /* Start the test mode */
  519. scr = ioread32(mmio_base + PDC_SYS_CTL);
  520. PDPRINTK("scr[%X]\n", scr);
  521. iowrite32(scr | (0x01 << 14), mmio_base + PDC_SYS_CTL);
  522. ioread32(mmio_base + PDC_SYS_CTL); /* flush */
  523. /* Read current counter value */
  524. start_count = pdc_read_counter(host);
  525. start_time = ktime_get();
  526. /* Let the counter run for 100 ms. */
  527. msleep(100);
  528. /* Read the counter values again */
  529. end_count = pdc_read_counter(host);
  530. end_time = ktime_get();
  531. /* Stop the test mode */
  532. scr = ioread32(mmio_base + PDC_SYS_CTL);
  533. PDPRINTK("scr[%X]\n", scr);
  534. iowrite32(scr & ~(0x01 << 14), mmio_base + PDC_SYS_CTL);
  535. ioread32(mmio_base + PDC_SYS_CTL); /* flush */
  536. /* calculate the input clock in Hz */
  537. usec_elapsed = (long) ktime_us_delta(end_time, start_time);
  538. pll_clock = ((start_count - end_count) & 0x3fffffff) / 100 *
  539. (100000000 / usec_elapsed);
  540. PDPRINTK("start[%ld] end[%ld] \n", start_count, end_count);
  541. PDPRINTK("PLL input clock[%ld]Hz\n", pll_clock);
  542. return pll_clock;
  543. }
  544. /**
  545. * pdc_hardware_init - Initialize the hardware.
  546. * @host: target ATA host
  547. * @board_idx: board identifier
  548. */
  549. static void pdc_hardware_init(struct ata_host *host, unsigned int board_idx)
  550. {
  551. long pll_clock;
  552. /*
  553. * Detect PLL input clock rate.
  554. * On some system, where PCI bus is running at non-standard clock rate.
  555. * Ex. 25MHz or 40MHz, we have to adjust the cycle_time.
  556. * The pdc20275 controller employs PLL circuit to help correct timing registers setting.
  557. */
  558. pll_clock = pdc_detect_pll_input_clock(host);
  559. dev_info(host->dev, "PLL input clock %ld kHz\n", pll_clock/1000);
  560. /* Adjust PLL control register */
  561. pdc_adjust_pll(host, pll_clock, board_idx);
  562. }
  563. /**
  564. * pdc_ata_setup_port - setup the mmio address
  565. * @port: ata ioports to setup
  566. * @base: base address
  567. */
  568. static void pdc_ata_setup_port(struct ata_ioports *port, void __iomem *base)
  569. {
  570. port->cmd_addr =
  571. port->data_addr = base;
  572. port->feature_addr =
  573. port->error_addr = base + 0x05;
  574. port->nsect_addr = base + 0x0a;
  575. port->lbal_addr = base + 0x0f;
  576. port->lbam_addr = base + 0x10;
  577. port->lbah_addr = base + 0x15;
  578. port->device_addr = base + 0x1a;
  579. port->command_addr =
  580. port->status_addr = base + 0x1f;
  581. port->altstatus_addr =
  582. port->ctl_addr = base + 0x81a;
  583. }
  584. /**
  585. * pdc2027x_init_one - PCI probe function
  586. * Called when an instance of PCI adapter is inserted.
  587. * This function checks whether the hardware is supported,
  588. * initialize hardware and register an instance of ata_host to
  589. * libata. (implements struct pci_driver.probe() )
  590. *
  591. * @pdev: instance of pci_dev found
  592. * @ent: matching entry in the id_tbl[]
  593. */
  594. static int pdc2027x_init_one(struct pci_dev *pdev,
  595. const struct pci_device_id *ent)
  596. {
  597. static const unsigned long cmd_offset[] = { 0x17c0, 0x15c0 };
  598. static const unsigned long bmdma_offset[] = { 0x1000, 0x1008 };
  599. unsigned int board_idx = (unsigned int) ent->driver_data;
  600. const struct ata_port_info *ppi[] =
  601. { &pdc2027x_port_info[board_idx], NULL };
  602. struct ata_host *host;
  603. void __iomem *mmio_base;
  604. int i, rc;
  605. ata_print_version_once(&pdev->dev, DRV_VERSION);
  606. /* alloc host */
  607. host = ata_host_alloc_pinfo(&pdev->dev, ppi, 2);
  608. if (!host)
  609. return -ENOMEM;
  610. /* acquire resources and fill host */
  611. rc = pcim_enable_device(pdev);
  612. if (rc)
  613. return rc;
  614. rc = pcim_iomap_regions(pdev, 1 << PDC_MMIO_BAR, DRV_NAME);
  615. if (rc)
  616. return rc;
  617. host->iomap = pcim_iomap_table(pdev);
  618. rc = dma_set_mask_and_coherent(&pdev->dev, ATA_DMA_MASK);
  619. if (rc)
  620. return rc;
  621. mmio_base = host->iomap[PDC_MMIO_BAR];
  622. for (i = 0; i < 2; i++) {
  623. struct ata_port *ap = host->ports[i];
  624. pdc_ata_setup_port(&ap->ioaddr, mmio_base + cmd_offset[i]);
  625. ap->ioaddr.bmdma_addr = mmio_base + bmdma_offset[i];
  626. ata_port_pbar_desc(ap, PDC_MMIO_BAR, -1, "mmio");
  627. ata_port_pbar_desc(ap, PDC_MMIO_BAR, cmd_offset[i], "cmd");
  628. }
  629. //pci_enable_intx(pdev);
  630. /* initialize adapter */
  631. pdc_hardware_init(host, board_idx);
  632. pci_set_master(pdev);
  633. return ata_host_activate(host, pdev->irq, ata_bmdma_interrupt,
  634. IRQF_SHARED, &pdc2027x_sht);
  635. }
  636. #ifdef CONFIG_PM_SLEEP
  637. static int pdc2027x_reinit_one(struct pci_dev *pdev)
  638. {
  639. struct ata_host *host = pci_get_drvdata(pdev);
  640. unsigned int board_idx;
  641. int rc;
  642. rc = ata_pci_device_do_resume(pdev);
  643. if (rc)
  644. return rc;
  645. if (pdev->device == PCI_DEVICE_ID_PROMISE_20268 ||
  646. pdev->device == PCI_DEVICE_ID_PROMISE_20270)
  647. board_idx = PDC_UDMA_100;
  648. else
  649. board_idx = PDC_UDMA_133;
  650. pdc_hardware_init(host, board_idx);
  651. ata_host_resume(host);
  652. return 0;
  653. }
  654. #endif
  655. module_pci_driver(pdc2027x_pci_driver);