pata_octeon_cf.c 27 KB

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  1. /*
  2. * Driver for the Octeon bootbus compact flash.
  3. *
  4. * This file is subject to the terms and conditions of the GNU General Public
  5. * License. See the file "COPYING" in the main directory of this archive
  6. * for more details.
  7. *
  8. * Copyright (C) 2005 - 2012 Cavium Inc.
  9. * Copyright (C) 2008 Wind River Systems
  10. */
  11. #include <linux/kernel.h>
  12. #include <linux/module.h>
  13. #include <linux/libata.h>
  14. #include <linux/hrtimer.h>
  15. #include <linux/slab.h>
  16. #include <linux/irq.h>
  17. #include <linux/of.h>
  18. #include <linux/of_platform.h>
  19. #include <linux/platform_device.h>
  20. #include <scsi/scsi_host.h>
  21. #include <asm/byteorder.h>
  22. #include <asm/octeon/octeon.h>
  23. /*
  24. * The Octeon bootbus compact flash interface is connected in at least
  25. * 3 different configurations on various evaluation boards:
  26. *
  27. * -- 8 bits no irq, no DMA
  28. * -- 16 bits no irq, no DMA
  29. * -- 16 bits True IDE mode with DMA, but no irq.
  30. *
  31. * In the last case the DMA engine can generate an interrupt when the
  32. * transfer is complete. For the first two cases only PIO is supported.
  33. *
  34. */
  35. #define DRV_NAME "pata_octeon_cf"
  36. #define DRV_VERSION "2.2"
  37. /* Poll interval in nS. */
  38. #define OCTEON_CF_BUSY_POLL_INTERVAL 500000
  39. #define DMA_CFG 0
  40. #define DMA_TIM 0x20
  41. #define DMA_INT 0x38
  42. #define DMA_INT_EN 0x50
  43. struct octeon_cf_port {
  44. struct hrtimer delayed_finish;
  45. struct ata_port *ap;
  46. int dma_finished;
  47. void *c0;
  48. unsigned int cs0;
  49. unsigned int cs1;
  50. bool is_true_ide;
  51. u64 dma_base;
  52. };
  53. static struct scsi_host_template octeon_cf_sht = {
  54. ATA_PIO_SHT(DRV_NAME),
  55. };
  56. static int enable_dma;
  57. module_param(enable_dma, int, 0444);
  58. MODULE_PARM_DESC(enable_dma,
  59. "Enable use of DMA on interfaces that support it (0=no dma [default], 1=use dma)");
  60. /**
  61. * Convert nanosecond based time to setting used in the
  62. * boot bus timing register, based on timing multiple
  63. */
  64. static unsigned int ns_to_tim_reg(unsigned int tim_mult, unsigned int nsecs)
  65. {
  66. unsigned int val;
  67. /*
  68. * Compute # of eclock periods to get desired duration in
  69. * nanoseconds.
  70. */
  71. val = DIV_ROUND_UP(nsecs * (octeon_get_io_clock_rate() / 1000000),
  72. 1000 * tim_mult);
  73. return val;
  74. }
  75. static void octeon_cf_set_boot_reg_cfg(int cs, unsigned int multiplier)
  76. {
  77. union cvmx_mio_boot_reg_cfgx reg_cfg;
  78. unsigned int tim_mult;
  79. switch (multiplier) {
  80. case 8:
  81. tim_mult = 3;
  82. break;
  83. case 4:
  84. tim_mult = 0;
  85. break;
  86. case 2:
  87. tim_mult = 2;
  88. break;
  89. default:
  90. tim_mult = 1;
  91. break;
  92. }
  93. reg_cfg.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(cs));
  94. reg_cfg.s.dmack = 0; /* Don't assert DMACK on access */
  95. reg_cfg.s.tim_mult = tim_mult; /* Timing mutiplier */
  96. reg_cfg.s.rd_dly = 0; /* Sample on falling edge of BOOT_OE */
  97. reg_cfg.s.sam = 0; /* Don't combine write and output enable */
  98. reg_cfg.s.we_ext = 0; /* No write enable extension */
  99. reg_cfg.s.oe_ext = 0; /* No read enable extension */
  100. reg_cfg.s.en = 1; /* Enable this region */
  101. reg_cfg.s.orbit = 0; /* Don't combine with previous region */
  102. reg_cfg.s.ale = 0; /* Don't do address multiplexing */
  103. cvmx_write_csr(CVMX_MIO_BOOT_REG_CFGX(cs), reg_cfg.u64);
  104. }
  105. /**
  106. * Called after libata determines the needed PIO mode. This
  107. * function programs the Octeon bootbus regions to support the
  108. * timing requirements of the PIO mode.
  109. *
  110. * @ap: ATA port information
  111. * @dev: ATA device
  112. */
  113. static void octeon_cf_set_piomode(struct ata_port *ap, struct ata_device *dev)
  114. {
  115. struct octeon_cf_port *cf_port = ap->private_data;
  116. union cvmx_mio_boot_reg_timx reg_tim;
  117. int T;
  118. struct ata_timing timing;
  119. unsigned int div;
  120. int use_iordy;
  121. int trh;
  122. int pause;
  123. /* These names are timing parameters from the ATA spec */
  124. int t2;
  125. /*
  126. * A divisor value of four will overflow the timing fields at
  127. * clock rates greater than 800MHz
  128. */
  129. if (octeon_get_io_clock_rate() <= 800000000)
  130. div = 4;
  131. else
  132. div = 8;
  133. T = (int)((1000000000000LL * div) / octeon_get_io_clock_rate());
  134. BUG_ON(ata_timing_compute(dev, dev->pio_mode, &timing, T, T));
  135. t2 = timing.active;
  136. if (t2)
  137. t2--;
  138. trh = ns_to_tim_reg(div, 20);
  139. if (trh)
  140. trh--;
  141. pause = (int)timing.cycle - (int)timing.active -
  142. (int)timing.setup - trh;
  143. if (pause < 0)
  144. pause = 0;
  145. if (pause)
  146. pause--;
  147. octeon_cf_set_boot_reg_cfg(cf_port->cs0, div);
  148. if (cf_port->is_true_ide)
  149. /* True IDE mode, program both chip selects. */
  150. octeon_cf_set_boot_reg_cfg(cf_port->cs1, div);
  151. use_iordy = ata_pio_need_iordy(dev);
  152. reg_tim.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_TIMX(cf_port->cs0));
  153. /* Disable page mode */
  154. reg_tim.s.pagem = 0;
  155. /* Enable dynamic timing */
  156. reg_tim.s.waitm = use_iordy;
  157. /* Pages are disabled */
  158. reg_tim.s.pages = 0;
  159. /* We don't use multiplexed address mode */
  160. reg_tim.s.ale = 0;
  161. /* Not used */
  162. reg_tim.s.page = 0;
  163. /* Time after IORDY to coninue to assert the data */
  164. reg_tim.s.wait = 0;
  165. /* Time to wait to complete the cycle. */
  166. reg_tim.s.pause = pause;
  167. /* How long to hold after a write to de-assert CE. */
  168. reg_tim.s.wr_hld = trh;
  169. /* How long to wait after a read to de-assert CE. */
  170. reg_tim.s.rd_hld = trh;
  171. /* How long write enable is asserted */
  172. reg_tim.s.we = t2;
  173. /* How long read enable is asserted */
  174. reg_tim.s.oe = t2;
  175. /* Time after CE that read/write starts */
  176. reg_tim.s.ce = ns_to_tim_reg(div, 5);
  177. /* Time before CE that address is valid */
  178. reg_tim.s.adr = 0;
  179. /* Program the bootbus region timing for the data port chip select. */
  180. cvmx_write_csr(CVMX_MIO_BOOT_REG_TIMX(cf_port->cs0), reg_tim.u64);
  181. if (cf_port->is_true_ide)
  182. /* True IDE mode, program both chip selects. */
  183. cvmx_write_csr(CVMX_MIO_BOOT_REG_TIMX(cf_port->cs1),
  184. reg_tim.u64);
  185. }
  186. static void octeon_cf_set_dmamode(struct ata_port *ap, struct ata_device *dev)
  187. {
  188. struct octeon_cf_port *cf_port = ap->private_data;
  189. union cvmx_mio_boot_pin_defs pin_defs;
  190. union cvmx_mio_boot_dma_timx dma_tim;
  191. unsigned int oe_a;
  192. unsigned int oe_n;
  193. unsigned int dma_ackh;
  194. unsigned int dma_arq;
  195. unsigned int pause;
  196. unsigned int T0, Tkr, Td;
  197. unsigned int tim_mult;
  198. int c;
  199. const struct ata_timing *timing;
  200. timing = ata_timing_find_mode(dev->dma_mode);
  201. T0 = timing->cycle;
  202. Td = timing->active;
  203. Tkr = timing->recover;
  204. dma_ackh = timing->dmack_hold;
  205. dma_tim.u64 = 0;
  206. /* dma_tim.s.tim_mult = 0 --> 4x */
  207. tim_mult = 4;
  208. /* not spec'ed, value in eclocks, not affected by tim_mult */
  209. dma_arq = 8;
  210. pause = 25 - dma_arq * 1000 /
  211. (octeon_get_io_clock_rate() / 1000000); /* Tz */
  212. oe_a = Td;
  213. /* Tkr from cf spec, lengthened to meet T0 */
  214. oe_n = max(T0 - oe_a, Tkr);
  215. pin_defs.u64 = cvmx_read_csr(CVMX_MIO_BOOT_PIN_DEFS);
  216. /* DMA channel number. */
  217. c = (cf_port->dma_base & 8) >> 3;
  218. /* Invert the polarity if the default is 0*/
  219. dma_tim.s.dmack_pi = (pin_defs.u64 & (1ull << (11 + c))) ? 0 : 1;
  220. dma_tim.s.oe_n = ns_to_tim_reg(tim_mult, oe_n);
  221. dma_tim.s.oe_a = ns_to_tim_reg(tim_mult, oe_a);
  222. /*
  223. * This is tI, C.F. spec. says 0, but Sony CF card requires
  224. * more, we use 20 nS.
  225. */
  226. dma_tim.s.dmack_s = ns_to_tim_reg(tim_mult, 20);
  227. dma_tim.s.dmack_h = ns_to_tim_reg(tim_mult, dma_ackh);
  228. dma_tim.s.dmarq = dma_arq;
  229. dma_tim.s.pause = ns_to_tim_reg(tim_mult, pause);
  230. dma_tim.s.rd_dly = 0; /* Sample right on edge */
  231. /* writes only */
  232. dma_tim.s.we_n = ns_to_tim_reg(tim_mult, oe_n);
  233. dma_tim.s.we_a = ns_to_tim_reg(tim_mult, oe_a);
  234. pr_debug("ns to ticks (mult %d) of %d is: %d\n", tim_mult, 60,
  235. ns_to_tim_reg(tim_mult, 60));
  236. pr_debug("oe_n: %d, oe_a: %d, dmack_s: %d, dmack_h: %d, dmarq: %d, pause: %d\n",
  237. dma_tim.s.oe_n, dma_tim.s.oe_a, dma_tim.s.dmack_s,
  238. dma_tim.s.dmack_h, dma_tim.s.dmarq, dma_tim.s.pause);
  239. cvmx_write_csr(cf_port->dma_base + DMA_TIM, dma_tim.u64);
  240. }
  241. /**
  242. * Handle an 8 bit I/O request.
  243. *
  244. * @qc: Queued command
  245. * @buffer: Data buffer
  246. * @buflen: Length of the buffer.
  247. * @rw: True to write.
  248. */
  249. static unsigned int octeon_cf_data_xfer8(struct ata_queued_cmd *qc,
  250. unsigned char *buffer,
  251. unsigned int buflen,
  252. int rw)
  253. {
  254. struct ata_port *ap = qc->dev->link->ap;
  255. void __iomem *data_addr = ap->ioaddr.data_addr;
  256. unsigned long words;
  257. int count;
  258. words = buflen;
  259. if (rw) {
  260. count = 16;
  261. while (words--) {
  262. iowrite8(*buffer, data_addr);
  263. buffer++;
  264. /*
  265. * Every 16 writes do a read so the bootbus
  266. * FIFO doesn't fill up.
  267. */
  268. if (--count == 0) {
  269. ioread8(ap->ioaddr.altstatus_addr);
  270. count = 16;
  271. }
  272. }
  273. } else {
  274. ioread8_rep(data_addr, buffer, words);
  275. }
  276. return buflen;
  277. }
  278. /**
  279. * Handle a 16 bit I/O request.
  280. *
  281. * @qc: Queued command
  282. * @buffer: Data buffer
  283. * @buflen: Length of the buffer.
  284. * @rw: True to write.
  285. */
  286. static unsigned int octeon_cf_data_xfer16(struct ata_queued_cmd *qc,
  287. unsigned char *buffer,
  288. unsigned int buflen,
  289. int rw)
  290. {
  291. struct ata_port *ap = qc->dev->link->ap;
  292. void __iomem *data_addr = ap->ioaddr.data_addr;
  293. unsigned long words;
  294. int count;
  295. words = buflen / 2;
  296. if (rw) {
  297. count = 16;
  298. while (words--) {
  299. iowrite16(*(uint16_t *)buffer, data_addr);
  300. buffer += sizeof(uint16_t);
  301. /*
  302. * Every 16 writes do a read so the bootbus
  303. * FIFO doesn't fill up.
  304. */
  305. if (--count == 0) {
  306. ioread8(ap->ioaddr.altstatus_addr);
  307. count = 16;
  308. }
  309. }
  310. } else {
  311. while (words--) {
  312. *(uint16_t *)buffer = ioread16(data_addr);
  313. buffer += sizeof(uint16_t);
  314. }
  315. }
  316. /* Transfer trailing 1 byte, if any. */
  317. if (unlikely(buflen & 0x01)) {
  318. __le16 align_buf[1] = { 0 };
  319. if (rw == READ) {
  320. align_buf[0] = cpu_to_le16(ioread16(data_addr));
  321. memcpy(buffer, align_buf, 1);
  322. } else {
  323. memcpy(align_buf, buffer, 1);
  324. iowrite16(le16_to_cpu(align_buf[0]), data_addr);
  325. }
  326. words++;
  327. }
  328. return buflen;
  329. }
  330. /**
  331. * Read the taskfile for 16bit non-True IDE only.
  332. */
  333. static void octeon_cf_tf_read16(struct ata_port *ap, struct ata_taskfile *tf)
  334. {
  335. u16 blob;
  336. /* The base of the registers is at ioaddr.data_addr. */
  337. void __iomem *base = ap->ioaddr.data_addr;
  338. blob = __raw_readw(base + 0xc);
  339. tf->feature = blob >> 8;
  340. blob = __raw_readw(base + 2);
  341. tf->nsect = blob & 0xff;
  342. tf->lbal = blob >> 8;
  343. blob = __raw_readw(base + 4);
  344. tf->lbam = blob & 0xff;
  345. tf->lbah = blob >> 8;
  346. blob = __raw_readw(base + 6);
  347. tf->device = blob & 0xff;
  348. tf->command = blob >> 8;
  349. if (tf->flags & ATA_TFLAG_LBA48) {
  350. if (likely(ap->ioaddr.ctl_addr)) {
  351. iowrite8(tf->ctl | ATA_HOB, ap->ioaddr.ctl_addr);
  352. blob = __raw_readw(base + 0xc);
  353. tf->hob_feature = blob >> 8;
  354. blob = __raw_readw(base + 2);
  355. tf->hob_nsect = blob & 0xff;
  356. tf->hob_lbal = blob >> 8;
  357. blob = __raw_readw(base + 4);
  358. tf->hob_lbam = blob & 0xff;
  359. tf->hob_lbah = blob >> 8;
  360. iowrite8(tf->ctl, ap->ioaddr.ctl_addr);
  361. ap->last_ctl = tf->ctl;
  362. } else {
  363. WARN_ON(1);
  364. }
  365. }
  366. }
  367. static u8 octeon_cf_check_status16(struct ata_port *ap)
  368. {
  369. u16 blob;
  370. void __iomem *base = ap->ioaddr.data_addr;
  371. blob = __raw_readw(base + 6);
  372. return blob >> 8;
  373. }
  374. static int octeon_cf_softreset16(struct ata_link *link, unsigned int *classes,
  375. unsigned long deadline)
  376. {
  377. struct ata_port *ap = link->ap;
  378. void __iomem *base = ap->ioaddr.data_addr;
  379. int rc;
  380. u8 err;
  381. DPRINTK("about to softreset\n");
  382. __raw_writew(ap->ctl, base + 0xe);
  383. udelay(20);
  384. __raw_writew(ap->ctl | ATA_SRST, base + 0xe);
  385. udelay(20);
  386. __raw_writew(ap->ctl, base + 0xe);
  387. rc = ata_sff_wait_after_reset(link, 1, deadline);
  388. if (rc) {
  389. ata_link_err(link, "SRST failed (errno=%d)\n", rc);
  390. return rc;
  391. }
  392. /* determine by signature whether we have ATA or ATAPI devices */
  393. classes[0] = ata_sff_dev_classify(&link->device[0], 1, &err);
  394. DPRINTK("EXIT, classes[0]=%u [1]=%u\n", classes[0], classes[1]);
  395. return 0;
  396. }
  397. /**
  398. * Load the taskfile for 16bit non-True IDE only. The device_addr is
  399. * not loaded, we do this as part of octeon_cf_exec_command16.
  400. */
  401. static void octeon_cf_tf_load16(struct ata_port *ap,
  402. const struct ata_taskfile *tf)
  403. {
  404. unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
  405. /* The base of the registers is at ioaddr.data_addr. */
  406. void __iomem *base = ap->ioaddr.data_addr;
  407. if (tf->ctl != ap->last_ctl) {
  408. iowrite8(tf->ctl, ap->ioaddr.ctl_addr);
  409. ap->last_ctl = tf->ctl;
  410. ata_wait_idle(ap);
  411. }
  412. if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
  413. __raw_writew(tf->hob_feature << 8, base + 0xc);
  414. __raw_writew(tf->hob_nsect | tf->hob_lbal << 8, base + 2);
  415. __raw_writew(tf->hob_lbam | tf->hob_lbah << 8, base + 4);
  416. VPRINTK("hob: feat 0x%X nsect 0x%X, lba 0x%X 0x%X 0x%X\n",
  417. tf->hob_feature,
  418. tf->hob_nsect,
  419. tf->hob_lbal,
  420. tf->hob_lbam,
  421. tf->hob_lbah);
  422. }
  423. if (is_addr) {
  424. __raw_writew(tf->feature << 8, base + 0xc);
  425. __raw_writew(tf->nsect | tf->lbal << 8, base + 2);
  426. __raw_writew(tf->lbam | tf->lbah << 8, base + 4);
  427. VPRINTK("feat 0x%X nsect 0x%X, lba 0x%X 0x%X 0x%X\n",
  428. tf->feature,
  429. tf->nsect,
  430. tf->lbal,
  431. tf->lbam,
  432. tf->lbah);
  433. }
  434. ata_wait_idle(ap);
  435. }
  436. static void octeon_cf_dev_select(struct ata_port *ap, unsigned int device)
  437. {
  438. /* There is only one device, do nothing. */
  439. return;
  440. }
  441. /*
  442. * Issue ATA command to host controller. The device_addr is also sent
  443. * as it must be written in a combined write with the command.
  444. */
  445. static void octeon_cf_exec_command16(struct ata_port *ap,
  446. const struct ata_taskfile *tf)
  447. {
  448. /* The base of the registers is at ioaddr.data_addr. */
  449. void __iomem *base = ap->ioaddr.data_addr;
  450. u16 blob;
  451. if (tf->flags & ATA_TFLAG_DEVICE) {
  452. VPRINTK("device 0x%X\n", tf->device);
  453. blob = tf->device;
  454. } else {
  455. blob = 0;
  456. }
  457. DPRINTK("ata%u: cmd 0x%X\n", ap->print_id, tf->command);
  458. blob |= (tf->command << 8);
  459. __raw_writew(blob, base + 6);
  460. ata_wait_idle(ap);
  461. }
  462. static void octeon_cf_ata_port_noaction(struct ata_port *ap)
  463. {
  464. }
  465. static void octeon_cf_dma_setup(struct ata_queued_cmd *qc)
  466. {
  467. struct ata_port *ap = qc->ap;
  468. struct octeon_cf_port *cf_port;
  469. cf_port = ap->private_data;
  470. DPRINTK("ENTER\n");
  471. /* issue r/w command */
  472. qc->cursg = qc->sg;
  473. cf_port->dma_finished = 0;
  474. ap->ops->sff_exec_command(ap, &qc->tf);
  475. DPRINTK("EXIT\n");
  476. }
  477. /**
  478. * Start a DMA transfer that was already setup
  479. *
  480. * @qc: Information about the DMA
  481. */
  482. static void octeon_cf_dma_start(struct ata_queued_cmd *qc)
  483. {
  484. struct octeon_cf_port *cf_port = qc->ap->private_data;
  485. union cvmx_mio_boot_dma_cfgx mio_boot_dma_cfg;
  486. union cvmx_mio_boot_dma_intx mio_boot_dma_int;
  487. struct scatterlist *sg;
  488. VPRINTK("%d scatterlists\n", qc->n_elem);
  489. /* Get the scatter list entry we need to DMA into */
  490. sg = qc->cursg;
  491. BUG_ON(!sg);
  492. /*
  493. * Clear the DMA complete status.
  494. */
  495. mio_boot_dma_int.u64 = 0;
  496. mio_boot_dma_int.s.done = 1;
  497. cvmx_write_csr(cf_port->dma_base + DMA_INT, mio_boot_dma_int.u64);
  498. /* Enable the interrupt. */
  499. cvmx_write_csr(cf_port->dma_base + DMA_INT_EN, mio_boot_dma_int.u64);
  500. /* Set the direction of the DMA */
  501. mio_boot_dma_cfg.u64 = 0;
  502. #ifdef __LITTLE_ENDIAN
  503. mio_boot_dma_cfg.s.endian = 1;
  504. #endif
  505. mio_boot_dma_cfg.s.en = 1;
  506. mio_boot_dma_cfg.s.rw = ((qc->tf.flags & ATA_TFLAG_WRITE) != 0);
  507. /*
  508. * Don't stop the DMA if the device deasserts DMARQ. Many
  509. * compact flashes deassert DMARQ for a short time between
  510. * sectors. Instead of stopping and restarting the DMA, we'll
  511. * let the hardware do it. If the DMA is really stopped early
  512. * due to an error condition, a later timeout will force us to
  513. * stop.
  514. */
  515. mio_boot_dma_cfg.s.clr = 0;
  516. /* Size is specified in 16bit words and minus one notation */
  517. mio_boot_dma_cfg.s.size = sg_dma_len(sg) / 2 - 1;
  518. /* We need to swap the high and low bytes of every 16 bits */
  519. mio_boot_dma_cfg.s.swap8 = 1;
  520. mio_boot_dma_cfg.s.adr = sg_dma_address(sg);
  521. VPRINTK("%s %d bytes address=%p\n",
  522. (mio_boot_dma_cfg.s.rw) ? "write" : "read", sg->length,
  523. (void *)(unsigned long)mio_boot_dma_cfg.s.adr);
  524. cvmx_write_csr(cf_port->dma_base + DMA_CFG, mio_boot_dma_cfg.u64);
  525. }
  526. /**
  527. *
  528. * LOCKING:
  529. * spin_lock_irqsave(host lock)
  530. *
  531. */
  532. static unsigned int octeon_cf_dma_finished(struct ata_port *ap,
  533. struct ata_queued_cmd *qc)
  534. {
  535. struct ata_eh_info *ehi = &ap->link.eh_info;
  536. struct octeon_cf_port *cf_port = ap->private_data;
  537. union cvmx_mio_boot_dma_cfgx dma_cfg;
  538. union cvmx_mio_boot_dma_intx dma_int;
  539. u8 status;
  540. VPRINTK("ata%u: protocol %d task_state %d\n",
  541. ap->print_id, qc->tf.protocol, ap->hsm_task_state);
  542. if (ap->hsm_task_state != HSM_ST_LAST)
  543. return 0;
  544. dma_cfg.u64 = cvmx_read_csr(cf_port->dma_base + DMA_CFG);
  545. if (dma_cfg.s.size != 0xfffff) {
  546. /* Error, the transfer was not complete. */
  547. qc->err_mask |= AC_ERR_HOST_BUS;
  548. ap->hsm_task_state = HSM_ST_ERR;
  549. }
  550. /* Stop and clear the dma engine. */
  551. dma_cfg.u64 = 0;
  552. dma_cfg.s.size = -1;
  553. cvmx_write_csr(cf_port->dma_base + DMA_CFG, dma_cfg.u64);
  554. /* Disable the interrupt. */
  555. dma_int.u64 = 0;
  556. cvmx_write_csr(cf_port->dma_base + DMA_INT_EN, dma_int.u64);
  557. /* Clear the DMA complete status */
  558. dma_int.s.done = 1;
  559. cvmx_write_csr(cf_port->dma_base + DMA_INT, dma_int.u64);
  560. status = ap->ops->sff_check_status(ap);
  561. ata_sff_hsm_move(ap, qc, status, 0);
  562. if (unlikely(qc->err_mask) && (qc->tf.protocol == ATA_PROT_DMA))
  563. ata_ehi_push_desc(ehi, "DMA stat 0x%x", status);
  564. return 1;
  565. }
  566. /*
  567. * Check if any queued commands have more DMAs, if so start the next
  568. * transfer, else do end of transfer handling.
  569. */
  570. static irqreturn_t octeon_cf_interrupt(int irq, void *dev_instance)
  571. {
  572. struct ata_host *host = dev_instance;
  573. struct octeon_cf_port *cf_port;
  574. int i;
  575. unsigned int handled = 0;
  576. unsigned long flags;
  577. spin_lock_irqsave(&host->lock, flags);
  578. DPRINTK("ENTER\n");
  579. for (i = 0; i < host->n_ports; i++) {
  580. u8 status;
  581. struct ata_port *ap;
  582. struct ata_queued_cmd *qc;
  583. union cvmx_mio_boot_dma_intx dma_int;
  584. union cvmx_mio_boot_dma_cfgx dma_cfg;
  585. ap = host->ports[i];
  586. cf_port = ap->private_data;
  587. dma_int.u64 = cvmx_read_csr(cf_port->dma_base + DMA_INT);
  588. dma_cfg.u64 = cvmx_read_csr(cf_port->dma_base + DMA_CFG);
  589. qc = ata_qc_from_tag(ap, ap->link.active_tag);
  590. if (!qc || (qc->tf.flags & ATA_TFLAG_POLLING))
  591. continue;
  592. if (dma_int.s.done && !dma_cfg.s.en) {
  593. if (!sg_is_last(qc->cursg)) {
  594. qc->cursg = sg_next(qc->cursg);
  595. handled = 1;
  596. octeon_cf_dma_start(qc);
  597. continue;
  598. } else {
  599. cf_port->dma_finished = 1;
  600. }
  601. }
  602. if (!cf_port->dma_finished)
  603. continue;
  604. status = ioread8(ap->ioaddr.altstatus_addr);
  605. if (status & (ATA_BUSY | ATA_DRQ)) {
  606. /*
  607. * We are busy, try to handle it later. This
  608. * is the DMA finished interrupt, and it could
  609. * take a little while for the card to be
  610. * ready for more commands.
  611. */
  612. /* Clear DMA irq. */
  613. dma_int.u64 = 0;
  614. dma_int.s.done = 1;
  615. cvmx_write_csr(cf_port->dma_base + DMA_INT,
  616. dma_int.u64);
  617. hrtimer_start_range_ns(&cf_port->delayed_finish,
  618. ns_to_ktime(OCTEON_CF_BUSY_POLL_INTERVAL),
  619. OCTEON_CF_BUSY_POLL_INTERVAL / 5,
  620. HRTIMER_MODE_REL);
  621. handled = 1;
  622. } else {
  623. handled |= octeon_cf_dma_finished(ap, qc);
  624. }
  625. }
  626. spin_unlock_irqrestore(&host->lock, flags);
  627. DPRINTK("EXIT\n");
  628. return IRQ_RETVAL(handled);
  629. }
  630. static enum hrtimer_restart octeon_cf_delayed_finish(struct hrtimer *hrt)
  631. {
  632. struct octeon_cf_port *cf_port = container_of(hrt,
  633. struct octeon_cf_port,
  634. delayed_finish);
  635. struct ata_port *ap = cf_port->ap;
  636. struct ata_host *host = ap->host;
  637. struct ata_queued_cmd *qc;
  638. unsigned long flags;
  639. u8 status;
  640. enum hrtimer_restart rv = HRTIMER_NORESTART;
  641. spin_lock_irqsave(&host->lock, flags);
  642. /*
  643. * If the port is not waiting for completion, it must have
  644. * handled it previously. The hsm_task_state is
  645. * protected by host->lock.
  646. */
  647. if (ap->hsm_task_state != HSM_ST_LAST || !cf_port->dma_finished)
  648. goto out;
  649. status = ioread8(ap->ioaddr.altstatus_addr);
  650. if (status & (ATA_BUSY | ATA_DRQ)) {
  651. /* Still busy, try again. */
  652. hrtimer_forward_now(hrt,
  653. ns_to_ktime(OCTEON_CF_BUSY_POLL_INTERVAL));
  654. rv = HRTIMER_RESTART;
  655. goto out;
  656. }
  657. qc = ata_qc_from_tag(ap, ap->link.active_tag);
  658. if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING)))
  659. octeon_cf_dma_finished(ap, qc);
  660. out:
  661. spin_unlock_irqrestore(&host->lock, flags);
  662. return rv;
  663. }
  664. static void octeon_cf_dev_config(struct ata_device *dev)
  665. {
  666. /*
  667. * A maximum of 2^20 - 1 16 bit transfers are possible with
  668. * the bootbus DMA. So we need to throttle max_sectors to
  669. * (2^12 - 1 == 4095) to assure that this can never happen.
  670. */
  671. dev->max_sectors = min(dev->max_sectors, 4095U);
  672. }
  673. /*
  674. * We don't do ATAPI DMA so return 0.
  675. */
  676. static int octeon_cf_check_atapi_dma(struct ata_queued_cmd *qc)
  677. {
  678. return 0;
  679. }
  680. static unsigned int octeon_cf_qc_issue(struct ata_queued_cmd *qc)
  681. {
  682. struct ata_port *ap = qc->ap;
  683. switch (qc->tf.protocol) {
  684. case ATA_PROT_DMA:
  685. WARN_ON(qc->tf.flags & ATA_TFLAG_POLLING);
  686. ap->ops->sff_tf_load(ap, &qc->tf); /* load tf registers */
  687. octeon_cf_dma_setup(qc); /* set up dma */
  688. octeon_cf_dma_start(qc); /* initiate dma */
  689. ap->hsm_task_state = HSM_ST_LAST;
  690. break;
  691. case ATAPI_PROT_DMA:
  692. dev_err(ap->dev, "Error, ATAPI not supported\n");
  693. BUG();
  694. default:
  695. return ata_sff_qc_issue(qc);
  696. }
  697. return 0;
  698. }
  699. static struct ata_port_operations octeon_cf_ops = {
  700. .inherits = &ata_sff_port_ops,
  701. .check_atapi_dma = octeon_cf_check_atapi_dma,
  702. .qc_prep = ata_noop_qc_prep,
  703. .qc_issue = octeon_cf_qc_issue,
  704. .sff_dev_select = octeon_cf_dev_select,
  705. .sff_irq_on = octeon_cf_ata_port_noaction,
  706. .sff_irq_clear = octeon_cf_ata_port_noaction,
  707. .cable_detect = ata_cable_40wire,
  708. .set_piomode = octeon_cf_set_piomode,
  709. .set_dmamode = octeon_cf_set_dmamode,
  710. .dev_config = octeon_cf_dev_config,
  711. };
  712. static int octeon_cf_probe(struct platform_device *pdev)
  713. {
  714. struct resource *res_cs0, *res_cs1;
  715. bool is_16bit;
  716. const __be32 *cs_num;
  717. struct property *reg_prop;
  718. int n_addr, n_size, reg_len;
  719. struct device_node *node;
  720. void __iomem *cs0;
  721. void __iomem *cs1 = NULL;
  722. struct ata_host *host;
  723. struct ata_port *ap;
  724. int irq = 0;
  725. irq_handler_t irq_handler = NULL;
  726. void __iomem *base;
  727. struct octeon_cf_port *cf_port;
  728. int rv = -ENOMEM;
  729. u32 bus_width;
  730. node = pdev->dev.of_node;
  731. if (node == NULL)
  732. return -EINVAL;
  733. cf_port = devm_kzalloc(&pdev->dev, sizeof(*cf_port), GFP_KERNEL);
  734. if (!cf_port)
  735. return -ENOMEM;
  736. cf_port->is_true_ide = of_property_read_bool(node, "cavium,true-ide");
  737. if (of_property_read_u32(node, "cavium,bus-width", &bus_width) == 0)
  738. is_16bit = (bus_width == 16);
  739. else
  740. is_16bit = false;
  741. n_addr = of_n_addr_cells(node);
  742. n_size = of_n_size_cells(node);
  743. reg_prop = of_find_property(node, "reg", &reg_len);
  744. if (!reg_prop || reg_len < sizeof(__be32))
  745. return -EINVAL;
  746. cs_num = reg_prop->value;
  747. cf_port->cs0 = be32_to_cpup(cs_num);
  748. if (cf_port->is_true_ide) {
  749. struct device_node *dma_node;
  750. dma_node = of_parse_phandle(node,
  751. "cavium,dma-engine-handle", 0);
  752. if (dma_node) {
  753. struct platform_device *dma_dev;
  754. dma_dev = of_find_device_by_node(dma_node);
  755. if (dma_dev) {
  756. struct resource *res_dma;
  757. int i;
  758. res_dma = platform_get_resource(dma_dev, IORESOURCE_MEM, 0);
  759. if (!res_dma) {
  760. of_node_put(dma_node);
  761. return -EINVAL;
  762. }
  763. cf_port->dma_base = (u64)devm_ioremap(&pdev->dev, res_dma->start,
  764. resource_size(res_dma));
  765. if (!cf_port->dma_base) {
  766. of_node_put(dma_node);
  767. return -EINVAL;
  768. }
  769. i = platform_get_irq(dma_dev, 0);
  770. if (i > 0) {
  771. irq = i;
  772. irq_handler = octeon_cf_interrupt;
  773. }
  774. }
  775. of_node_put(dma_node);
  776. }
  777. res_cs1 = platform_get_resource(pdev, IORESOURCE_MEM, 1);
  778. if (!res_cs1)
  779. return -EINVAL;
  780. cs1 = devm_ioremap(&pdev->dev, res_cs1->start,
  781. resource_size(res_cs1));
  782. if (!cs1)
  783. return rv;
  784. if (reg_len < (n_addr + n_size + 1) * sizeof(__be32))
  785. return -EINVAL;
  786. cs_num += n_addr + n_size;
  787. cf_port->cs1 = be32_to_cpup(cs_num);
  788. }
  789. res_cs0 = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  790. if (!res_cs0)
  791. return -EINVAL;
  792. cs0 = devm_ioremap(&pdev->dev, res_cs0->start,
  793. resource_size(res_cs0));
  794. if (!cs0)
  795. return rv;
  796. /* allocate host */
  797. host = ata_host_alloc(&pdev->dev, 1);
  798. if (!host)
  799. return rv;
  800. ap = host->ports[0];
  801. ap->private_data = cf_port;
  802. pdev->dev.platform_data = cf_port;
  803. cf_port->ap = ap;
  804. ap->ops = &octeon_cf_ops;
  805. ap->pio_mask = ATA_PIO6;
  806. ap->flags |= ATA_FLAG_NO_ATAPI | ATA_FLAG_PIO_POLLING;
  807. if (!is_16bit) {
  808. base = cs0 + 0x800;
  809. ap->ioaddr.cmd_addr = base;
  810. ata_sff_std_ports(&ap->ioaddr);
  811. ap->ioaddr.altstatus_addr = base + 0xe;
  812. ap->ioaddr.ctl_addr = base + 0xe;
  813. octeon_cf_ops.sff_data_xfer = octeon_cf_data_xfer8;
  814. } else if (cf_port->is_true_ide) {
  815. base = cs0;
  816. ap->ioaddr.cmd_addr = base + (ATA_REG_CMD << 1) + 1;
  817. ap->ioaddr.data_addr = base + (ATA_REG_DATA << 1);
  818. ap->ioaddr.error_addr = base + (ATA_REG_ERR << 1) + 1;
  819. ap->ioaddr.feature_addr = base + (ATA_REG_FEATURE << 1) + 1;
  820. ap->ioaddr.nsect_addr = base + (ATA_REG_NSECT << 1) + 1;
  821. ap->ioaddr.lbal_addr = base + (ATA_REG_LBAL << 1) + 1;
  822. ap->ioaddr.lbam_addr = base + (ATA_REG_LBAM << 1) + 1;
  823. ap->ioaddr.lbah_addr = base + (ATA_REG_LBAH << 1) + 1;
  824. ap->ioaddr.device_addr = base + (ATA_REG_DEVICE << 1) + 1;
  825. ap->ioaddr.status_addr = base + (ATA_REG_STATUS << 1) + 1;
  826. ap->ioaddr.command_addr = base + (ATA_REG_CMD << 1) + 1;
  827. ap->ioaddr.altstatus_addr = cs1 + (6 << 1) + 1;
  828. ap->ioaddr.ctl_addr = cs1 + (6 << 1) + 1;
  829. octeon_cf_ops.sff_data_xfer = octeon_cf_data_xfer16;
  830. ap->mwdma_mask = enable_dma ? ATA_MWDMA4 : 0;
  831. /* True IDE mode needs a timer to poll for not-busy. */
  832. hrtimer_init(&cf_port->delayed_finish, CLOCK_MONOTONIC,
  833. HRTIMER_MODE_REL);
  834. cf_port->delayed_finish.function = octeon_cf_delayed_finish;
  835. } else {
  836. /* 16 bit but not True IDE */
  837. base = cs0 + 0x800;
  838. octeon_cf_ops.sff_data_xfer = octeon_cf_data_xfer16;
  839. octeon_cf_ops.softreset = octeon_cf_softreset16;
  840. octeon_cf_ops.sff_check_status = octeon_cf_check_status16;
  841. octeon_cf_ops.sff_tf_read = octeon_cf_tf_read16;
  842. octeon_cf_ops.sff_tf_load = octeon_cf_tf_load16;
  843. octeon_cf_ops.sff_exec_command = octeon_cf_exec_command16;
  844. ap->ioaddr.data_addr = base + ATA_REG_DATA;
  845. ap->ioaddr.nsect_addr = base + ATA_REG_NSECT;
  846. ap->ioaddr.lbal_addr = base + ATA_REG_LBAL;
  847. ap->ioaddr.ctl_addr = base + 0xe;
  848. ap->ioaddr.altstatus_addr = base + 0xe;
  849. }
  850. cf_port->c0 = ap->ioaddr.ctl_addr;
  851. rv = dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
  852. if (rv)
  853. return rv;
  854. ata_port_desc(ap, "cmd %p ctl %p", base, ap->ioaddr.ctl_addr);
  855. dev_info(&pdev->dev, "version " DRV_VERSION" %d bit%s.\n",
  856. is_16bit ? 16 : 8,
  857. cf_port->is_true_ide ? ", True IDE" : "");
  858. return ata_host_activate(host, irq, irq_handler,
  859. IRQF_SHARED, &octeon_cf_sht);
  860. }
  861. static void octeon_cf_shutdown(struct device *dev)
  862. {
  863. union cvmx_mio_boot_dma_cfgx dma_cfg;
  864. union cvmx_mio_boot_dma_intx dma_int;
  865. struct octeon_cf_port *cf_port = dev_get_platdata(dev);
  866. if (cf_port->dma_base) {
  867. /* Stop and clear the dma engine. */
  868. dma_cfg.u64 = 0;
  869. dma_cfg.s.size = -1;
  870. cvmx_write_csr(cf_port->dma_base + DMA_CFG, dma_cfg.u64);
  871. /* Disable the interrupt. */
  872. dma_int.u64 = 0;
  873. cvmx_write_csr(cf_port->dma_base + DMA_INT_EN, dma_int.u64);
  874. /* Clear the DMA complete status */
  875. dma_int.s.done = 1;
  876. cvmx_write_csr(cf_port->dma_base + DMA_INT, dma_int.u64);
  877. __raw_writeb(0, cf_port->c0);
  878. udelay(20);
  879. __raw_writeb(ATA_SRST, cf_port->c0);
  880. udelay(20);
  881. __raw_writeb(0, cf_port->c0);
  882. mdelay(100);
  883. }
  884. }
  885. static const struct of_device_id octeon_cf_match[] = {
  886. {
  887. .compatible = "cavium,ebt3000-compact-flash",
  888. },
  889. {},
  890. };
  891. MODULE_DEVICE_TABLE(of, octeon_cf_match);
  892. static struct platform_driver octeon_cf_driver = {
  893. .probe = octeon_cf_probe,
  894. .driver = {
  895. .name = DRV_NAME,
  896. .of_match_table = octeon_cf_match,
  897. .shutdown = octeon_cf_shutdown
  898. },
  899. };
  900. static int __init octeon_cf_init(void)
  901. {
  902. return platform_driver_register(&octeon_cf_driver);
  903. }
  904. MODULE_AUTHOR("David Daney <ddaney@caviumnetworks.com>");
  905. MODULE_DESCRIPTION("low-level driver for Cavium OCTEON Compact Flash PATA");
  906. MODULE_LICENSE("GPL");
  907. MODULE_VERSION(DRV_VERSION);
  908. MODULE_ALIAS("platform:" DRV_NAME);
  909. module_init(octeon_cf_init);