pata_hpt366.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Libata driver for the highpoint 366 and 368 UDMA66 ATA controllers.
  4. *
  5. * This driver is heavily based upon:
  6. *
  7. * linux/drivers/ide/pci/hpt366.c Version 0.36 April 25, 2003
  8. *
  9. * Copyright (C) 1999-2003 Andre Hedrick <andre@linux-ide.org>
  10. * Portions Copyright (C) 2001 Sun Microsystems, Inc.
  11. * Portions Copyright (C) 2003 Red Hat Inc
  12. *
  13. *
  14. * TODO
  15. * Look into engine reset on timeout errors. Should not be required.
  16. */
  17. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  18. #include <linux/kernel.h>
  19. #include <linux/module.h>
  20. #include <linux/pci.h>
  21. #include <linux/blkdev.h>
  22. #include <linux/delay.h>
  23. #include <scsi/scsi_host.h>
  24. #include <linux/libata.h>
  25. #define DRV_NAME "pata_hpt366"
  26. #define DRV_VERSION "0.6.11"
  27. struct hpt_clock {
  28. u8 xfer_mode;
  29. u32 timing;
  30. };
  31. /* key for bus clock timings
  32. * bit
  33. * 0:3 data_high_time. Inactive time of DIOW_/DIOR_ for PIO and MW DMA.
  34. * cycles = value + 1
  35. * 4:7 data_low_time. Active time of DIOW_/DIOR_ for PIO and MW DMA.
  36. * cycles = value + 1
  37. * 8:11 cmd_high_time. Inactive time of DIOW_/DIOR_ during task file
  38. * register access.
  39. * 12:15 cmd_low_time. Active time of DIOW_/DIOR_ during task file
  40. * register access.
  41. * 16:18 udma_cycle_time. Clock cycles for UDMA xfer?
  42. * 19:21 pre_high_time. Time to initialize 1st cycle for PIO and MW DMA xfer.
  43. * 22:24 cmd_pre_high_time. Time to initialize 1st PIO cycle for task file
  44. * register access.
  45. * 28 UDMA enable.
  46. * 29 DMA enable.
  47. * 30 PIO_MST enable. If set, the chip is in bus master mode during
  48. * PIO xfer.
  49. * 31 FIFO enable.
  50. */
  51. static const struct hpt_clock hpt366_40[] = {
  52. { XFER_UDMA_4, 0x900fd943 },
  53. { XFER_UDMA_3, 0x900ad943 },
  54. { XFER_UDMA_2, 0x900bd943 },
  55. { XFER_UDMA_1, 0x9008d943 },
  56. { XFER_UDMA_0, 0x9008d943 },
  57. { XFER_MW_DMA_2, 0xa008d943 },
  58. { XFER_MW_DMA_1, 0xa010d955 },
  59. { XFER_MW_DMA_0, 0xa010d9fc },
  60. { XFER_PIO_4, 0xc008d963 },
  61. { XFER_PIO_3, 0xc010d974 },
  62. { XFER_PIO_2, 0xc010d997 },
  63. { XFER_PIO_1, 0xc010d9c7 },
  64. { XFER_PIO_0, 0xc018d9d9 },
  65. { 0, 0x0120d9d9 }
  66. };
  67. static const struct hpt_clock hpt366_33[] = {
  68. { XFER_UDMA_4, 0x90c9a731 },
  69. { XFER_UDMA_3, 0x90cfa731 },
  70. { XFER_UDMA_2, 0x90caa731 },
  71. { XFER_UDMA_1, 0x90cba731 },
  72. { XFER_UDMA_0, 0x90c8a731 },
  73. { XFER_MW_DMA_2, 0xa0c8a731 },
  74. { XFER_MW_DMA_1, 0xa0c8a732 }, /* 0xa0c8a733 */
  75. { XFER_MW_DMA_0, 0xa0c8a797 },
  76. { XFER_PIO_4, 0xc0c8a731 },
  77. { XFER_PIO_3, 0xc0c8a742 },
  78. { XFER_PIO_2, 0xc0d0a753 },
  79. { XFER_PIO_1, 0xc0d0a7a3 }, /* 0xc0d0a793 */
  80. { XFER_PIO_0, 0xc0d0a7aa }, /* 0xc0d0a7a7 */
  81. { 0, 0x0120a7a7 }
  82. };
  83. static const struct hpt_clock hpt366_25[] = {
  84. { XFER_UDMA_4, 0x90c98521 },
  85. { XFER_UDMA_3, 0x90cf8521 },
  86. { XFER_UDMA_2, 0x90cf8521 },
  87. { XFER_UDMA_1, 0x90cb8521 },
  88. { XFER_UDMA_0, 0x90cb8521 },
  89. { XFER_MW_DMA_2, 0xa0ca8521 },
  90. { XFER_MW_DMA_1, 0xa0ca8532 },
  91. { XFER_MW_DMA_0, 0xa0ca8575 },
  92. { XFER_PIO_4, 0xc0ca8521 },
  93. { XFER_PIO_3, 0xc0ca8532 },
  94. { XFER_PIO_2, 0xc0ca8542 },
  95. { XFER_PIO_1, 0xc0d08572 },
  96. { XFER_PIO_0, 0xc0d08585 },
  97. { 0, 0x01208585 }
  98. };
  99. /**
  100. * hpt36x_find_mode - find the hpt36x timing
  101. * @ap: ATA port
  102. * @speed: transfer mode
  103. *
  104. * Return the 32bit register programming information for this channel
  105. * that matches the speed provided.
  106. */
  107. static u32 hpt36x_find_mode(struct ata_port *ap, int speed)
  108. {
  109. struct hpt_clock *clocks = ap->host->private_data;
  110. while (clocks->xfer_mode) {
  111. if (clocks->xfer_mode == speed)
  112. return clocks->timing;
  113. clocks++;
  114. }
  115. BUG();
  116. return 0xffffffffU; /* silence compiler warning */
  117. }
  118. static const char * const bad_ata33[] = {
  119. "Maxtor 92720U8", "Maxtor 92040U6", "Maxtor 91360U4", "Maxtor 91020U3",
  120. "Maxtor 90845U3", "Maxtor 90650U2",
  121. "Maxtor 91360D8", "Maxtor 91190D7", "Maxtor 91020D6", "Maxtor 90845D5",
  122. "Maxtor 90680D4", "Maxtor 90510D3", "Maxtor 90340D2",
  123. "Maxtor 91152D8", "Maxtor 91008D7", "Maxtor 90845D6", "Maxtor 90840D6",
  124. "Maxtor 90720D5", "Maxtor 90648D5", "Maxtor 90576D4",
  125. "Maxtor 90510D4",
  126. "Maxtor 90432D3", "Maxtor 90288D2", "Maxtor 90256D2",
  127. "Maxtor 91000D8", "Maxtor 90910D8", "Maxtor 90875D7", "Maxtor 90840D7",
  128. "Maxtor 90750D6", "Maxtor 90625D5", "Maxtor 90500D4",
  129. "Maxtor 91728D8", "Maxtor 91512D7", "Maxtor 91303D6", "Maxtor 91080D5",
  130. "Maxtor 90845D4", "Maxtor 90680D4", "Maxtor 90648D3", "Maxtor 90432D2",
  131. NULL
  132. };
  133. static const char * const bad_ata66_4[] = {
  134. "IBM-DTLA-307075",
  135. "IBM-DTLA-307060",
  136. "IBM-DTLA-307045",
  137. "IBM-DTLA-307030",
  138. "IBM-DTLA-307020",
  139. "IBM-DTLA-307015",
  140. "IBM-DTLA-305040",
  141. "IBM-DTLA-305030",
  142. "IBM-DTLA-305020",
  143. "IC35L010AVER07-0",
  144. "IC35L020AVER07-0",
  145. "IC35L030AVER07-0",
  146. "IC35L040AVER07-0",
  147. "IC35L060AVER07-0",
  148. "WDC AC310200R",
  149. NULL
  150. };
  151. static const char * const bad_ata66_3[] = {
  152. "WDC AC310200R",
  153. NULL
  154. };
  155. static int hpt_dma_blacklisted(const struct ata_device *dev, char *modestr,
  156. const char * const list[])
  157. {
  158. unsigned char model_num[ATA_ID_PROD_LEN + 1];
  159. int i;
  160. ata_id_c_string(dev->id, model_num, ATA_ID_PROD, sizeof(model_num));
  161. i = match_string(list, -1, model_num);
  162. if (i >= 0) {
  163. pr_warn("%s is not supported for %s\n", modestr, list[i]);
  164. return 1;
  165. }
  166. return 0;
  167. }
  168. /**
  169. * hpt366_filter - mode selection filter
  170. * @adev: ATA device
  171. *
  172. * Block UDMA on devices that cause trouble with this controller.
  173. */
  174. static unsigned long hpt366_filter(struct ata_device *adev, unsigned long mask)
  175. {
  176. if (adev->class == ATA_DEV_ATA) {
  177. if (hpt_dma_blacklisted(adev, "UDMA", bad_ata33))
  178. mask &= ~ATA_MASK_UDMA;
  179. if (hpt_dma_blacklisted(adev, "UDMA3", bad_ata66_3))
  180. mask &= ~(0xF8 << ATA_SHIFT_UDMA);
  181. if (hpt_dma_blacklisted(adev, "UDMA4", bad_ata66_4))
  182. mask &= ~(0xF0 << ATA_SHIFT_UDMA);
  183. } else if (adev->class == ATA_DEV_ATAPI)
  184. mask &= ~(ATA_MASK_MWDMA | ATA_MASK_UDMA);
  185. return mask;
  186. }
  187. static int hpt36x_cable_detect(struct ata_port *ap)
  188. {
  189. struct pci_dev *pdev = to_pci_dev(ap->host->dev);
  190. u8 ata66;
  191. /*
  192. * Each channel of pata_hpt366 occupies separate PCI function
  193. * as the primary channel and bit1 indicates the cable type.
  194. */
  195. pci_read_config_byte(pdev, 0x5A, &ata66);
  196. if (ata66 & 2)
  197. return ATA_CBL_PATA40;
  198. return ATA_CBL_PATA80;
  199. }
  200. static void hpt366_set_mode(struct ata_port *ap, struct ata_device *adev,
  201. u8 mode)
  202. {
  203. struct pci_dev *pdev = to_pci_dev(ap->host->dev);
  204. u32 addr = 0x40 + 4 * adev->devno;
  205. u32 mask, reg, t;
  206. /* determine timing mask and find matching clock entry */
  207. if (mode < XFER_MW_DMA_0)
  208. mask = 0xc1f8ffff;
  209. else if (mode < XFER_UDMA_0)
  210. mask = 0x303800ff;
  211. else
  212. mask = 0x30070000;
  213. t = hpt36x_find_mode(ap, mode);
  214. /*
  215. * Combine new mode bits with old config bits and disable
  216. * on-chip PIO FIFO/buffer (and PIO MST mode as well) to avoid
  217. * problems handling I/O errors later.
  218. */
  219. pci_read_config_dword(pdev, addr, &reg);
  220. reg = ((reg & ~mask) | (t & mask)) & ~0xc0000000;
  221. pci_write_config_dword(pdev, addr, reg);
  222. }
  223. /**
  224. * hpt366_set_piomode - PIO setup
  225. * @ap: ATA interface
  226. * @adev: device on the interface
  227. *
  228. * Perform PIO mode setup.
  229. */
  230. static void hpt366_set_piomode(struct ata_port *ap, struct ata_device *adev)
  231. {
  232. hpt366_set_mode(ap, adev, adev->pio_mode);
  233. }
  234. /**
  235. * hpt366_set_dmamode - DMA timing setup
  236. * @ap: ATA interface
  237. * @adev: Device being configured
  238. *
  239. * Set up the channel for MWDMA or UDMA modes. Much the same as with
  240. * PIO, load the mode number and then set MWDMA or UDMA flag.
  241. */
  242. static void hpt366_set_dmamode(struct ata_port *ap, struct ata_device *adev)
  243. {
  244. hpt366_set_mode(ap, adev, adev->dma_mode);
  245. }
  246. static struct scsi_host_template hpt36x_sht = {
  247. ATA_BMDMA_SHT(DRV_NAME),
  248. };
  249. /*
  250. * Configuration for HPT366/68
  251. */
  252. static struct ata_port_operations hpt366_port_ops = {
  253. .inherits = &ata_bmdma_port_ops,
  254. .cable_detect = hpt36x_cable_detect,
  255. .mode_filter = hpt366_filter,
  256. .set_piomode = hpt366_set_piomode,
  257. .set_dmamode = hpt366_set_dmamode,
  258. };
  259. /**
  260. * hpt36x_init_chipset - common chip setup
  261. * @dev: PCI device
  262. *
  263. * Perform the chip setup work that must be done at both init and
  264. * resume time
  265. */
  266. static void hpt36x_init_chipset(struct pci_dev *dev)
  267. {
  268. u8 drive_fast;
  269. pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4));
  270. pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78);
  271. pci_write_config_byte(dev, PCI_MIN_GNT, 0x08);
  272. pci_write_config_byte(dev, PCI_MAX_LAT, 0x08);
  273. pci_read_config_byte(dev, 0x51, &drive_fast);
  274. if (drive_fast & 0x80)
  275. pci_write_config_byte(dev, 0x51, drive_fast & ~0x80);
  276. }
  277. /**
  278. * hpt36x_init_one - Initialise an HPT366/368
  279. * @dev: PCI device
  280. * @id: Entry in match table
  281. *
  282. * Initialise an HPT36x device. There are some interesting complications
  283. * here. Firstly the chip may report 366 and be one of several variants.
  284. * Secondly all the timings depend on the clock for the chip which we must
  285. * detect and look up
  286. *
  287. * This is the known chip mappings. It may be missing a couple of later
  288. * releases.
  289. *
  290. * Chip version PCI Rev Notes
  291. * HPT366 4 (HPT366) 0 UDMA66
  292. * HPT366 4 (HPT366) 1 UDMA66
  293. * HPT368 4 (HPT366) 2 UDMA66
  294. * HPT37x/30x 4 (HPT366) 3+ Other driver
  295. *
  296. */
  297. static int hpt36x_init_one(struct pci_dev *dev, const struct pci_device_id *id)
  298. {
  299. static const struct ata_port_info info_hpt366 = {
  300. .flags = ATA_FLAG_SLAVE_POSS,
  301. .pio_mask = ATA_PIO4,
  302. .mwdma_mask = ATA_MWDMA2,
  303. .udma_mask = ATA_UDMA4,
  304. .port_ops = &hpt366_port_ops
  305. };
  306. const struct ata_port_info *ppi[] = { &info_hpt366, NULL };
  307. const void *hpriv = NULL;
  308. u32 reg1;
  309. int rc;
  310. rc = pcim_enable_device(dev);
  311. if (rc)
  312. return rc;
  313. /* May be a later chip in disguise. Check */
  314. /* Newer chips are not in the HPT36x driver. Ignore them */
  315. if (dev->revision > 2)
  316. return -ENODEV;
  317. hpt36x_init_chipset(dev);
  318. pci_read_config_dword(dev, 0x40, &reg1);
  319. /* PCI clocking determines the ATA timing values to use */
  320. /* info_hpt366 is safe against re-entry so we can scribble on it */
  321. switch ((reg1 & 0xf00) >> 8) {
  322. case 9:
  323. hpriv = &hpt366_40;
  324. break;
  325. case 5:
  326. hpriv = &hpt366_25;
  327. break;
  328. default:
  329. hpriv = &hpt366_33;
  330. break;
  331. }
  332. /* Now kick off ATA set up */
  333. return ata_pci_bmdma_init_one(dev, ppi, &hpt36x_sht, (void *)hpriv, 0);
  334. }
  335. #ifdef CONFIG_PM_SLEEP
  336. static int hpt36x_reinit_one(struct pci_dev *dev)
  337. {
  338. struct ata_host *host = pci_get_drvdata(dev);
  339. int rc;
  340. rc = ata_pci_device_do_resume(dev);
  341. if (rc)
  342. return rc;
  343. hpt36x_init_chipset(dev);
  344. ata_host_resume(host);
  345. return 0;
  346. }
  347. #endif
  348. static const struct pci_device_id hpt36x[] = {
  349. { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT366), },
  350. { },
  351. };
  352. static struct pci_driver hpt36x_pci_driver = {
  353. .name = DRV_NAME,
  354. .id_table = hpt36x,
  355. .probe = hpt36x_init_one,
  356. .remove = ata_pci_remove_one,
  357. #ifdef CONFIG_PM_SLEEP
  358. .suspend = ata_pci_device_suspend,
  359. .resume = hpt36x_reinit_one,
  360. #endif
  361. };
  362. module_pci_driver(hpt36x_pci_driver);
  363. MODULE_AUTHOR("Alan Cox");
  364. MODULE_DESCRIPTION("low-level driver for the Highpoint HPT366/368");
  365. MODULE_LICENSE("GPL");
  366. MODULE_DEVICE_TABLE(pci, hpt36x);
  367. MODULE_VERSION(DRV_VERSION);