pata_efar.c 8.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * pata_efar.c - EFAR PIIX clone controller driver
  4. *
  5. * (C) 2005 Red Hat
  6. * (C) 2009-2010 Bartlomiej Zolnierkiewicz
  7. *
  8. * Some parts based on ata_piix.c by Jeff Garzik and others.
  9. *
  10. * The EFAR is a PIIX4 clone with UDMA66 support. Unlike the later
  11. * Intel ICH controllers the EFAR widened the UDMA mode register bits
  12. * and doesn't require the funky clock selection.
  13. */
  14. #include <linux/kernel.h>
  15. #include <linux/module.h>
  16. #include <linux/pci.h>
  17. #include <linux/blkdev.h>
  18. #include <linux/delay.h>
  19. #include <linux/device.h>
  20. #include <scsi/scsi_host.h>
  21. #include <linux/libata.h>
  22. #include <linux/ata.h>
  23. #define DRV_NAME "pata_efar"
  24. #define DRV_VERSION "0.4.5"
  25. /**
  26. * efar_pre_reset - Enable bits
  27. * @link: ATA link
  28. * @deadline: deadline jiffies for the operation
  29. *
  30. * Perform cable detection for the EFAR ATA interface. This is
  31. * different to the PIIX arrangement
  32. */
  33. static int efar_pre_reset(struct ata_link *link, unsigned long deadline)
  34. {
  35. static const struct pci_bits efar_enable_bits[] = {
  36. { 0x41U, 1U, 0x80UL, 0x80UL }, /* port 0 */
  37. { 0x43U, 1U, 0x80UL, 0x80UL }, /* port 1 */
  38. };
  39. struct ata_port *ap = link->ap;
  40. struct pci_dev *pdev = to_pci_dev(ap->host->dev);
  41. if (!pci_test_config_bits(pdev, &efar_enable_bits[ap->port_no]))
  42. return -ENOENT;
  43. return ata_sff_prereset(link, deadline);
  44. }
  45. /**
  46. * efar_cable_detect - check for 40/80 pin
  47. * @ap: Port
  48. *
  49. * Perform cable detection for the EFAR ATA interface. This is
  50. * different to the PIIX arrangement
  51. */
  52. static int efar_cable_detect(struct ata_port *ap)
  53. {
  54. struct pci_dev *pdev = to_pci_dev(ap->host->dev);
  55. u8 tmp;
  56. pci_read_config_byte(pdev, 0x47, &tmp);
  57. if (tmp & (2 >> ap->port_no))
  58. return ATA_CBL_PATA40;
  59. return ATA_CBL_PATA80;
  60. }
  61. static DEFINE_SPINLOCK(efar_lock);
  62. /**
  63. * efar_set_piomode - Initialize host controller PATA PIO timings
  64. * @ap: Port whose timings we are configuring
  65. * @adev: Device to program
  66. *
  67. * Set PIO mode for device, in host controller PCI config space.
  68. *
  69. * LOCKING:
  70. * None (inherited from caller).
  71. */
  72. static void efar_set_piomode (struct ata_port *ap, struct ata_device *adev)
  73. {
  74. unsigned int pio = adev->pio_mode - XFER_PIO_0;
  75. struct pci_dev *dev = to_pci_dev(ap->host->dev);
  76. unsigned int master_port = ap->port_no ? 0x42 : 0x40;
  77. unsigned long flags;
  78. u16 master_data;
  79. u8 udma_enable;
  80. int control = 0;
  81. /*
  82. * See Intel Document 298600-004 for the timing programing rules
  83. * for PIIX/ICH. The EFAR is a clone so very similar
  84. */
  85. static const /* ISP RTC */
  86. u8 timings[][2] = { { 0, 0 },
  87. { 0, 0 },
  88. { 1, 0 },
  89. { 2, 1 },
  90. { 2, 3 }, };
  91. if (pio > 1)
  92. control |= 1; /* TIME */
  93. if (ata_pio_need_iordy(adev)) /* PIO 3/4 require IORDY */
  94. control |= 2; /* IE */
  95. /* Intel specifies that the prefetch/posting is for disk only */
  96. if (adev->class == ATA_DEV_ATA)
  97. control |= 4; /* PPE */
  98. spin_lock_irqsave(&efar_lock, flags);
  99. pci_read_config_word(dev, master_port, &master_data);
  100. /* Set PPE, IE, and TIME as appropriate */
  101. if (adev->devno == 0) {
  102. master_data &= 0xCCF0;
  103. master_data |= control;
  104. master_data |= (timings[pio][0] << 12) |
  105. (timings[pio][1] << 8);
  106. } else {
  107. int shift = 4 * ap->port_no;
  108. u8 slave_data;
  109. master_data &= 0xFF0F;
  110. master_data |= (control << 4);
  111. /* Slave timing in separate register */
  112. pci_read_config_byte(dev, 0x44, &slave_data);
  113. slave_data &= ap->port_no ? 0x0F : 0xF0;
  114. slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) << shift;
  115. pci_write_config_byte(dev, 0x44, slave_data);
  116. }
  117. master_data |= 0x4000; /* Ensure SITRE is set */
  118. pci_write_config_word(dev, master_port, master_data);
  119. pci_read_config_byte(dev, 0x48, &udma_enable);
  120. udma_enable &= ~(1 << (2 * ap->port_no + adev->devno));
  121. pci_write_config_byte(dev, 0x48, udma_enable);
  122. spin_unlock_irqrestore(&efar_lock, flags);
  123. }
  124. /**
  125. * efar_set_dmamode - Initialize host controller PATA DMA timings
  126. * @ap: Port whose timings we are configuring
  127. * @adev: Device to program
  128. *
  129. * Set UDMA/MWDMA mode for device, in host controller PCI config space.
  130. *
  131. * LOCKING:
  132. * None (inherited from caller).
  133. */
  134. static void efar_set_dmamode (struct ata_port *ap, struct ata_device *adev)
  135. {
  136. struct pci_dev *dev = to_pci_dev(ap->host->dev);
  137. u8 master_port = ap->port_no ? 0x42 : 0x40;
  138. u16 master_data;
  139. u8 speed = adev->dma_mode;
  140. int devid = adev->devno + 2 * ap->port_no;
  141. unsigned long flags;
  142. u8 udma_enable;
  143. static const /* ISP RTC */
  144. u8 timings[][2] = { { 0, 0 },
  145. { 0, 0 },
  146. { 1, 0 },
  147. { 2, 1 },
  148. { 2, 3 }, };
  149. spin_lock_irqsave(&efar_lock, flags);
  150. pci_read_config_word(dev, master_port, &master_data);
  151. pci_read_config_byte(dev, 0x48, &udma_enable);
  152. if (speed >= XFER_UDMA_0) {
  153. unsigned int udma = adev->dma_mode - XFER_UDMA_0;
  154. u16 udma_timing;
  155. udma_enable |= (1 << devid);
  156. /* Load the UDMA mode number */
  157. pci_read_config_word(dev, 0x4A, &udma_timing);
  158. udma_timing &= ~(7 << (4 * devid));
  159. udma_timing |= udma << (4 * devid);
  160. pci_write_config_word(dev, 0x4A, udma_timing);
  161. } else {
  162. /*
  163. * MWDMA is driven by the PIO timings. We must also enable
  164. * IORDY unconditionally along with TIME1. PPE has already
  165. * been set when the PIO timing was set.
  166. */
  167. unsigned int mwdma = adev->dma_mode - XFER_MW_DMA_0;
  168. unsigned int control;
  169. u8 slave_data;
  170. const unsigned int needed_pio[3] = {
  171. XFER_PIO_0, XFER_PIO_3, XFER_PIO_4
  172. };
  173. int pio = needed_pio[mwdma] - XFER_PIO_0;
  174. control = 3; /* IORDY|TIME1 */
  175. /* If the drive MWDMA is faster than it can do PIO then
  176. we must force PIO into PIO0 */
  177. if (adev->pio_mode < needed_pio[mwdma])
  178. /* Enable DMA timing only */
  179. control |= 8; /* PIO cycles in PIO0 */
  180. if (adev->devno) { /* Slave */
  181. master_data &= 0xFF4F; /* Mask out IORDY|TIME1|DMAONLY */
  182. master_data |= control << 4;
  183. pci_read_config_byte(dev, 0x44, &slave_data);
  184. slave_data &= ap->port_no ? 0x0F : 0xF0;
  185. /* Load the matching timing */
  186. slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) << (ap->port_no ? 4 : 0);
  187. pci_write_config_byte(dev, 0x44, slave_data);
  188. } else { /* Master */
  189. master_data &= 0xCCF4; /* Mask out IORDY|TIME1|DMAONLY
  190. and master timing bits */
  191. master_data |= control;
  192. master_data |=
  193. (timings[pio][0] << 12) |
  194. (timings[pio][1] << 8);
  195. }
  196. udma_enable &= ~(1 << devid);
  197. pci_write_config_word(dev, master_port, master_data);
  198. }
  199. pci_write_config_byte(dev, 0x48, udma_enable);
  200. spin_unlock_irqrestore(&efar_lock, flags);
  201. }
  202. static struct scsi_host_template efar_sht = {
  203. ATA_BMDMA_SHT(DRV_NAME),
  204. };
  205. static struct ata_port_operations efar_ops = {
  206. .inherits = &ata_bmdma_port_ops,
  207. .cable_detect = efar_cable_detect,
  208. .set_piomode = efar_set_piomode,
  209. .set_dmamode = efar_set_dmamode,
  210. .prereset = efar_pre_reset,
  211. };
  212. /**
  213. * efar_init_one - Register EFAR ATA PCI device with kernel services
  214. * @pdev: PCI device to register
  215. * @ent: Entry in efar_pci_tbl matching with @pdev
  216. *
  217. * Called from kernel PCI layer.
  218. *
  219. * LOCKING:
  220. * Inherited from PCI layer (may sleep).
  221. *
  222. * RETURNS:
  223. * Zero on success, or -ERRNO value.
  224. */
  225. static int efar_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
  226. {
  227. static const struct ata_port_info info = {
  228. .flags = ATA_FLAG_SLAVE_POSS,
  229. .pio_mask = ATA_PIO4,
  230. .mwdma_mask = ATA_MWDMA12_ONLY,
  231. .udma_mask = ATA_UDMA4,
  232. .port_ops = &efar_ops,
  233. };
  234. const struct ata_port_info *ppi[] = { &info, &info };
  235. ata_print_version_once(&pdev->dev, DRV_VERSION);
  236. return ata_pci_bmdma_init_one(pdev, ppi, &efar_sht, NULL,
  237. ATA_HOST_PARALLEL_SCAN);
  238. }
  239. static const struct pci_device_id efar_pci_tbl[] = {
  240. { PCI_VDEVICE(EFAR, 0x9130), },
  241. { } /* terminate list */
  242. };
  243. static struct pci_driver efar_pci_driver = {
  244. .name = DRV_NAME,
  245. .id_table = efar_pci_tbl,
  246. .probe = efar_init_one,
  247. .remove = ata_pci_remove_one,
  248. #ifdef CONFIG_PM_SLEEP
  249. .suspend = ata_pci_device_suspend,
  250. .resume = ata_pci_device_resume,
  251. #endif
  252. };
  253. module_pci_driver(efar_pci_driver);
  254. MODULE_AUTHOR("Alan Cox");
  255. MODULE_DESCRIPTION("SCSI low-level driver for EFAR PIIX clones");
  256. MODULE_LICENSE("GPL");
  257. MODULE_DEVICE_TABLE(pci, efar_pci_tbl);
  258. MODULE_VERSION(DRV_VERSION);