pata_cs5530.c 8.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * pata-cs5530.c - CS5530 PATA for new ATA layer
  4. * (C) 2005 Red Hat Inc
  5. *
  6. * based upon cs5530.c by Mark Lord.
  7. *
  8. * Loosely based on the piix & svwks drivers.
  9. *
  10. * Documentation:
  11. * Available from AMD web site.
  12. */
  13. #include <linux/kernel.h>
  14. #include <linux/module.h>
  15. #include <linux/pci.h>
  16. #include <linux/blkdev.h>
  17. #include <linux/delay.h>
  18. #include <scsi/scsi_host.h>
  19. #include <linux/libata.h>
  20. #include <linux/dmi.h>
  21. #define DRV_NAME "pata_cs5530"
  22. #define DRV_VERSION "0.7.4"
  23. static void __iomem *cs5530_port_base(struct ata_port *ap)
  24. {
  25. unsigned long bmdma = (unsigned long)ap->ioaddr.bmdma_addr;
  26. return (void __iomem *)((bmdma & ~0x0F) + 0x20 + 0x10 * ap->port_no);
  27. }
  28. /**
  29. * cs5530_set_piomode - PIO setup
  30. * @ap: ATA interface
  31. * @adev: device on the interface
  32. *
  33. * Set our PIO requirements. This is fairly simple on the CS5530
  34. * chips.
  35. */
  36. static void cs5530_set_piomode(struct ata_port *ap, struct ata_device *adev)
  37. {
  38. static const unsigned int cs5530_pio_timings[2][5] = {
  39. {0x00009172, 0x00012171, 0x00020080, 0x00032010, 0x00040010},
  40. {0xd1329172, 0x71212171, 0x30200080, 0x20102010, 0x00100010}
  41. };
  42. void __iomem *base = cs5530_port_base(ap);
  43. u32 tuning;
  44. int format;
  45. /* Find out which table to use */
  46. tuning = ioread32(base + 0x04);
  47. format = (tuning & 0x80000000UL) ? 1 : 0;
  48. /* Now load the right timing register */
  49. if (adev->devno)
  50. base += 0x08;
  51. iowrite32(cs5530_pio_timings[format][adev->pio_mode - XFER_PIO_0], base);
  52. }
  53. /**
  54. * cs5530_set_dmamode - DMA timing setup
  55. * @ap: ATA interface
  56. * @adev: Device being configured
  57. *
  58. * We cannot mix MWDMA and UDMA without reloading timings each switch
  59. * master to slave. We track the last DMA setup in order to minimise
  60. * reloads.
  61. */
  62. static void cs5530_set_dmamode(struct ata_port *ap, struct ata_device *adev)
  63. {
  64. void __iomem *base = cs5530_port_base(ap);
  65. u32 tuning, timing = 0;
  66. u8 reg;
  67. /* Find out which table to use */
  68. tuning = ioread32(base + 0x04);
  69. switch(adev->dma_mode) {
  70. case XFER_UDMA_0:
  71. timing = 0x00921250;break;
  72. case XFER_UDMA_1:
  73. timing = 0x00911140;break;
  74. case XFER_UDMA_2:
  75. timing = 0x00911030;break;
  76. case XFER_MW_DMA_0:
  77. timing = 0x00077771;break;
  78. case XFER_MW_DMA_1:
  79. timing = 0x00012121;break;
  80. case XFER_MW_DMA_2:
  81. timing = 0x00002020;break;
  82. default:
  83. BUG();
  84. }
  85. /* Merge in the PIO format bit */
  86. timing |= (tuning & 0x80000000UL);
  87. if (adev->devno == 0) /* Master */
  88. iowrite32(timing, base + 0x04);
  89. else {
  90. if (timing & 0x00100000)
  91. tuning |= 0x00100000; /* UDMA for both */
  92. else
  93. tuning &= ~0x00100000; /* MWDMA for both */
  94. iowrite32(tuning, base + 0x04);
  95. iowrite32(timing, base + 0x0C);
  96. }
  97. /* Set the DMA capable bit in the BMDMA area */
  98. reg = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_STATUS);
  99. reg |= (1 << (5 + adev->devno));
  100. iowrite8(reg, ap->ioaddr.bmdma_addr + ATA_DMA_STATUS);
  101. /* Remember the last DMA setup we did */
  102. ap->private_data = adev;
  103. }
  104. /**
  105. * cs5530_qc_issue - command issue
  106. * @qc: command pending
  107. *
  108. * Called when the libata layer is about to issue a command. We wrap
  109. * this interface so that we can load the correct ATA timings if
  110. * necessary. Specifically we have a problem that there is only
  111. * one MWDMA/UDMA bit.
  112. */
  113. static unsigned int cs5530_qc_issue(struct ata_queued_cmd *qc)
  114. {
  115. struct ata_port *ap = qc->ap;
  116. struct ata_device *adev = qc->dev;
  117. struct ata_device *prev = ap->private_data;
  118. /* See if the DMA settings could be wrong */
  119. if (ata_dma_enabled(adev) && adev != prev && prev != NULL) {
  120. /* Maybe, but do the channels match MWDMA/UDMA ? */
  121. if ((ata_using_udma(adev) && !ata_using_udma(prev)) ||
  122. (ata_using_udma(prev) && !ata_using_udma(adev)))
  123. /* Switch the mode bits */
  124. cs5530_set_dmamode(ap, adev);
  125. }
  126. return ata_bmdma_qc_issue(qc);
  127. }
  128. static struct scsi_host_template cs5530_sht = {
  129. ATA_BMDMA_SHT(DRV_NAME),
  130. .sg_tablesize = LIBATA_DUMB_MAX_PRD,
  131. };
  132. static struct ata_port_operations cs5530_port_ops = {
  133. .inherits = &ata_bmdma_port_ops,
  134. .qc_prep = ata_bmdma_dumb_qc_prep,
  135. .qc_issue = cs5530_qc_issue,
  136. .cable_detect = ata_cable_40wire,
  137. .set_piomode = cs5530_set_piomode,
  138. .set_dmamode = cs5530_set_dmamode,
  139. };
  140. static const struct dmi_system_id palmax_dmi_table[] = {
  141. {
  142. .ident = "Palmax PD1100",
  143. .matches = {
  144. DMI_MATCH(DMI_SYS_VENDOR, "Cyrix"),
  145. DMI_MATCH(DMI_PRODUCT_NAME, "Caddis"),
  146. },
  147. },
  148. { }
  149. };
  150. static int cs5530_is_palmax(void)
  151. {
  152. if (dmi_check_system(palmax_dmi_table)) {
  153. printk(KERN_INFO "Palmax PD1100: Disabling DMA on docking port.\n");
  154. return 1;
  155. }
  156. return 0;
  157. }
  158. /**
  159. * cs5530_init_chip - Chipset init
  160. *
  161. * Perform the chip initialisation work that is shared between both
  162. * setup and resume paths
  163. */
  164. static int cs5530_init_chip(void)
  165. {
  166. struct pci_dev *master_0 = NULL, *cs5530_0 = NULL, *dev = NULL;
  167. while ((dev = pci_get_device(PCI_VENDOR_ID_CYRIX, PCI_ANY_ID, dev)) != NULL) {
  168. switch (dev->device) {
  169. case PCI_DEVICE_ID_CYRIX_PCI_MASTER:
  170. master_0 = pci_dev_get(dev);
  171. break;
  172. case PCI_DEVICE_ID_CYRIX_5530_LEGACY:
  173. cs5530_0 = pci_dev_get(dev);
  174. break;
  175. }
  176. }
  177. if (!master_0) {
  178. printk(KERN_ERR DRV_NAME ": unable to locate PCI MASTER function\n");
  179. goto fail_put;
  180. }
  181. if (!cs5530_0) {
  182. printk(KERN_ERR DRV_NAME ": unable to locate CS5530 LEGACY function\n");
  183. goto fail_put;
  184. }
  185. pci_set_master(cs5530_0);
  186. pci_try_set_mwi(cs5530_0);
  187. /*
  188. * Set PCI CacheLineSize to 16-bytes:
  189. * --> Write 0x04 into 8-bit PCI CACHELINESIZE reg of function 0 of the cs5530
  190. *
  191. * Note: This value is constant because the 5530 is only a Geode companion
  192. */
  193. pci_write_config_byte(cs5530_0, PCI_CACHE_LINE_SIZE, 0x04);
  194. /*
  195. * Disable trapping of UDMA register accesses (Win98 hack):
  196. * --> Write 0x5006 into 16-bit reg at offset 0xd0 of function 0 of the cs5530
  197. */
  198. pci_write_config_word(cs5530_0, 0xd0, 0x5006);
  199. /*
  200. * Bit-1 at 0x40 enables MemoryWriteAndInvalidate on internal X-bus:
  201. * The other settings are what is necessary to get the register
  202. * into a sane state for IDE DMA operation.
  203. */
  204. pci_write_config_byte(master_0, 0x40, 0x1e);
  205. /*
  206. * Set max PCI burst size (16-bytes seems to work best):
  207. * 16bytes: set bit-1 at 0x41 (reg value of 0x16)
  208. * all others: clear bit-1 at 0x41, and do:
  209. * 128bytes: OR 0x00 at 0x41
  210. * 256bytes: OR 0x04 at 0x41
  211. * 512bytes: OR 0x08 at 0x41
  212. * 1024bytes: OR 0x0c at 0x41
  213. */
  214. pci_write_config_byte(master_0, 0x41, 0x14);
  215. /*
  216. * These settings are necessary to get the chip
  217. * into a sane state for IDE DMA operation.
  218. */
  219. pci_write_config_byte(master_0, 0x42, 0x00);
  220. pci_write_config_byte(master_0, 0x43, 0xc1);
  221. pci_dev_put(master_0);
  222. pci_dev_put(cs5530_0);
  223. return 0;
  224. fail_put:
  225. pci_dev_put(master_0);
  226. pci_dev_put(cs5530_0);
  227. return -ENODEV;
  228. }
  229. /**
  230. * cs5530_init_one - Initialise a CS5530
  231. * @dev: PCI device
  232. * @id: Entry in match table
  233. *
  234. * Install a driver for the newly found CS5530 companion chip. Most of
  235. * this is just housekeeping. We have to set the chip up correctly and
  236. * turn off various bits of emulation magic.
  237. */
  238. static int cs5530_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
  239. {
  240. static const struct ata_port_info info = {
  241. .flags = ATA_FLAG_SLAVE_POSS,
  242. .pio_mask = ATA_PIO4,
  243. .mwdma_mask = ATA_MWDMA2,
  244. .udma_mask = ATA_UDMA2,
  245. .port_ops = &cs5530_port_ops
  246. };
  247. /* The docking connector doesn't do UDMA, and it seems not MWDMA */
  248. static const struct ata_port_info info_palmax_secondary = {
  249. .flags = ATA_FLAG_SLAVE_POSS,
  250. .pio_mask = ATA_PIO4,
  251. .port_ops = &cs5530_port_ops
  252. };
  253. const struct ata_port_info *ppi[] = { &info, NULL };
  254. int rc;
  255. rc = pcim_enable_device(pdev);
  256. if (rc)
  257. return rc;
  258. /* Chip initialisation */
  259. if (cs5530_init_chip())
  260. return -ENODEV;
  261. if (cs5530_is_palmax())
  262. ppi[1] = &info_palmax_secondary;
  263. /* Now kick off ATA set up */
  264. return ata_pci_bmdma_init_one(pdev, ppi, &cs5530_sht, NULL, 0);
  265. }
  266. #ifdef CONFIG_PM_SLEEP
  267. static int cs5530_reinit_one(struct pci_dev *pdev)
  268. {
  269. struct ata_host *host = pci_get_drvdata(pdev);
  270. int rc;
  271. rc = ata_pci_device_do_resume(pdev);
  272. if (rc)
  273. return rc;
  274. /* If we fail on resume we are doomed */
  275. if (cs5530_init_chip())
  276. return -EIO;
  277. ata_host_resume(host);
  278. return 0;
  279. }
  280. #endif /* CONFIG_PM_SLEEP */
  281. static const struct pci_device_id cs5530[] = {
  282. { PCI_VDEVICE(CYRIX, PCI_DEVICE_ID_CYRIX_5530_IDE), },
  283. { },
  284. };
  285. static struct pci_driver cs5530_pci_driver = {
  286. .name = DRV_NAME,
  287. .id_table = cs5530,
  288. .probe = cs5530_init_one,
  289. .remove = ata_pci_remove_one,
  290. #ifdef CONFIG_PM_SLEEP
  291. .suspend = ata_pci_device_suspend,
  292. .resume = cs5530_reinit_one,
  293. #endif
  294. };
  295. module_pci_driver(cs5530_pci_driver);
  296. MODULE_AUTHOR("Alan Cox");
  297. MODULE_DESCRIPTION("low-level driver for the Cyrix/NS/AMD 5530");
  298. MODULE_LICENSE("GPL");
  299. MODULE_DEVICE_TABLE(pci, cs5530);
  300. MODULE_VERSION(DRV_VERSION);