pata_cmd64x.c 13 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * pata_cmd64x.c - CMD64x PATA for new ATA layer
  4. * (C) 2005 Red Hat Inc
  5. * Alan Cox <alan@lxorguk.ukuu.org.uk>
  6. * (C) 2009-2010 Bartlomiej Zolnierkiewicz
  7. * (C) 2012 MontaVista Software, LLC <source@mvista.com>
  8. *
  9. * Based upon
  10. * linux/drivers/ide/pci/cmd64x.c Version 1.30 Sept 10, 2002
  11. *
  12. * cmd64x.c: Enable interrupts at initialization time on Ultra/PCI machines.
  13. * Note, this driver is not used at all on other systems because
  14. * there the "BIOS" has done all of the following already.
  15. * Due to massive hardware bugs, UltraDMA is only supported
  16. * on the 646U2 and not on the 646U.
  17. *
  18. * Copyright (C) 1998 Eddie C. Dost (ecd@skynet.be)
  19. * Copyright (C) 1998 David S. Miller (davem@redhat.com)
  20. *
  21. * Copyright (C) 1999-2002 Andre Hedrick <andre@linux-ide.org>
  22. *
  23. * TODO
  24. * Testing work
  25. */
  26. #include <linux/kernel.h>
  27. #include <linux/module.h>
  28. #include <linux/pci.h>
  29. #include <linux/blkdev.h>
  30. #include <linux/delay.h>
  31. #include <scsi/scsi_host.h>
  32. #include <linux/libata.h>
  33. #define DRV_NAME "pata_cmd64x"
  34. #define DRV_VERSION "0.2.18"
  35. /*
  36. * CMD64x specific registers definition.
  37. */
  38. enum {
  39. CFR = 0x50,
  40. CFR_INTR_CH0 = 0x04,
  41. CNTRL = 0x51,
  42. CNTRL_CH0 = 0x04,
  43. CNTRL_CH1 = 0x08,
  44. CMDTIM = 0x52,
  45. ARTTIM0 = 0x53,
  46. DRWTIM0 = 0x54,
  47. ARTTIM1 = 0x55,
  48. DRWTIM1 = 0x56,
  49. ARTTIM23 = 0x57,
  50. ARTTIM23_DIS_RA2 = 0x04,
  51. ARTTIM23_DIS_RA3 = 0x08,
  52. ARTTIM23_INTR_CH1 = 0x10,
  53. DRWTIM2 = 0x58,
  54. BRST = 0x59,
  55. DRWTIM3 = 0x5b,
  56. BMIDECR0 = 0x70,
  57. MRDMODE = 0x71,
  58. MRDMODE_INTR_CH0 = 0x04,
  59. MRDMODE_INTR_CH1 = 0x08,
  60. BMIDESR0 = 0x72,
  61. UDIDETCR0 = 0x73,
  62. DTPR0 = 0x74,
  63. BMIDECR1 = 0x78,
  64. BMIDECSR = 0x79,
  65. UDIDETCR1 = 0x7B,
  66. DTPR1 = 0x7C
  67. };
  68. static int cmd648_cable_detect(struct ata_port *ap)
  69. {
  70. struct pci_dev *pdev = to_pci_dev(ap->host->dev);
  71. u8 r;
  72. /* Check cable detect bits */
  73. pci_read_config_byte(pdev, BMIDECSR, &r);
  74. if (r & (1 << ap->port_no))
  75. return ATA_CBL_PATA80;
  76. return ATA_CBL_PATA40;
  77. }
  78. /**
  79. * cmd64x_set_timing - set PIO and MWDMA timing
  80. * @ap: ATA interface
  81. * @adev: ATA device
  82. * @mode: mode
  83. *
  84. * Called to do the PIO and MWDMA mode setup.
  85. */
  86. static void cmd64x_set_timing(struct ata_port *ap, struct ata_device *adev, u8 mode)
  87. {
  88. struct pci_dev *pdev = to_pci_dev(ap->host->dev);
  89. struct ata_timing t;
  90. const unsigned long T = 1000000 / 33;
  91. const u8 setup_data[] = { 0x40, 0x40, 0x40, 0x80, 0x00 };
  92. u8 reg;
  93. /* Port layout is not logical so use a table */
  94. const u8 arttim_port[2][2] = {
  95. { ARTTIM0, ARTTIM1 },
  96. { ARTTIM23, ARTTIM23 }
  97. };
  98. const u8 drwtim_port[2][2] = {
  99. { DRWTIM0, DRWTIM1 },
  100. { DRWTIM2, DRWTIM3 }
  101. };
  102. int arttim = arttim_port[ap->port_no][adev->devno];
  103. int drwtim = drwtim_port[ap->port_no][adev->devno];
  104. /* ata_timing_compute is smart and will produce timings for MWDMA
  105. that don't violate the drives PIO capabilities. */
  106. if (ata_timing_compute(adev, mode, &t, T, 0) < 0) {
  107. printk(KERN_ERR DRV_NAME ": mode computation failed.\n");
  108. return;
  109. }
  110. if (ap->port_no) {
  111. /* Slave has shared address setup */
  112. struct ata_device *pair = ata_dev_pair(adev);
  113. if (pair) {
  114. struct ata_timing tp;
  115. ata_timing_compute(pair, pair->pio_mode, &tp, T, 0);
  116. ata_timing_merge(&t, &tp, &t, ATA_TIMING_SETUP);
  117. }
  118. }
  119. printk(KERN_DEBUG DRV_NAME ": active %d recovery %d setup %d.\n",
  120. t.active, t.recover, t.setup);
  121. if (t.recover > 16) {
  122. t.active += t.recover - 16;
  123. t.recover = 16;
  124. }
  125. if (t.active > 16)
  126. t.active = 16;
  127. /* Now convert the clocks into values we can actually stuff into
  128. the chip */
  129. if (t.recover == 16)
  130. t.recover = 0;
  131. else if (t.recover > 1)
  132. t.recover--;
  133. else
  134. t.recover = 15;
  135. if (t.setup > 4)
  136. t.setup = 0xC0;
  137. else
  138. t.setup = setup_data[t.setup];
  139. t.active &= 0x0F; /* 0 = 16 */
  140. /* Load setup timing */
  141. pci_read_config_byte(pdev, arttim, &reg);
  142. reg &= 0x3F;
  143. reg |= t.setup;
  144. pci_write_config_byte(pdev, arttim, reg);
  145. /* Load active/recovery */
  146. pci_write_config_byte(pdev, drwtim, (t.active << 4) | t.recover);
  147. }
  148. /**
  149. * cmd64x_set_piomode - set initial PIO mode data
  150. * @ap: ATA interface
  151. * @adev: ATA device
  152. *
  153. * Used when configuring the devices ot set the PIO timings. All the
  154. * actual work is done by the PIO/MWDMA setting helper
  155. */
  156. static void cmd64x_set_piomode(struct ata_port *ap, struct ata_device *adev)
  157. {
  158. cmd64x_set_timing(ap, adev, adev->pio_mode);
  159. }
  160. /**
  161. * cmd64x_set_dmamode - set initial DMA mode data
  162. * @ap: ATA interface
  163. * @adev: ATA device
  164. *
  165. * Called to do the DMA mode setup.
  166. */
  167. static void cmd64x_set_dmamode(struct ata_port *ap, struct ata_device *adev)
  168. {
  169. static const u8 udma_data[] = {
  170. 0x30, 0x20, 0x10, 0x20, 0x10, 0x00
  171. };
  172. struct pci_dev *pdev = to_pci_dev(ap->host->dev);
  173. u8 regU, regD;
  174. int pciU = UDIDETCR0 + 8 * ap->port_no;
  175. int pciD = BMIDESR0 + 8 * ap->port_no;
  176. int shift = 2 * adev->devno;
  177. pci_read_config_byte(pdev, pciD, &regD);
  178. pci_read_config_byte(pdev, pciU, &regU);
  179. /* DMA bits off */
  180. regD &= ~(0x20 << adev->devno);
  181. /* DMA control bits */
  182. regU &= ~(0x30 << shift);
  183. /* DMA timing bits */
  184. regU &= ~(0x05 << adev->devno);
  185. if (adev->dma_mode >= XFER_UDMA_0) {
  186. /* Merge the timing value */
  187. regU |= udma_data[adev->dma_mode - XFER_UDMA_0] << shift;
  188. /* Merge the control bits */
  189. regU |= 1 << adev->devno; /* UDMA on */
  190. if (adev->dma_mode > XFER_UDMA_2) /* 15nS timing */
  191. regU |= 4 << adev->devno;
  192. } else {
  193. regU &= ~ (1 << adev->devno); /* UDMA off */
  194. cmd64x_set_timing(ap, adev, adev->dma_mode);
  195. }
  196. regD |= 0x20 << adev->devno;
  197. pci_write_config_byte(pdev, pciU, regU);
  198. pci_write_config_byte(pdev, pciD, regD);
  199. }
  200. /**
  201. * cmd64x_sff_irq_check - check IDE interrupt
  202. * @ap: ATA interface
  203. *
  204. * Check IDE interrupt in CFR/ARTTIM23 registers.
  205. */
  206. static bool cmd64x_sff_irq_check(struct ata_port *ap)
  207. {
  208. struct pci_dev *pdev = to_pci_dev(ap->host->dev);
  209. int irq_mask = ap->port_no ? ARTTIM23_INTR_CH1 : CFR_INTR_CH0;
  210. int irq_reg = ap->port_no ? ARTTIM23 : CFR;
  211. u8 irq_stat;
  212. /* NOTE: reading the register should clear the interrupt */
  213. pci_read_config_byte(pdev, irq_reg, &irq_stat);
  214. return irq_stat & irq_mask;
  215. }
  216. /**
  217. * cmd64x_sff_irq_clear - clear IDE interrupt
  218. * @ap: ATA interface
  219. *
  220. * Clear IDE interrupt in CFR/ARTTIM23 and DMA status registers.
  221. */
  222. static void cmd64x_sff_irq_clear(struct ata_port *ap)
  223. {
  224. struct pci_dev *pdev = to_pci_dev(ap->host->dev);
  225. int irq_reg = ap->port_no ? ARTTIM23 : CFR;
  226. u8 irq_stat;
  227. ata_bmdma_irq_clear(ap);
  228. /* Reading the register should be enough to clear the interrupt */
  229. pci_read_config_byte(pdev, irq_reg, &irq_stat);
  230. }
  231. /**
  232. * cmd648_sff_irq_check - check IDE interrupt
  233. * @ap: ATA interface
  234. *
  235. * Check IDE interrupt in MRDMODE register.
  236. */
  237. static bool cmd648_sff_irq_check(struct ata_port *ap)
  238. {
  239. struct pci_dev *pdev = to_pci_dev(ap->host->dev);
  240. unsigned long base = pci_resource_start(pdev, 4);
  241. int irq_mask = ap->port_no ? MRDMODE_INTR_CH1 : MRDMODE_INTR_CH0;
  242. u8 mrdmode = inb(base + 1);
  243. return mrdmode & irq_mask;
  244. }
  245. /**
  246. * cmd648_sff_irq_clear - clear IDE interrupt
  247. * @ap: ATA interface
  248. *
  249. * Clear IDE interrupt in MRDMODE and DMA status registers.
  250. */
  251. static void cmd648_sff_irq_clear(struct ata_port *ap)
  252. {
  253. struct pci_dev *pdev = to_pci_dev(ap->host->dev);
  254. unsigned long base = pci_resource_start(pdev, 4);
  255. int irq_mask = ap->port_no ? MRDMODE_INTR_CH1 : MRDMODE_INTR_CH0;
  256. u8 mrdmode;
  257. ata_bmdma_irq_clear(ap);
  258. /* Clear this port's interrupt bit (leaving the other port alone) */
  259. mrdmode = inb(base + 1);
  260. mrdmode &= ~(MRDMODE_INTR_CH0 | MRDMODE_INTR_CH1);
  261. outb(mrdmode | irq_mask, base + 1);
  262. }
  263. /**
  264. * cmd646r1_bmdma_stop - DMA stop callback
  265. * @qc: Command in progress
  266. *
  267. * Stub for now while investigating the r1 quirk in the old driver.
  268. */
  269. static void cmd646r1_bmdma_stop(struct ata_queued_cmd *qc)
  270. {
  271. ata_bmdma_stop(qc);
  272. }
  273. static struct scsi_host_template cmd64x_sht = {
  274. ATA_BMDMA_SHT(DRV_NAME),
  275. };
  276. static const struct ata_port_operations cmd64x_base_ops = {
  277. .inherits = &ata_bmdma_port_ops,
  278. .set_piomode = cmd64x_set_piomode,
  279. .set_dmamode = cmd64x_set_dmamode,
  280. };
  281. static struct ata_port_operations cmd64x_port_ops = {
  282. .inherits = &cmd64x_base_ops,
  283. .sff_irq_check = cmd64x_sff_irq_check,
  284. .sff_irq_clear = cmd64x_sff_irq_clear,
  285. .cable_detect = ata_cable_40wire,
  286. };
  287. static struct ata_port_operations cmd646r1_port_ops = {
  288. .inherits = &cmd64x_base_ops,
  289. .sff_irq_check = cmd64x_sff_irq_check,
  290. .sff_irq_clear = cmd64x_sff_irq_clear,
  291. .bmdma_stop = cmd646r1_bmdma_stop,
  292. .cable_detect = ata_cable_40wire,
  293. };
  294. static struct ata_port_operations cmd646r3_port_ops = {
  295. .inherits = &cmd64x_base_ops,
  296. .sff_irq_check = cmd648_sff_irq_check,
  297. .sff_irq_clear = cmd648_sff_irq_clear,
  298. .cable_detect = ata_cable_40wire,
  299. };
  300. static struct ata_port_operations cmd648_port_ops = {
  301. .inherits = &cmd64x_base_ops,
  302. .sff_irq_check = cmd648_sff_irq_check,
  303. .sff_irq_clear = cmd648_sff_irq_clear,
  304. .cable_detect = cmd648_cable_detect,
  305. };
  306. static void cmd64x_fixup(struct pci_dev *pdev)
  307. {
  308. u8 mrdmode;
  309. pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 64);
  310. pci_read_config_byte(pdev, MRDMODE, &mrdmode);
  311. mrdmode &= ~0x30; /* IRQ set up */
  312. mrdmode |= 0x02; /* Memory read line enable */
  313. pci_write_config_byte(pdev, MRDMODE, mrdmode);
  314. /* PPC specific fixup copied from old driver */
  315. #ifdef CONFIG_PPC
  316. pci_write_config_byte(pdev, UDIDETCR0, 0xF0);
  317. #endif
  318. }
  319. static int cmd64x_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
  320. {
  321. static const struct ata_port_info cmd_info[7] = {
  322. { /* CMD 643 - no UDMA */
  323. .flags = ATA_FLAG_SLAVE_POSS,
  324. .pio_mask = ATA_PIO4,
  325. .mwdma_mask = ATA_MWDMA2,
  326. .port_ops = &cmd64x_port_ops
  327. },
  328. { /* CMD 646 with broken UDMA */
  329. .flags = ATA_FLAG_SLAVE_POSS,
  330. .pio_mask = ATA_PIO4,
  331. .mwdma_mask = ATA_MWDMA2,
  332. .port_ops = &cmd64x_port_ops
  333. },
  334. { /* CMD 646U with broken UDMA */
  335. .flags = ATA_FLAG_SLAVE_POSS,
  336. .pio_mask = ATA_PIO4,
  337. .mwdma_mask = ATA_MWDMA2,
  338. .port_ops = &cmd646r3_port_ops
  339. },
  340. { /* CMD 646U2 with working UDMA */
  341. .flags = ATA_FLAG_SLAVE_POSS,
  342. .pio_mask = ATA_PIO4,
  343. .mwdma_mask = ATA_MWDMA2,
  344. .udma_mask = ATA_UDMA2,
  345. .port_ops = &cmd646r3_port_ops
  346. },
  347. { /* CMD 646 rev 1 */
  348. .flags = ATA_FLAG_SLAVE_POSS,
  349. .pio_mask = ATA_PIO4,
  350. .mwdma_mask = ATA_MWDMA2,
  351. .port_ops = &cmd646r1_port_ops
  352. },
  353. { /* CMD 648 */
  354. .flags = ATA_FLAG_SLAVE_POSS,
  355. .pio_mask = ATA_PIO4,
  356. .mwdma_mask = ATA_MWDMA2,
  357. .udma_mask = ATA_UDMA4,
  358. .port_ops = &cmd648_port_ops
  359. },
  360. { /* CMD 649 */
  361. .flags = ATA_FLAG_SLAVE_POSS,
  362. .pio_mask = ATA_PIO4,
  363. .mwdma_mask = ATA_MWDMA2,
  364. .udma_mask = ATA_UDMA5,
  365. .port_ops = &cmd648_port_ops
  366. }
  367. };
  368. const struct ata_port_info *ppi[] = {
  369. &cmd_info[id->driver_data],
  370. &cmd_info[id->driver_data],
  371. NULL
  372. };
  373. u8 reg;
  374. int rc;
  375. struct pci_dev *bridge = pdev->bus->self;
  376. /* mobility split bridges don't report enabled ports correctly */
  377. int port_ok = !(bridge && bridge->vendor ==
  378. PCI_VENDOR_ID_MOBILITY_ELECTRONICS);
  379. /* all (with exceptions below) apart from 643 have CNTRL_CH0 bit */
  380. int cntrl_ch0_ok = (id->driver_data != 0);
  381. rc = pcim_enable_device(pdev);
  382. if (rc)
  383. return rc;
  384. if (id->driver_data == 0) /* 643 */
  385. ata_pci_bmdma_clear_simplex(pdev);
  386. if (pdev->device == PCI_DEVICE_ID_CMD_646)
  387. switch (pdev->revision) {
  388. /* UDMA works since rev 5 */
  389. default:
  390. ppi[0] = &cmd_info[3];
  391. ppi[1] = &cmd_info[3];
  392. break;
  393. /* Interrupts in MRDMODE since rev 3 */
  394. case 3:
  395. case 4:
  396. ppi[0] = &cmd_info[2];
  397. ppi[1] = &cmd_info[2];
  398. break;
  399. /* Rev 1 with other problems? */
  400. case 1:
  401. ppi[0] = &cmd_info[4];
  402. ppi[1] = &cmd_info[4];
  403. fallthrough;
  404. /* Early revs have no CNTRL_CH0 */
  405. case 2:
  406. case 0:
  407. cntrl_ch0_ok = 0;
  408. break;
  409. }
  410. cmd64x_fixup(pdev);
  411. /* check for enabled ports */
  412. pci_read_config_byte(pdev, CNTRL, &reg);
  413. if (!port_ok)
  414. dev_notice(&pdev->dev, "Mobility Bridge detected, ignoring CNTRL port enable/disable\n");
  415. if (port_ok && cntrl_ch0_ok && !(reg & CNTRL_CH0)) {
  416. dev_notice(&pdev->dev, "Primary port is disabled\n");
  417. ppi[0] = &ata_dummy_port_info;
  418. }
  419. if (port_ok && !(reg & CNTRL_CH1)) {
  420. dev_notice(&pdev->dev, "Secondary port is disabled\n");
  421. ppi[1] = &ata_dummy_port_info;
  422. }
  423. return ata_pci_bmdma_init_one(pdev, ppi, &cmd64x_sht, NULL, 0);
  424. }
  425. #ifdef CONFIG_PM_SLEEP
  426. static int cmd64x_reinit_one(struct pci_dev *pdev)
  427. {
  428. struct ata_host *host = pci_get_drvdata(pdev);
  429. int rc;
  430. rc = ata_pci_device_do_resume(pdev);
  431. if (rc)
  432. return rc;
  433. cmd64x_fixup(pdev);
  434. ata_host_resume(host);
  435. return 0;
  436. }
  437. #endif
  438. static const struct pci_device_id cmd64x[] = {
  439. { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_643), 0 },
  440. { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_646), 1 },
  441. { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_648), 5 },
  442. { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_649), 6 },
  443. { },
  444. };
  445. static struct pci_driver cmd64x_pci_driver = {
  446. .name = DRV_NAME,
  447. .id_table = cmd64x,
  448. .probe = cmd64x_init_one,
  449. .remove = ata_pci_remove_one,
  450. #ifdef CONFIG_PM_SLEEP
  451. .suspend = ata_pci_device_suspend,
  452. .resume = cmd64x_reinit_one,
  453. #endif
  454. };
  455. module_pci_driver(cmd64x_pci_driver);
  456. MODULE_AUTHOR("Alan Cox");
  457. MODULE_DESCRIPTION("low-level driver for CMD64x series PATA controllers");
  458. MODULE_LICENSE("GPL");
  459. MODULE_DEVICE_TABLE(pci, cmd64x);
  460. MODULE_VERSION(DRV_VERSION);