pata_amd.c 17 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * pata_amd.c - AMD PATA for new ATA layer
  4. * (C) 2005-2006 Red Hat Inc
  5. *
  6. * Based on pata-sil680. Errata information is taken from data sheets
  7. * and the amd74xx.c driver by Vojtech Pavlik. Nvidia SATA devices are
  8. * claimed by sata-nv.c.
  9. *
  10. * TODO:
  11. * Variable system clock when/if it makes sense
  12. * Power management on ports
  13. *
  14. *
  15. * Documentation publicly available.
  16. */
  17. #include <linux/kernel.h>
  18. #include <linux/module.h>
  19. #include <linux/pci.h>
  20. #include <linux/blkdev.h>
  21. #include <linux/delay.h>
  22. #include <scsi/scsi_host.h>
  23. #include <linux/libata.h>
  24. #define DRV_NAME "pata_amd"
  25. #define DRV_VERSION "0.4.1"
  26. /**
  27. * timing_setup - shared timing computation and load
  28. * @ap: ATA port being set up
  29. * @adev: drive being configured
  30. * @offset: port offset
  31. * @speed: target speed
  32. * @clock: clock multiplier (number of times 33MHz for this part)
  33. *
  34. * Perform the actual timing set up for Nvidia or AMD PATA devices.
  35. * The actual devices vary so they all call into this helper function
  36. * providing the clock multipler and offset (because AMD and Nvidia put
  37. * the ports at different locations).
  38. */
  39. static void timing_setup(struct ata_port *ap, struct ata_device *adev, int offset, int speed, int clock)
  40. {
  41. static const unsigned char amd_cyc2udma[] = {
  42. 6, 6, 5, 4, 0, 1, 1, 2, 2, 3, 3, 3, 3, 3, 3, 7
  43. };
  44. struct pci_dev *pdev = to_pci_dev(ap->host->dev);
  45. struct ata_device *peer = ata_dev_pair(adev);
  46. int dn = ap->port_no * 2 + adev->devno;
  47. struct ata_timing at, apeer;
  48. int T, UT;
  49. const int amd_clock = 33333; /* KHz. */
  50. u8 t;
  51. T = 1000000000 / amd_clock;
  52. UT = T;
  53. if (clock >= 2)
  54. UT = T / 2;
  55. if (ata_timing_compute(adev, speed, &at, T, UT) < 0) {
  56. dev_err(&pdev->dev, "unknown mode %d\n", speed);
  57. return;
  58. }
  59. if (peer) {
  60. /* This may be over conservative */
  61. if (peer->dma_mode) {
  62. ata_timing_compute(peer, peer->dma_mode, &apeer, T, UT);
  63. ata_timing_merge(&apeer, &at, &at, ATA_TIMING_8BIT);
  64. }
  65. ata_timing_compute(peer, peer->pio_mode, &apeer, T, UT);
  66. ata_timing_merge(&apeer, &at, &at, ATA_TIMING_8BIT);
  67. }
  68. if (speed == XFER_UDMA_5 && amd_clock <= 33333) at.udma = 1;
  69. if (speed == XFER_UDMA_6 && amd_clock <= 33333) at.udma = 15;
  70. /*
  71. * Now do the setup work
  72. */
  73. /* Configure the address set up timing */
  74. pci_read_config_byte(pdev, offset + 0x0C, &t);
  75. t = (t & ~(3 << ((3 - dn) << 1))) | ((clamp_val(at.setup, 1, 4) - 1) << ((3 - dn) << 1));
  76. pci_write_config_byte(pdev, offset + 0x0C , t);
  77. /* Configure the 8bit I/O timing */
  78. pci_write_config_byte(pdev, offset + 0x0E + (1 - (dn >> 1)),
  79. ((clamp_val(at.act8b, 1, 16) - 1) << 4) | (clamp_val(at.rec8b, 1, 16) - 1));
  80. /* Drive timing */
  81. pci_write_config_byte(pdev, offset + 0x08 + (3 - dn),
  82. ((clamp_val(at.active, 1, 16) - 1) << 4) | (clamp_val(at.recover, 1, 16) - 1));
  83. switch (clock) {
  84. case 1:
  85. t = at.udma ? (0xc0 | (clamp_val(at.udma, 2, 5) - 2)) : 0x03;
  86. break;
  87. case 2:
  88. t = at.udma ? (0xc0 | amd_cyc2udma[clamp_val(at.udma, 2, 10)]) : 0x03;
  89. break;
  90. case 3:
  91. t = at.udma ? (0xc0 | amd_cyc2udma[clamp_val(at.udma, 1, 10)]) : 0x03;
  92. break;
  93. case 4:
  94. t = at.udma ? (0xc0 | amd_cyc2udma[clamp_val(at.udma, 1, 15)]) : 0x03;
  95. break;
  96. default:
  97. return;
  98. }
  99. /* UDMA timing */
  100. if (at.udma)
  101. pci_write_config_byte(pdev, offset + 0x10 + (3 - dn), t);
  102. }
  103. /**
  104. * amd_pre_reset - perform reset handling
  105. * @link: ATA link
  106. * @deadline: deadline jiffies for the operation
  107. *
  108. * Reset sequence checking enable bits to see which ports are
  109. * active.
  110. */
  111. static int amd_pre_reset(struct ata_link *link, unsigned long deadline)
  112. {
  113. static const struct pci_bits amd_enable_bits[] = {
  114. { 0x40, 1, 0x02, 0x02 },
  115. { 0x40, 1, 0x01, 0x01 }
  116. };
  117. struct ata_port *ap = link->ap;
  118. struct pci_dev *pdev = to_pci_dev(ap->host->dev);
  119. if (!pci_test_config_bits(pdev, &amd_enable_bits[ap->port_no]))
  120. return -ENOENT;
  121. return ata_sff_prereset(link, deadline);
  122. }
  123. /**
  124. * amd_cable_detect - report cable type
  125. * @ap: port
  126. *
  127. * AMD controller/BIOS setups record the cable type in word 0x42
  128. */
  129. static int amd_cable_detect(struct ata_port *ap)
  130. {
  131. static const u32 bitmask[2] = {0x03, 0x0C};
  132. struct pci_dev *pdev = to_pci_dev(ap->host->dev);
  133. u8 ata66;
  134. pci_read_config_byte(pdev, 0x42, &ata66);
  135. if (ata66 & bitmask[ap->port_no])
  136. return ATA_CBL_PATA80;
  137. return ATA_CBL_PATA40;
  138. }
  139. /**
  140. * amd_fifo_setup - set the PIO FIFO for ATA/ATAPI
  141. * @ap: ATA interface
  142. * @adev: ATA device
  143. *
  144. * Set the PCI fifo for this device according to the devices present
  145. * on the bus at this point in time. We need to turn the post write buffer
  146. * off for ATAPI devices as we may need to issue a word sized write to the
  147. * device as the final I/O
  148. */
  149. static void amd_fifo_setup(struct ata_port *ap)
  150. {
  151. struct ata_device *adev;
  152. struct pci_dev *pdev = to_pci_dev(ap->host->dev);
  153. static const u8 fifobit[2] = { 0xC0, 0x30};
  154. u8 fifo = fifobit[ap->port_no];
  155. u8 r;
  156. ata_for_each_dev(adev, &ap->link, ENABLED) {
  157. if (adev->class == ATA_DEV_ATAPI)
  158. fifo = 0;
  159. }
  160. if (pdev->device == PCI_DEVICE_ID_AMD_VIPER_7411) /* FIFO is broken */
  161. fifo = 0;
  162. /* On the later chips the read prefetch bits become no-op bits */
  163. pci_read_config_byte(pdev, 0x41, &r);
  164. r &= ~fifobit[ap->port_no];
  165. r |= fifo;
  166. pci_write_config_byte(pdev, 0x41, r);
  167. }
  168. /**
  169. * amd33_set_piomode - set initial PIO mode data
  170. * @ap: ATA interface
  171. * @adev: ATA device
  172. *
  173. * Program the AMD registers for PIO mode.
  174. */
  175. static void amd33_set_piomode(struct ata_port *ap, struct ata_device *adev)
  176. {
  177. amd_fifo_setup(ap);
  178. timing_setup(ap, adev, 0x40, adev->pio_mode, 1);
  179. }
  180. static void amd66_set_piomode(struct ata_port *ap, struct ata_device *adev)
  181. {
  182. amd_fifo_setup(ap);
  183. timing_setup(ap, adev, 0x40, adev->pio_mode, 2);
  184. }
  185. static void amd100_set_piomode(struct ata_port *ap, struct ata_device *adev)
  186. {
  187. amd_fifo_setup(ap);
  188. timing_setup(ap, adev, 0x40, adev->pio_mode, 3);
  189. }
  190. static void amd133_set_piomode(struct ata_port *ap, struct ata_device *adev)
  191. {
  192. amd_fifo_setup(ap);
  193. timing_setup(ap, adev, 0x40, adev->pio_mode, 4);
  194. }
  195. /**
  196. * amd33_set_dmamode - set initial DMA mode data
  197. * @ap: ATA interface
  198. * @adev: ATA device
  199. *
  200. * Program the MWDMA/UDMA modes for the AMD and Nvidia
  201. * chipset.
  202. */
  203. static void amd33_set_dmamode(struct ata_port *ap, struct ata_device *adev)
  204. {
  205. timing_setup(ap, adev, 0x40, adev->dma_mode, 1);
  206. }
  207. static void amd66_set_dmamode(struct ata_port *ap, struct ata_device *adev)
  208. {
  209. timing_setup(ap, adev, 0x40, adev->dma_mode, 2);
  210. }
  211. static void amd100_set_dmamode(struct ata_port *ap, struct ata_device *adev)
  212. {
  213. timing_setup(ap, adev, 0x40, adev->dma_mode, 3);
  214. }
  215. static void amd133_set_dmamode(struct ata_port *ap, struct ata_device *adev)
  216. {
  217. timing_setup(ap, adev, 0x40, adev->dma_mode, 4);
  218. }
  219. /* Both host-side and drive-side detection results are worthless on NV
  220. * PATAs. Ignore them and just follow what BIOS configured. Both the
  221. * current configuration in PCI config reg and ACPI GTM result are
  222. * cached during driver attach and are consulted to select transfer
  223. * mode.
  224. */
  225. static unsigned long nv_mode_filter(struct ata_device *dev,
  226. unsigned long xfer_mask)
  227. {
  228. static const unsigned int udma_mask_map[] =
  229. { ATA_UDMA2, ATA_UDMA1, ATA_UDMA0, 0,
  230. ATA_UDMA3, ATA_UDMA4, ATA_UDMA5, ATA_UDMA6 };
  231. struct ata_port *ap = dev->link->ap;
  232. char acpi_str[32] = "";
  233. u32 saved_udma, udma;
  234. const struct ata_acpi_gtm *gtm;
  235. unsigned long bios_limit = 0, acpi_limit = 0, limit;
  236. /* find out what BIOS configured */
  237. udma = saved_udma = (unsigned long)ap->host->private_data;
  238. if (ap->port_no == 0)
  239. udma >>= 16;
  240. if (dev->devno == 0)
  241. udma >>= 8;
  242. if ((udma & 0xc0) == 0xc0)
  243. bios_limit = ata_pack_xfermask(0, 0, udma_mask_map[udma & 0x7]);
  244. /* consult ACPI GTM too */
  245. gtm = ata_acpi_init_gtm(ap);
  246. if (gtm) {
  247. acpi_limit = ata_acpi_gtm_xfermask(dev, gtm);
  248. snprintf(acpi_str, sizeof(acpi_str), " (%u:%u:0x%x)",
  249. gtm->drive[0].dma, gtm->drive[1].dma, gtm->flags);
  250. }
  251. /* be optimistic, EH can take care of things if something goes wrong */
  252. limit = bios_limit | acpi_limit;
  253. /* If PIO or DMA isn't configured at all, don't limit. Let EH
  254. * handle it.
  255. */
  256. if (!(limit & ATA_MASK_PIO))
  257. limit |= ATA_MASK_PIO;
  258. if (!(limit & (ATA_MASK_MWDMA | ATA_MASK_UDMA)))
  259. limit |= ATA_MASK_MWDMA | ATA_MASK_UDMA;
  260. /* PIO4, MWDMA2, UDMA2 should always be supported regardless of
  261. cable detection result */
  262. limit |= ata_pack_xfermask(ATA_PIO4, ATA_MWDMA2, ATA_UDMA2);
  263. ata_port_dbg(ap, "nv_mode_filter: 0x%lx&0x%lx->0x%lx, "
  264. "BIOS=0x%lx (0x%x) ACPI=0x%lx%s\n",
  265. xfer_mask, limit, xfer_mask & limit, bios_limit,
  266. saved_udma, acpi_limit, acpi_str);
  267. return xfer_mask & limit;
  268. }
  269. /**
  270. * nv_probe_init - cable detection
  271. * @lin: ATA link
  272. *
  273. * Perform cable detection. The BIOS stores this in PCI config
  274. * space for us.
  275. */
  276. static int nv_pre_reset(struct ata_link *link, unsigned long deadline)
  277. {
  278. static const struct pci_bits nv_enable_bits[] = {
  279. { 0x50, 1, 0x02, 0x02 },
  280. { 0x50, 1, 0x01, 0x01 }
  281. };
  282. struct ata_port *ap = link->ap;
  283. struct pci_dev *pdev = to_pci_dev(ap->host->dev);
  284. if (!pci_test_config_bits(pdev, &nv_enable_bits[ap->port_no]))
  285. return -ENOENT;
  286. return ata_sff_prereset(link, deadline);
  287. }
  288. /**
  289. * nv100_set_piomode - set initial PIO mode data
  290. * @ap: ATA interface
  291. * @adev: ATA device
  292. *
  293. * Program the AMD registers for PIO mode.
  294. */
  295. static void nv100_set_piomode(struct ata_port *ap, struct ata_device *adev)
  296. {
  297. timing_setup(ap, adev, 0x50, adev->pio_mode, 3);
  298. }
  299. static void nv133_set_piomode(struct ata_port *ap, struct ata_device *adev)
  300. {
  301. timing_setup(ap, adev, 0x50, adev->pio_mode, 4);
  302. }
  303. /**
  304. * nv100_set_dmamode - set initial DMA mode data
  305. * @ap: ATA interface
  306. * @adev: ATA device
  307. *
  308. * Program the MWDMA/UDMA modes for the AMD and Nvidia
  309. * chipset.
  310. */
  311. static void nv100_set_dmamode(struct ata_port *ap, struct ata_device *adev)
  312. {
  313. timing_setup(ap, adev, 0x50, adev->dma_mode, 3);
  314. }
  315. static void nv133_set_dmamode(struct ata_port *ap, struct ata_device *adev)
  316. {
  317. timing_setup(ap, adev, 0x50, adev->dma_mode, 4);
  318. }
  319. static void nv_host_stop(struct ata_host *host)
  320. {
  321. u32 udma = (unsigned long)host->private_data;
  322. /* restore PCI config register 0x60 */
  323. pci_write_config_dword(to_pci_dev(host->dev), 0x60, udma);
  324. }
  325. static struct scsi_host_template amd_sht = {
  326. ATA_BMDMA_SHT(DRV_NAME),
  327. };
  328. static const struct ata_port_operations amd_base_port_ops = {
  329. .inherits = &ata_bmdma32_port_ops,
  330. .prereset = amd_pre_reset,
  331. };
  332. static struct ata_port_operations amd33_port_ops = {
  333. .inherits = &amd_base_port_ops,
  334. .cable_detect = ata_cable_40wire,
  335. .set_piomode = amd33_set_piomode,
  336. .set_dmamode = amd33_set_dmamode,
  337. };
  338. static struct ata_port_operations amd66_port_ops = {
  339. .inherits = &amd_base_port_ops,
  340. .cable_detect = ata_cable_unknown,
  341. .set_piomode = amd66_set_piomode,
  342. .set_dmamode = amd66_set_dmamode,
  343. };
  344. static struct ata_port_operations amd100_port_ops = {
  345. .inherits = &amd_base_port_ops,
  346. .cable_detect = ata_cable_unknown,
  347. .set_piomode = amd100_set_piomode,
  348. .set_dmamode = amd100_set_dmamode,
  349. };
  350. static struct ata_port_operations amd133_port_ops = {
  351. .inherits = &amd_base_port_ops,
  352. .cable_detect = amd_cable_detect,
  353. .set_piomode = amd133_set_piomode,
  354. .set_dmamode = amd133_set_dmamode,
  355. };
  356. static const struct ata_port_operations nv_base_port_ops = {
  357. .inherits = &ata_bmdma_port_ops,
  358. .cable_detect = ata_cable_ignore,
  359. .mode_filter = nv_mode_filter,
  360. .prereset = nv_pre_reset,
  361. .host_stop = nv_host_stop,
  362. };
  363. static struct ata_port_operations nv100_port_ops = {
  364. .inherits = &nv_base_port_ops,
  365. .set_piomode = nv100_set_piomode,
  366. .set_dmamode = nv100_set_dmamode,
  367. };
  368. static struct ata_port_operations nv133_port_ops = {
  369. .inherits = &nv_base_port_ops,
  370. .set_piomode = nv133_set_piomode,
  371. .set_dmamode = nv133_set_dmamode,
  372. };
  373. static void amd_clear_fifo(struct pci_dev *pdev)
  374. {
  375. u8 fifo;
  376. /* Disable the FIFO, the FIFO logic will re-enable it as
  377. appropriate */
  378. pci_read_config_byte(pdev, 0x41, &fifo);
  379. fifo &= 0x0F;
  380. pci_write_config_byte(pdev, 0x41, fifo);
  381. }
  382. static int amd_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
  383. {
  384. static const struct ata_port_info info[10] = {
  385. { /* 0: AMD 7401 - no swdma */
  386. .flags = ATA_FLAG_SLAVE_POSS,
  387. .pio_mask = ATA_PIO4,
  388. .mwdma_mask = ATA_MWDMA2,
  389. .udma_mask = ATA_UDMA2,
  390. .port_ops = &amd33_port_ops
  391. },
  392. { /* 1: Early AMD7409 - no swdma */
  393. .flags = ATA_FLAG_SLAVE_POSS,
  394. .pio_mask = ATA_PIO4,
  395. .mwdma_mask = ATA_MWDMA2,
  396. .udma_mask = ATA_UDMA4,
  397. .port_ops = &amd66_port_ops
  398. },
  399. { /* 2: AMD 7409 */
  400. .flags = ATA_FLAG_SLAVE_POSS,
  401. .pio_mask = ATA_PIO4,
  402. .mwdma_mask = ATA_MWDMA2,
  403. .udma_mask = ATA_UDMA4,
  404. .port_ops = &amd66_port_ops
  405. },
  406. { /* 3: AMD 7411 */
  407. .flags = ATA_FLAG_SLAVE_POSS,
  408. .pio_mask = ATA_PIO4,
  409. .mwdma_mask = ATA_MWDMA2,
  410. .udma_mask = ATA_UDMA5,
  411. .port_ops = &amd100_port_ops
  412. },
  413. { /* 4: AMD 7441 */
  414. .flags = ATA_FLAG_SLAVE_POSS,
  415. .pio_mask = ATA_PIO4,
  416. .mwdma_mask = ATA_MWDMA2,
  417. .udma_mask = ATA_UDMA5,
  418. .port_ops = &amd100_port_ops
  419. },
  420. { /* 5: AMD 8111 - no swdma */
  421. .flags = ATA_FLAG_SLAVE_POSS,
  422. .pio_mask = ATA_PIO4,
  423. .mwdma_mask = ATA_MWDMA2,
  424. .udma_mask = ATA_UDMA6,
  425. .port_ops = &amd133_port_ops
  426. },
  427. { /* 6: AMD 8111 UDMA 100 (Serenade) - no swdma */
  428. .flags = ATA_FLAG_SLAVE_POSS,
  429. .pio_mask = ATA_PIO4,
  430. .mwdma_mask = ATA_MWDMA2,
  431. .udma_mask = ATA_UDMA5,
  432. .port_ops = &amd133_port_ops
  433. },
  434. { /* 7: Nvidia Nforce */
  435. .flags = ATA_FLAG_SLAVE_POSS,
  436. .pio_mask = ATA_PIO4,
  437. .mwdma_mask = ATA_MWDMA2,
  438. .udma_mask = ATA_UDMA5,
  439. .port_ops = &nv100_port_ops
  440. },
  441. { /* 8: Nvidia Nforce2 and later - no swdma */
  442. .flags = ATA_FLAG_SLAVE_POSS,
  443. .pio_mask = ATA_PIO4,
  444. .mwdma_mask = ATA_MWDMA2,
  445. .udma_mask = ATA_UDMA6,
  446. .port_ops = &nv133_port_ops
  447. },
  448. { /* 9: AMD CS5536 (Geode companion) */
  449. .flags = ATA_FLAG_SLAVE_POSS,
  450. .pio_mask = ATA_PIO4,
  451. .mwdma_mask = ATA_MWDMA2,
  452. .udma_mask = ATA_UDMA5,
  453. .port_ops = &amd100_port_ops
  454. }
  455. };
  456. const struct ata_port_info *ppi[] = { NULL, NULL };
  457. int type = id->driver_data;
  458. void *hpriv = NULL;
  459. u8 fifo;
  460. int rc;
  461. ata_print_version_once(&pdev->dev, DRV_VERSION);
  462. rc = pcim_enable_device(pdev);
  463. if (rc)
  464. return rc;
  465. pci_read_config_byte(pdev, 0x41, &fifo);
  466. /* Check for AMD7409 without swdma errata and if found adjust type */
  467. if (type == 1 && pdev->revision > 0x7)
  468. type = 2;
  469. /* Serenade ? */
  470. if (type == 5 && pdev->subsystem_vendor == PCI_VENDOR_ID_AMD &&
  471. pdev->subsystem_device == PCI_DEVICE_ID_AMD_SERENADE)
  472. type = 6; /* UDMA 100 only */
  473. /*
  474. * Okay, type is determined now. Apply type-specific workarounds.
  475. */
  476. ppi[0] = &info[type];
  477. if (type < 3)
  478. ata_pci_bmdma_clear_simplex(pdev);
  479. if (pdev->vendor == PCI_VENDOR_ID_AMD)
  480. amd_clear_fifo(pdev);
  481. /* Cable detection on Nvidia chips doesn't work too well,
  482. * cache BIOS programmed UDMA mode.
  483. */
  484. if (type == 7 || type == 8) {
  485. u32 udma;
  486. pci_read_config_dword(pdev, 0x60, &udma);
  487. hpriv = (void *)(unsigned long)udma;
  488. }
  489. /* And fire it up */
  490. return ata_pci_bmdma_init_one(pdev, ppi, &amd_sht, hpriv, 0);
  491. }
  492. #ifdef CONFIG_PM_SLEEP
  493. static int amd_reinit_one(struct pci_dev *pdev)
  494. {
  495. struct ata_host *host = pci_get_drvdata(pdev);
  496. int rc;
  497. rc = ata_pci_device_do_resume(pdev);
  498. if (rc)
  499. return rc;
  500. if (pdev->vendor == PCI_VENDOR_ID_AMD) {
  501. amd_clear_fifo(pdev);
  502. if (pdev->device == PCI_DEVICE_ID_AMD_VIPER_7409 ||
  503. pdev->device == PCI_DEVICE_ID_AMD_COBRA_7401)
  504. ata_pci_bmdma_clear_simplex(pdev);
  505. }
  506. ata_host_resume(host);
  507. return 0;
  508. }
  509. #endif
  510. static const struct pci_device_id amd[] = {
  511. { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_COBRA_7401), 0 },
  512. { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_VIPER_7409), 1 },
  513. { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_VIPER_7411), 3 },
  514. { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_OPUS_7441), 4 },
  515. { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_8111_IDE), 5 },
  516. { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_IDE), 7 },
  517. { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2_IDE), 8 },
  518. { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2S_IDE), 8 },
  519. { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3_IDE), 8 },
  520. { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_IDE), 8 },
  521. { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_IDE), 8 },
  522. { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_IDE), 8 },
  523. { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_IDE), 8 },
  524. { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_IDE), 8 },
  525. { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_IDE), 8 },
  526. { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP65_IDE), 8 },
  527. { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP67_IDE), 8 },
  528. { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP73_IDE), 8 },
  529. { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP77_IDE), 8 },
  530. { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_CS5536_IDE), 9 },
  531. { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_CS5536_DEV_IDE), 9 },
  532. { },
  533. };
  534. static struct pci_driver amd_pci_driver = {
  535. .name = DRV_NAME,
  536. .id_table = amd,
  537. .probe = amd_init_one,
  538. .remove = ata_pci_remove_one,
  539. #ifdef CONFIG_PM_SLEEP
  540. .suspend = ata_pci_device_suspend,
  541. .resume = amd_reinit_one,
  542. #endif
  543. };
  544. module_pci_driver(amd_pci_driver);
  545. MODULE_AUTHOR("Alan Cox");
  546. MODULE_DESCRIPTION("low-level driver for AMD and Nvidia PATA IDE");
  547. MODULE_LICENSE("GPL");
  548. MODULE_DEVICE_TABLE(pci, amd);
  549. MODULE_VERSION(DRV_VERSION);