acard-ahci.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * acard-ahci.c - ACard AHCI SATA support
  4. *
  5. * Maintained by: Tejun Heo <tj@kernel.org>
  6. * Please ALWAYS copy linux-ide@vger.kernel.org
  7. * on emails.
  8. *
  9. * Copyright 2010 Red Hat, Inc.
  10. *
  11. * libata documentation is available via 'make {ps|pdf}docs',
  12. * as Documentation/driver-api/libata.rst
  13. *
  14. * AHCI hardware documentation:
  15. * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
  16. * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
  17. */
  18. #include <linux/kernel.h>
  19. #include <linux/module.h>
  20. #include <linux/pci.h>
  21. #include <linux/blkdev.h>
  22. #include <linux/delay.h>
  23. #include <linux/interrupt.h>
  24. #include <linux/dma-mapping.h>
  25. #include <linux/device.h>
  26. #include <linux/dmi.h>
  27. #include <linux/gfp.h>
  28. #include <scsi/scsi_host.h>
  29. #include <scsi/scsi_cmnd.h>
  30. #include <linux/libata.h>
  31. #include "ahci.h"
  32. #define DRV_NAME "acard-ahci"
  33. #define DRV_VERSION "1.0"
  34. /*
  35. Received FIS structure limited to 80h.
  36. */
  37. #define ACARD_AHCI_RX_FIS_SZ 128
  38. enum {
  39. AHCI_PCI_BAR = 5,
  40. };
  41. enum board_ids {
  42. board_acard_ahci,
  43. };
  44. struct acard_sg {
  45. __le32 addr;
  46. __le32 addr_hi;
  47. __le32 reserved;
  48. __le32 size; /* bit 31 (EOT) max==0x10000 (64k) */
  49. };
  50. static enum ata_completion_errors acard_ahci_qc_prep(struct ata_queued_cmd *qc);
  51. static bool acard_ahci_qc_fill_rtf(struct ata_queued_cmd *qc);
  52. static int acard_ahci_port_start(struct ata_port *ap);
  53. static int acard_ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
  54. #ifdef CONFIG_PM_SLEEP
  55. static int acard_ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
  56. static int acard_ahci_pci_device_resume(struct pci_dev *pdev);
  57. #endif
  58. static struct scsi_host_template acard_ahci_sht = {
  59. AHCI_SHT("acard-ahci"),
  60. };
  61. static struct ata_port_operations acard_ops = {
  62. .inherits = &ahci_ops,
  63. .qc_prep = acard_ahci_qc_prep,
  64. .qc_fill_rtf = acard_ahci_qc_fill_rtf,
  65. .port_start = acard_ahci_port_start,
  66. };
  67. #define AHCI_HFLAGS(flags) .private_data = (void *)(flags)
  68. static const struct ata_port_info acard_ahci_port_info[] = {
  69. [board_acard_ahci] =
  70. {
  71. AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ),
  72. .flags = AHCI_FLAG_COMMON,
  73. .pio_mask = ATA_PIO4,
  74. .udma_mask = ATA_UDMA6,
  75. .port_ops = &acard_ops,
  76. },
  77. };
  78. static const struct pci_device_id acard_ahci_pci_tbl[] = {
  79. /* ACard */
  80. { PCI_VDEVICE(ARTOP, 0x000d), board_acard_ahci }, /* ATP8620 */
  81. { } /* terminate list */
  82. };
  83. static struct pci_driver acard_ahci_pci_driver = {
  84. .name = DRV_NAME,
  85. .id_table = acard_ahci_pci_tbl,
  86. .probe = acard_ahci_init_one,
  87. .remove = ata_pci_remove_one,
  88. #ifdef CONFIG_PM_SLEEP
  89. .suspend = acard_ahci_pci_device_suspend,
  90. .resume = acard_ahci_pci_device_resume,
  91. #endif
  92. };
  93. #ifdef CONFIG_PM_SLEEP
  94. static int acard_ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
  95. {
  96. struct ata_host *host = pci_get_drvdata(pdev);
  97. struct ahci_host_priv *hpriv = host->private_data;
  98. void __iomem *mmio = hpriv->mmio;
  99. u32 ctl;
  100. if (mesg.event & PM_EVENT_SUSPEND &&
  101. hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
  102. dev_err(&pdev->dev,
  103. "BIOS update required for suspend/resume\n");
  104. return -EIO;
  105. }
  106. if (mesg.event & PM_EVENT_SLEEP) {
  107. /* AHCI spec rev1.1 section 8.3.3:
  108. * Software must disable interrupts prior to requesting a
  109. * transition of the HBA to D3 state.
  110. */
  111. ctl = readl(mmio + HOST_CTL);
  112. ctl &= ~HOST_IRQ_EN;
  113. writel(ctl, mmio + HOST_CTL);
  114. readl(mmio + HOST_CTL); /* flush */
  115. }
  116. return ata_pci_device_suspend(pdev, mesg);
  117. }
  118. static int acard_ahci_pci_device_resume(struct pci_dev *pdev)
  119. {
  120. struct ata_host *host = pci_get_drvdata(pdev);
  121. int rc;
  122. rc = ata_pci_device_do_resume(pdev);
  123. if (rc)
  124. return rc;
  125. if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
  126. rc = ahci_reset_controller(host);
  127. if (rc)
  128. return rc;
  129. ahci_init_controller(host);
  130. }
  131. ata_host_resume(host);
  132. return 0;
  133. }
  134. #endif
  135. static void acard_ahci_pci_print_info(struct ata_host *host)
  136. {
  137. struct pci_dev *pdev = to_pci_dev(host->dev);
  138. u16 cc;
  139. const char *scc_s;
  140. pci_read_config_word(pdev, 0x0a, &cc);
  141. if (cc == PCI_CLASS_STORAGE_IDE)
  142. scc_s = "IDE";
  143. else if (cc == PCI_CLASS_STORAGE_SATA)
  144. scc_s = "SATA";
  145. else if (cc == PCI_CLASS_STORAGE_RAID)
  146. scc_s = "RAID";
  147. else
  148. scc_s = "unknown";
  149. ahci_print_info(host, scc_s);
  150. }
  151. static unsigned int acard_ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
  152. {
  153. struct scatterlist *sg;
  154. struct acard_sg *acard_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
  155. unsigned int si, last_si = 0;
  156. VPRINTK("ENTER\n");
  157. /*
  158. * Next, the S/G list.
  159. */
  160. for_each_sg(qc->sg, sg, qc->n_elem, si) {
  161. dma_addr_t addr = sg_dma_address(sg);
  162. u32 sg_len = sg_dma_len(sg);
  163. /*
  164. * ACard note:
  165. * We must set an end-of-table (EOT) bit,
  166. * and the segment cannot exceed 64k (0x10000)
  167. */
  168. acard_sg[si].addr = cpu_to_le32(addr & 0xffffffff);
  169. acard_sg[si].addr_hi = cpu_to_le32((addr >> 16) >> 16);
  170. acard_sg[si].size = cpu_to_le32(sg_len);
  171. last_si = si;
  172. }
  173. acard_sg[last_si].size |= cpu_to_le32(1 << 31); /* set EOT */
  174. return si;
  175. }
  176. static enum ata_completion_errors acard_ahci_qc_prep(struct ata_queued_cmd *qc)
  177. {
  178. struct ata_port *ap = qc->ap;
  179. struct ahci_port_priv *pp = ap->private_data;
  180. int is_atapi = ata_is_atapi(qc->tf.protocol);
  181. void *cmd_tbl;
  182. u32 opts;
  183. const u32 cmd_fis_len = 5; /* five dwords */
  184. /*
  185. * Fill in command table information. First, the header,
  186. * a SATA Register - Host to Device command FIS.
  187. */
  188. cmd_tbl = pp->cmd_tbl + qc->hw_tag * AHCI_CMD_TBL_SZ;
  189. ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl);
  190. if (is_atapi) {
  191. memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
  192. memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len);
  193. }
  194. if (qc->flags & ATA_QCFLAG_DMAMAP)
  195. acard_ahci_fill_sg(qc, cmd_tbl);
  196. /*
  197. * Fill in command slot information.
  198. *
  199. * ACard note: prd table length not filled in
  200. */
  201. opts = cmd_fis_len | (qc->dev->link->pmp << 12);
  202. if (qc->tf.flags & ATA_TFLAG_WRITE)
  203. opts |= AHCI_CMD_WRITE;
  204. if (is_atapi)
  205. opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
  206. ahci_fill_cmd_slot(pp, qc->hw_tag, opts);
  207. return AC_ERR_OK;
  208. }
  209. static bool acard_ahci_qc_fill_rtf(struct ata_queued_cmd *qc)
  210. {
  211. struct ahci_port_priv *pp = qc->ap->private_data;
  212. u8 *rx_fis = pp->rx_fis;
  213. if (pp->fbs_enabled)
  214. rx_fis += qc->dev->link->pmp * ACARD_AHCI_RX_FIS_SZ;
  215. /*
  216. * After a successful execution of an ATA PIO data-in command,
  217. * the device doesn't send D2H Reg FIS to update the TF and
  218. * the host should take TF and E_Status from the preceding PIO
  219. * Setup FIS.
  220. */
  221. if (qc->tf.protocol == ATA_PROT_PIO && qc->dma_dir == DMA_FROM_DEVICE &&
  222. !(qc->flags & ATA_QCFLAG_FAILED)) {
  223. ata_tf_from_fis(rx_fis + RX_FIS_PIO_SETUP, &qc->result_tf);
  224. qc->result_tf.command = (rx_fis + RX_FIS_PIO_SETUP)[15];
  225. } else
  226. ata_tf_from_fis(rx_fis + RX_FIS_D2H_REG, &qc->result_tf);
  227. return true;
  228. }
  229. static int acard_ahci_port_start(struct ata_port *ap)
  230. {
  231. struct ahci_host_priv *hpriv = ap->host->private_data;
  232. struct device *dev = ap->host->dev;
  233. struct ahci_port_priv *pp;
  234. void *mem;
  235. dma_addr_t mem_dma;
  236. size_t dma_sz, rx_fis_sz;
  237. pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
  238. if (!pp)
  239. return -ENOMEM;
  240. /* check FBS capability */
  241. if ((hpriv->cap & HOST_CAP_FBS) && sata_pmp_supported(ap)) {
  242. void __iomem *port_mmio = ahci_port_base(ap);
  243. u32 cmd = readl(port_mmio + PORT_CMD);
  244. if (cmd & PORT_CMD_FBSCP)
  245. pp->fbs_supported = true;
  246. else if (hpriv->flags & AHCI_HFLAG_YES_FBS) {
  247. dev_info(dev, "port %d can do FBS, forcing FBSCP\n",
  248. ap->port_no);
  249. pp->fbs_supported = true;
  250. } else
  251. dev_warn(dev, "port %d is not capable of FBS\n",
  252. ap->port_no);
  253. }
  254. if (pp->fbs_supported) {
  255. dma_sz = AHCI_PORT_PRIV_FBS_DMA_SZ;
  256. rx_fis_sz = ACARD_AHCI_RX_FIS_SZ * 16;
  257. } else {
  258. dma_sz = AHCI_PORT_PRIV_DMA_SZ;
  259. rx_fis_sz = ACARD_AHCI_RX_FIS_SZ;
  260. }
  261. mem = dmam_alloc_coherent(dev, dma_sz, &mem_dma, GFP_KERNEL);
  262. if (!mem)
  263. return -ENOMEM;
  264. /*
  265. * First item in chunk of DMA memory: 32-slot command table,
  266. * 32 bytes each in size
  267. */
  268. pp->cmd_slot = mem;
  269. pp->cmd_slot_dma = mem_dma;
  270. mem += AHCI_CMD_SLOT_SZ;
  271. mem_dma += AHCI_CMD_SLOT_SZ;
  272. /*
  273. * Second item: Received-FIS area
  274. */
  275. pp->rx_fis = mem;
  276. pp->rx_fis_dma = mem_dma;
  277. mem += rx_fis_sz;
  278. mem_dma += rx_fis_sz;
  279. /*
  280. * Third item: data area for storing a single command
  281. * and its scatter-gather table
  282. */
  283. pp->cmd_tbl = mem;
  284. pp->cmd_tbl_dma = mem_dma;
  285. /*
  286. * Save off initial list of interrupts to be enabled.
  287. * This could be changed later
  288. */
  289. pp->intr_mask = DEF_PORT_IRQ;
  290. ap->private_data = pp;
  291. /* engage engines, captain */
  292. return ahci_port_resume(ap);
  293. }
  294. static int acard_ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
  295. {
  296. unsigned int board_id = ent->driver_data;
  297. struct ata_port_info pi = acard_ahci_port_info[board_id];
  298. const struct ata_port_info *ppi[] = { &pi, NULL };
  299. struct device *dev = &pdev->dev;
  300. struct ahci_host_priv *hpriv;
  301. struct ata_host *host;
  302. int n_ports, i, rc;
  303. VPRINTK("ENTER\n");
  304. WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
  305. ata_print_version_once(&pdev->dev, DRV_VERSION);
  306. /* acquire resources */
  307. rc = pcim_enable_device(pdev);
  308. if (rc)
  309. return rc;
  310. /* AHCI controllers often implement SFF compatible interface.
  311. * Grab all PCI BARs just in case.
  312. */
  313. rc = pcim_iomap_regions_request_all(pdev, 1 << AHCI_PCI_BAR, DRV_NAME);
  314. if (rc == -EBUSY)
  315. pcim_pin_device(pdev);
  316. if (rc)
  317. return rc;
  318. hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
  319. if (!hpriv)
  320. return -ENOMEM;
  321. hpriv->irq = pdev->irq;
  322. hpriv->flags |= (unsigned long)pi.private_data;
  323. if (!(hpriv->flags & AHCI_HFLAG_NO_MSI))
  324. pci_enable_msi(pdev);
  325. hpriv->mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR];
  326. /* save initial config */
  327. ahci_save_initial_config(&pdev->dev, hpriv);
  328. /* prepare host */
  329. if (hpriv->cap & HOST_CAP_NCQ)
  330. pi.flags |= ATA_FLAG_NCQ;
  331. if (hpriv->cap & HOST_CAP_PMP)
  332. pi.flags |= ATA_FLAG_PMP;
  333. ahci_set_em_messages(hpriv, &pi);
  334. /* CAP.NP sometimes indicate the index of the last enabled
  335. * port, at other times, that of the last possible port, so
  336. * determining the maximum port number requires looking at
  337. * both CAP.NP and port_map.
  338. */
  339. n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
  340. host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
  341. if (!host)
  342. return -ENOMEM;
  343. host->private_data = hpriv;
  344. if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
  345. host->flags |= ATA_HOST_PARALLEL_SCAN;
  346. else
  347. printk(KERN_INFO "ahci: SSS flag set, parallel bus scan disabled\n");
  348. for (i = 0; i < host->n_ports; i++) {
  349. struct ata_port *ap = host->ports[i];
  350. ata_port_pbar_desc(ap, AHCI_PCI_BAR, -1, "abar");
  351. ata_port_pbar_desc(ap, AHCI_PCI_BAR,
  352. 0x100 + ap->port_no * 0x80, "port");
  353. /* set initial link pm policy */
  354. /*
  355. ap->pm_policy = NOT_AVAILABLE;
  356. */
  357. /* disabled/not-implemented port */
  358. if (!(hpriv->port_map & (1 << i)))
  359. ap->ops = &ata_dummy_port_ops;
  360. }
  361. /* initialize adapter */
  362. rc = dma_set_mask_and_coherent(&pdev->dev,
  363. DMA_BIT_MASK((hpriv->cap & HOST_CAP_64) ? 64 : 32));
  364. if (rc) {
  365. dev_err(&pdev->dev, "DMA enable failed\n");
  366. return rc;
  367. }
  368. rc = ahci_reset_controller(host);
  369. if (rc)
  370. return rc;
  371. ahci_init_controller(host);
  372. acard_ahci_pci_print_info(host);
  373. pci_set_master(pdev);
  374. return ahci_host_activate(host, &acard_ahci_sht);
  375. }
  376. module_pci_driver(acard_ahci_pci_driver);
  377. MODULE_AUTHOR("Jeff Garzik");
  378. MODULE_DESCRIPTION("ACard AHCI SATA low-level driver");
  379. MODULE_LICENSE("GPL");
  380. MODULE_DEVICE_TABLE(pci, acard_ahci_pci_tbl);
  381. MODULE_VERSION(DRV_VERSION);