spcr.c 5.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2012, Intel Corporation
  4. * Copyright (c) 2015, Red Hat, Inc.
  5. * Copyright (c) 2015, 2016 Linaro Ltd.
  6. */
  7. #define pr_fmt(fmt) "ACPI: SPCR: " fmt
  8. #include <linux/acpi.h>
  9. #include <linux/console.h>
  10. #include <linux/kernel.h>
  11. #include <linux/serial_core.h>
  12. /*
  13. * Erratum 44 for QDF2432v1 and QDF2400v1 SoCs describes the BUSY bit as
  14. * occasionally getting stuck as 1. To avoid the potential for a hang, check
  15. * TXFE == 0 instead of BUSY == 1. This may not be suitable for all UART
  16. * implementations, so only do so if an affected platform is detected in
  17. * acpi_parse_spcr().
  18. */
  19. bool qdf2400_e44_present;
  20. EXPORT_SYMBOL(qdf2400_e44_present);
  21. /*
  22. * Some Qualcomm Datacenter Technologies SoCs have a defective UART BUSY bit.
  23. * Detect them by examining the OEM fields in the SPCR header, similar to PCI
  24. * quirk detection in pci_mcfg.c.
  25. */
  26. static bool qdf2400_erratum_44_present(struct acpi_table_header *h)
  27. {
  28. if (memcmp(h->oem_id, "QCOM ", ACPI_OEM_ID_SIZE))
  29. return false;
  30. if (!memcmp(h->oem_table_id, "QDF2432 ", ACPI_OEM_TABLE_ID_SIZE))
  31. return true;
  32. if (!memcmp(h->oem_table_id, "QDF2400 ", ACPI_OEM_TABLE_ID_SIZE) &&
  33. h->oem_revision == 1)
  34. return true;
  35. return false;
  36. }
  37. /*
  38. * APM X-Gene v1 and v2 UART hardware is an 16550 like device but has its
  39. * register aligned to 32-bit. In addition, the BIOS also encoded the
  40. * access width to be 8 bits. This function detects this errata condition.
  41. */
  42. static bool xgene_8250_erratum_present(struct acpi_table_spcr *tb)
  43. {
  44. bool xgene_8250 = false;
  45. if (tb->interface_type != ACPI_DBG2_16550_COMPATIBLE)
  46. return false;
  47. if (memcmp(tb->header.oem_id, "APMC0D", ACPI_OEM_ID_SIZE) &&
  48. memcmp(tb->header.oem_id, "HPE ", ACPI_OEM_ID_SIZE))
  49. return false;
  50. if (!memcmp(tb->header.oem_table_id, "XGENESPC",
  51. ACPI_OEM_TABLE_ID_SIZE) && tb->header.oem_revision == 0)
  52. xgene_8250 = true;
  53. if (!memcmp(tb->header.oem_table_id, "ProLiant",
  54. ACPI_OEM_TABLE_ID_SIZE) && tb->header.oem_revision == 1)
  55. xgene_8250 = true;
  56. return xgene_8250;
  57. }
  58. /**
  59. * acpi_parse_spcr() - parse ACPI SPCR table and add preferred console
  60. *
  61. * @enable_earlycon: set up earlycon for the console specified by the table
  62. * @enable_console: setup the console specified by the table.
  63. *
  64. * For the architectures with support for ACPI, CONFIG_ACPI_SPCR_TABLE may be
  65. * defined to parse ACPI SPCR table. As a result of the parsing preferred
  66. * console is registered and if @enable_earlycon is true, earlycon is set up.
  67. * If @enable_console is true the system console is also configured.
  68. *
  69. * When CONFIG_ACPI_SPCR_TABLE is defined, this function should be called
  70. * from arch initialization code as soon as the DT/ACPI decision is made.
  71. *
  72. */
  73. int __init acpi_parse_spcr(bool enable_earlycon, bool enable_console)
  74. {
  75. static char opts[64];
  76. struct acpi_table_spcr *table;
  77. acpi_status status;
  78. char *uart;
  79. char *iotype;
  80. int baud_rate;
  81. int err;
  82. if (acpi_disabled)
  83. return -ENODEV;
  84. status = acpi_get_table(ACPI_SIG_SPCR, 0,
  85. (struct acpi_table_header **)&table);
  86. if (ACPI_FAILURE(status))
  87. return -ENOENT;
  88. if (table->header.revision < 2)
  89. pr_info("SPCR table version %d\n", table->header.revision);
  90. if (table->serial_port.space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY) {
  91. switch (ACPI_ACCESS_BIT_WIDTH((
  92. table->serial_port.access_width))) {
  93. default:
  94. pr_err("Unexpected SPCR Access Width. Defaulting to byte size\n");
  95. fallthrough;
  96. case 8:
  97. iotype = "mmio";
  98. break;
  99. case 16:
  100. iotype = "mmio16";
  101. break;
  102. case 32:
  103. iotype = "mmio32";
  104. break;
  105. }
  106. } else
  107. iotype = "io";
  108. switch (table->interface_type) {
  109. case ACPI_DBG2_ARM_SBSA_32BIT:
  110. iotype = "mmio32";
  111. fallthrough;
  112. case ACPI_DBG2_ARM_PL011:
  113. case ACPI_DBG2_ARM_SBSA_GENERIC:
  114. case ACPI_DBG2_BCM2835:
  115. uart = "pl011";
  116. break;
  117. case ACPI_DBG2_16550_COMPATIBLE:
  118. case ACPI_DBG2_16550_SUBSET:
  119. uart = "uart";
  120. break;
  121. default:
  122. err = -ENOENT;
  123. goto done;
  124. }
  125. switch (table->baud_rate) {
  126. case 0:
  127. /*
  128. * SPCR 1.04 defines 0 as a preconfigured state of UART.
  129. * Assume firmware or bootloader configures console correctly.
  130. */
  131. baud_rate = 0;
  132. break;
  133. case 3:
  134. baud_rate = 9600;
  135. break;
  136. case 4:
  137. baud_rate = 19200;
  138. break;
  139. case 6:
  140. baud_rate = 57600;
  141. break;
  142. case 7:
  143. baud_rate = 115200;
  144. break;
  145. default:
  146. err = -ENOENT;
  147. goto done;
  148. }
  149. /*
  150. * If the E44 erratum is required, then we need to tell the pl011
  151. * driver to implement the work-around.
  152. *
  153. * The global variable is used by the probe function when it
  154. * creates the UARTs, whether or not they're used as a console.
  155. *
  156. * If the user specifies "traditional" earlycon, the qdf2400_e44
  157. * console name matches the EARLYCON_DECLARE() statement, and
  158. * SPCR is not used. Parameter "earlycon" is false.
  159. *
  160. * If the user specifies "SPCR" earlycon, then we need to update
  161. * the console name so that it also says "qdf2400_e44". Parameter
  162. * "earlycon" is true.
  163. *
  164. * For consistency, if we change the console name, then we do it
  165. * for everyone, not just earlycon.
  166. */
  167. if (qdf2400_erratum_44_present(&table->header)) {
  168. qdf2400_e44_present = true;
  169. if (enable_earlycon)
  170. uart = "qdf2400_e44";
  171. }
  172. if (xgene_8250_erratum_present(table)) {
  173. iotype = "mmio32";
  174. /* for xgene v1 and v2 we don't know the clock rate of the
  175. * UART so don't attempt to change to the baud rate state
  176. * in the table because driver cannot calculate the dividers
  177. */
  178. baud_rate = 0;
  179. }
  180. if (!baud_rate) {
  181. snprintf(opts, sizeof(opts), "%s,%s,0x%llx", uart, iotype,
  182. table->serial_port.address);
  183. } else {
  184. snprintf(opts, sizeof(opts), "%s,%s,0x%llx,%d", uart, iotype,
  185. table->serial_port.address, baud_rate);
  186. }
  187. pr_info("console: %s\n", opts);
  188. if (enable_earlycon)
  189. setup_earlycon(opts);
  190. if (enable_console)
  191. err = add_preferred_console(uart, 0, opts + strlen(uart) + 1);
  192. else
  193. err = 0;
  194. done:
  195. acpi_put_table((struct acpi_table_header *)table);
  196. return err;
  197. }