pci_mcfg.c 8.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (C) 2016 Broadcom
  4. * Author: Jayachandran C <jchandra@broadcom.com>
  5. * Copyright (C) 2016 Semihalf
  6. * Author: Tomasz Nowicki <tn@semihalf.com>
  7. */
  8. #define pr_fmt(fmt) "ACPI: " fmt
  9. #include <linux/kernel.h>
  10. #include <linux/pci.h>
  11. #include <linux/pci-acpi.h>
  12. #include <linux/pci-ecam.h>
  13. /* Structure to hold entries from the MCFG table */
  14. struct mcfg_entry {
  15. struct list_head list;
  16. phys_addr_t addr;
  17. u16 segment;
  18. u8 bus_start;
  19. u8 bus_end;
  20. };
  21. #ifdef CONFIG_PCI_QUIRKS
  22. struct mcfg_fixup {
  23. char oem_id[ACPI_OEM_ID_SIZE + 1];
  24. char oem_table_id[ACPI_OEM_TABLE_ID_SIZE + 1];
  25. u32 oem_revision;
  26. u16 segment;
  27. struct resource bus_range;
  28. const struct pci_ecam_ops *ops;
  29. struct resource cfgres;
  30. };
  31. #define MCFG_BUS_RANGE(start, end) DEFINE_RES_NAMED((start), \
  32. ((end) - (start) + 1), \
  33. NULL, IORESOURCE_BUS)
  34. #define MCFG_BUS_ANY MCFG_BUS_RANGE(0x0, 0xff)
  35. static struct mcfg_fixup mcfg_quirks[] = {
  36. /* { OEM_ID, OEM_TABLE_ID, REV, SEGMENT, BUS_RANGE, ops, cfgres }, */
  37. #define AL_ECAM(table_id, rev, seg, ops) \
  38. { "AMAZON", table_id, rev, seg, MCFG_BUS_ANY, ops }
  39. AL_ECAM("GRAVITON", 0, 0, &al_pcie_ops),
  40. AL_ECAM("GRAVITON", 0, 1, &al_pcie_ops),
  41. AL_ECAM("GRAVITON", 0, 2, &al_pcie_ops),
  42. AL_ECAM("GRAVITON", 0, 3, &al_pcie_ops),
  43. AL_ECAM("GRAVITON", 0, 4, &al_pcie_ops),
  44. AL_ECAM("GRAVITON", 0, 5, &al_pcie_ops),
  45. AL_ECAM("GRAVITON", 0, 6, &al_pcie_ops),
  46. AL_ECAM("GRAVITON", 0, 7, &al_pcie_ops),
  47. #define QCOM_ECAM32(seg) \
  48. { "QCOM ", "QDF2432 ", 1, seg, MCFG_BUS_ANY, &pci_32b_ops }
  49. QCOM_ECAM32(0),
  50. QCOM_ECAM32(1),
  51. QCOM_ECAM32(2),
  52. QCOM_ECAM32(3),
  53. QCOM_ECAM32(4),
  54. QCOM_ECAM32(5),
  55. QCOM_ECAM32(6),
  56. QCOM_ECAM32(7),
  57. #define HISI_QUAD_DOM(table_id, seg, ops) \
  58. { "HISI ", table_id, 0, (seg) + 0, MCFG_BUS_ANY, ops }, \
  59. { "HISI ", table_id, 0, (seg) + 1, MCFG_BUS_ANY, ops }, \
  60. { "HISI ", table_id, 0, (seg) + 2, MCFG_BUS_ANY, ops }, \
  61. { "HISI ", table_id, 0, (seg) + 3, MCFG_BUS_ANY, ops }
  62. HISI_QUAD_DOM("HIP05 ", 0, &hisi_pcie_ops),
  63. HISI_QUAD_DOM("HIP06 ", 0, &hisi_pcie_ops),
  64. HISI_QUAD_DOM("HIP07 ", 0, &hisi_pcie_ops),
  65. HISI_QUAD_DOM("HIP07 ", 4, &hisi_pcie_ops),
  66. HISI_QUAD_DOM("HIP07 ", 8, &hisi_pcie_ops),
  67. HISI_QUAD_DOM("HIP07 ", 12, &hisi_pcie_ops),
  68. #define THUNDER_PEM_RES(addr, node) \
  69. DEFINE_RES_MEM((addr) + ((u64) (node) << 44), 0x39 * SZ_16M)
  70. #define THUNDER_PEM_QUIRK(rev, node) \
  71. { "CAVIUM", "THUNDERX", rev, 4 + (10 * (node)), MCFG_BUS_ANY, \
  72. &thunder_pem_ecam_ops, THUNDER_PEM_RES(0x88001f000000UL, node) }, \
  73. { "CAVIUM", "THUNDERX", rev, 5 + (10 * (node)), MCFG_BUS_ANY, \
  74. &thunder_pem_ecam_ops, THUNDER_PEM_RES(0x884057000000UL, node) }, \
  75. { "CAVIUM", "THUNDERX", rev, 6 + (10 * (node)), MCFG_BUS_ANY, \
  76. &thunder_pem_ecam_ops, THUNDER_PEM_RES(0x88808f000000UL, node) }, \
  77. { "CAVIUM", "THUNDERX", rev, 7 + (10 * (node)), MCFG_BUS_ANY, \
  78. &thunder_pem_ecam_ops, THUNDER_PEM_RES(0x89001f000000UL, node) }, \
  79. { "CAVIUM", "THUNDERX", rev, 8 + (10 * (node)), MCFG_BUS_ANY, \
  80. &thunder_pem_ecam_ops, THUNDER_PEM_RES(0x894057000000UL, node) }, \
  81. { "CAVIUM", "THUNDERX", rev, 9 + (10 * (node)), MCFG_BUS_ANY, \
  82. &thunder_pem_ecam_ops, THUNDER_PEM_RES(0x89808f000000UL, node) }
  83. #define THUNDER_ECAM_QUIRK(rev, seg) \
  84. { "CAVIUM", "THUNDERX", rev, seg, MCFG_BUS_ANY, \
  85. &pci_thunder_ecam_ops }
  86. /* SoC pass2.x */
  87. THUNDER_PEM_QUIRK(1, 0),
  88. THUNDER_PEM_QUIRK(1, 1),
  89. THUNDER_ECAM_QUIRK(1, 10),
  90. /* SoC pass1.x */
  91. THUNDER_PEM_QUIRK(2, 0), /* off-chip devices */
  92. THUNDER_PEM_QUIRK(2, 1), /* off-chip devices */
  93. THUNDER_ECAM_QUIRK(2, 0),
  94. THUNDER_ECAM_QUIRK(2, 1),
  95. THUNDER_ECAM_QUIRK(2, 2),
  96. THUNDER_ECAM_QUIRK(2, 3),
  97. THUNDER_ECAM_QUIRK(2, 10),
  98. THUNDER_ECAM_QUIRK(2, 11),
  99. THUNDER_ECAM_QUIRK(2, 12),
  100. THUNDER_ECAM_QUIRK(2, 13),
  101. #define XGENE_V1_ECAM_MCFG(rev, seg) \
  102. {"APM ", "XGENE ", rev, seg, MCFG_BUS_ANY, \
  103. &xgene_v1_pcie_ecam_ops }
  104. #define XGENE_V2_ECAM_MCFG(rev, seg) \
  105. {"APM ", "XGENE ", rev, seg, MCFG_BUS_ANY, \
  106. &xgene_v2_pcie_ecam_ops }
  107. /* X-Gene SoC with v1 PCIe controller */
  108. XGENE_V1_ECAM_MCFG(1, 0),
  109. XGENE_V1_ECAM_MCFG(1, 1),
  110. XGENE_V1_ECAM_MCFG(1, 2),
  111. XGENE_V1_ECAM_MCFG(1, 3),
  112. XGENE_V1_ECAM_MCFG(1, 4),
  113. XGENE_V1_ECAM_MCFG(2, 0),
  114. XGENE_V1_ECAM_MCFG(2, 1),
  115. XGENE_V1_ECAM_MCFG(2, 2),
  116. XGENE_V1_ECAM_MCFG(2, 3),
  117. XGENE_V1_ECAM_MCFG(2, 4),
  118. /* X-Gene SoC with v2.1 PCIe controller */
  119. XGENE_V2_ECAM_MCFG(3, 0),
  120. XGENE_V2_ECAM_MCFG(3, 1),
  121. /* X-Gene SoC with v2.2 PCIe controller */
  122. XGENE_V2_ECAM_MCFG(4, 0),
  123. XGENE_V2_ECAM_MCFG(4, 1),
  124. XGENE_V2_ECAM_MCFG(4, 2),
  125. #define ALTRA_ECAM_QUIRK(rev, seg) \
  126. { "Ampere", "Altra ", rev, seg, MCFG_BUS_ANY, &pci_32b_read_ops }
  127. ALTRA_ECAM_QUIRK(1, 0),
  128. ALTRA_ECAM_QUIRK(1, 1),
  129. ALTRA_ECAM_QUIRK(1, 2),
  130. ALTRA_ECAM_QUIRK(1, 3),
  131. ALTRA_ECAM_QUIRK(1, 4),
  132. ALTRA_ECAM_QUIRK(1, 5),
  133. ALTRA_ECAM_QUIRK(1, 6),
  134. ALTRA_ECAM_QUIRK(1, 7),
  135. ALTRA_ECAM_QUIRK(1, 8),
  136. ALTRA_ECAM_QUIRK(1, 9),
  137. ALTRA_ECAM_QUIRK(1, 10),
  138. ALTRA_ECAM_QUIRK(1, 11),
  139. ALTRA_ECAM_QUIRK(1, 12),
  140. ALTRA_ECAM_QUIRK(1, 13),
  141. ALTRA_ECAM_QUIRK(1, 14),
  142. ALTRA_ECAM_QUIRK(1, 15),
  143. };
  144. static char mcfg_oem_id[ACPI_OEM_ID_SIZE];
  145. static char mcfg_oem_table_id[ACPI_OEM_TABLE_ID_SIZE];
  146. static u32 mcfg_oem_revision;
  147. static int pci_mcfg_quirk_matches(struct mcfg_fixup *f, u16 segment,
  148. struct resource *bus_range)
  149. {
  150. if (!memcmp(f->oem_id, mcfg_oem_id, ACPI_OEM_ID_SIZE) &&
  151. !memcmp(f->oem_table_id, mcfg_oem_table_id,
  152. ACPI_OEM_TABLE_ID_SIZE) &&
  153. f->oem_revision == mcfg_oem_revision &&
  154. f->segment == segment &&
  155. resource_contains(&f->bus_range, bus_range))
  156. return 1;
  157. return 0;
  158. }
  159. #endif
  160. static void pci_mcfg_apply_quirks(struct acpi_pci_root *root,
  161. struct resource *cfgres,
  162. const struct pci_ecam_ops **ecam_ops)
  163. {
  164. #ifdef CONFIG_PCI_QUIRKS
  165. u16 segment = root->segment;
  166. struct resource *bus_range = &root->secondary;
  167. struct mcfg_fixup *f;
  168. int i;
  169. for (i = 0, f = mcfg_quirks; i < ARRAY_SIZE(mcfg_quirks); i++, f++) {
  170. if (pci_mcfg_quirk_matches(f, segment, bus_range)) {
  171. if (f->cfgres.start)
  172. *cfgres = f->cfgres;
  173. if (f->ops)
  174. *ecam_ops = f->ops;
  175. dev_info(&root->device->dev, "MCFG quirk: ECAM at %pR for %pR with %ps\n",
  176. cfgres, bus_range, *ecam_ops);
  177. return;
  178. }
  179. }
  180. #endif
  181. }
  182. /* List to save MCFG entries */
  183. static LIST_HEAD(pci_mcfg_list);
  184. int pci_mcfg_lookup(struct acpi_pci_root *root, struct resource *cfgres,
  185. const struct pci_ecam_ops **ecam_ops)
  186. {
  187. const struct pci_ecam_ops *ops = &pci_generic_ecam_ops;
  188. struct resource *bus_res = &root->secondary;
  189. u16 seg = root->segment;
  190. struct mcfg_entry *e;
  191. struct resource res;
  192. /* Use address from _CBA if present, otherwise lookup MCFG */
  193. if (root->mcfg_addr)
  194. goto skip_lookup;
  195. /*
  196. * We expect the range in bus_res in the coverage of MCFG bus range.
  197. */
  198. list_for_each_entry(e, &pci_mcfg_list, list) {
  199. if (e->segment == seg && e->bus_start <= bus_res->start &&
  200. e->bus_end >= bus_res->end) {
  201. root->mcfg_addr = e->addr;
  202. }
  203. }
  204. skip_lookup:
  205. memset(&res, 0, sizeof(res));
  206. if (root->mcfg_addr) {
  207. res.start = root->mcfg_addr + (bus_res->start << 20);
  208. res.end = res.start + (resource_size(bus_res) << 20) - 1;
  209. res.flags = IORESOURCE_MEM;
  210. }
  211. /*
  212. * Allow quirks to override default ECAM ops and CFG resource
  213. * range. This may even fabricate a CFG resource range in case
  214. * MCFG does not have it. Invalid CFG start address means MCFG
  215. * firmware bug or we need another quirk in array.
  216. */
  217. pci_mcfg_apply_quirks(root, &res, &ops);
  218. if (!res.start)
  219. return -ENXIO;
  220. *cfgres = res;
  221. *ecam_ops = ops;
  222. return 0;
  223. }
  224. static __init int pci_mcfg_parse(struct acpi_table_header *header)
  225. {
  226. struct acpi_table_mcfg *mcfg;
  227. struct acpi_mcfg_allocation *mptr;
  228. struct mcfg_entry *e, *arr;
  229. int i, n;
  230. if (header->length < sizeof(struct acpi_table_mcfg))
  231. return -EINVAL;
  232. n = (header->length - sizeof(struct acpi_table_mcfg)) /
  233. sizeof(struct acpi_mcfg_allocation);
  234. mcfg = (struct acpi_table_mcfg *)header;
  235. mptr = (struct acpi_mcfg_allocation *) &mcfg[1];
  236. arr = kcalloc(n, sizeof(*arr), GFP_KERNEL);
  237. if (!arr)
  238. return -ENOMEM;
  239. for (i = 0, e = arr; i < n; i++, mptr++, e++) {
  240. e->segment = mptr->pci_segment;
  241. e->addr = mptr->address;
  242. e->bus_start = mptr->start_bus_number;
  243. e->bus_end = mptr->end_bus_number;
  244. list_add(&e->list, &pci_mcfg_list);
  245. }
  246. #ifdef CONFIG_PCI_QUIRKS
  247. /* Save MCFG IDs and revision for quirks matching */
  248. memcpy(mcfg_oem_id, header->oem_id, ACPI_OEM_ID_SIZE);
  249. memcpy(mcfg_oem_table_id, header->oem_table_id, ACPI_OEM_TABLE_ID_SIZE);
  250. mcfg_oem_revision = header->oem_revision;
  251. #endif
  252. pr_info("MCFG table detected, %d entries\n", n);
  253. return 0;
  254. }
  255. /* Interface called by ACPI - parse and save MCFG table */
  256. void __init pci_mmcfg_late_init(void)
  257. {
  258. int err = acpi_table_parse(ACPI_SIG_MCFG, pci_mcfg_parse);
  259. if (err)
  260. pr_debug("Failed to parse MCFG (%d)\n", err);
  261. }