intel.h 4.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright(c) 2018 Intel Corporation. All rights reserved.
  4. * Intel specific definitions for NVDIMM Firmware Interface Table - NFIT
  5. */
  6. #ifndef _NFIT_INTEL_H_
  7. #define _NFIT_INTEL_H_
  8. #define ND_INTEL_SMART 1
  9. #define ND_INTEL_SMART_SHUTDOWN_COUNT_VALID (1 << 5)
  10. #define ND_INTEL_SMART_SHUTDOWN_VALID (1 << 10)
  11. struct nd_intel_smart {
  12. u32 status;
  13. union {
  14. struct {
  15. u32 flags;
  16. u8 reserved0[4];
  17. u8 health;
  18. u8 spares;
  19. u8 life_used;
  20. u8 alarm_flags;
  21. u16 media_temperature;
  22. u16 ctrl_temperature;
  23. u32 shutdown_count;
  24. u8 ait_status;
  25. u16 pmic_temperature;
  26. u8 reserved1[8];
  27. u8 shutdown_state;
  28. u32 vendor_size;
  29. u8 vendor_data[92];
  30. } __packed;
  31. u8 data[128];
  32. };
  33. } __packed;
  34. extern const struct nvdimm_security_ops *intel_security_ops;
  35. #define ND_INTEL_STATUS_SIZE 4
  36. #define ND_INTEL_PASSPHRASE_SIZE 32
  37. #define ND_INTEL_STATUS_NOT_SUPPORTED 1
  38. #define ND_INTEL_STATUS_RETRY 5
  39. #define ND_INTEL_STATUS_NOT_READY 9
  40. #define ND_INTEL_STATUS_INVALID_STATE 10
  41. #define ND_INTEL_STATUS_INVALID_PASS 11
  42. #define ND_INTEL_STATUS_OVERWRITE_UNSUPPORTED 0x10007
  43. #define ND_INTEL_STATUS_OQUERY_INPROGRESS 0x10007
  44. #define ND_INTEL_STATUS_OQUERY_SEQUENCE_ERR 0x20007
  45. #define ND_INTEL_SEC_STATE_ENABLED 0x02
  46. #define ND_INTEL_SEC_STATE_LOCKED 0x04
  47. #define ND_INTEL_SEC_STATE_FROZEN 0x08
  48. #define ND_INTEL_SEC_STATE_PLIMIT 0x10
  49. #define ND_INTEL_SEC_STATE_UNSUPPORTED 0x20
  50. #define ND_INTEL_SEC_STATE_OVERWRITE 0x40
  51. #define ND_INTEL_SEC_ESTATE_ENABLED 0x01
  52. #define ND_INTEL_SEC_ESTATE_PLIMIT 0x02
  53. struct nd_intel_get_security_state {
  54. u32 status;
  55. u8 extended_state;
  56. u8 reserved[3];
  57. u8 state;
  58. u8 reserved1[3];
  59. } __packed;
  60. struct nd_intel_set_passphrase {
  61. u8 old_pass[ND_INTEL_PASSPHRASE_SIZE];
  62. u8 new_pass[ND_INTEL_PASSPHRASE_SIZE];
  63. u32 status;
  64. } __packed;
  65. struct nd_intel_unlock_unit {
  66. u8 passphrase[ND_INTEL_PASSPHRASE_SIZE];
  67. u32 status;
  68. } __packed;
  69. struct nd_intel_disable_passphrase {
  70. u8 passphrase[ND_INTEL_PASSPHRASE_SIZE];
  71. u32 status;
  72. } __packed;
  73. struct nd_intel_freeze_lock {
  74. u32 status;
  75. } __packed;
  76. struct nd_intel_secure_erase {
  77. u8 passphrase[ND_INTEL_PASSPHRASE_SIZE];
  78. u32 status;
  79. } __packed;
  80. struct nd_intel_overwrite {
  81. u8 passphrase[ND_INTEL_PASSPHRASE_SIZE];
  82. u32 status;
  83. } __packed;
  84. struct nd_intel_query_overwrite {
  85. u32 status;
  86. } __packed;
  87. struct nd_intel_set_master_passphrase {
  88. u8 old_pass[ND_INTEL_PASSPHRASE_SIZE];
  89. u8 new_pass[ND_INTEL_PASSPHRASE_SIZE];
  90. u32 status;
  91. } __packed;
  92. struct nd_intel_master_secure_erase {
  93. u8 passphrase[ND_INTEL_PASSPHRASE_SIZE];
  94. u32 status;
  95. } __packed;
  96. #define ND_INTEL_FWA_IDLE 0
  97. #define ND_INTEL_FWA_ARMED 1
  98. #define ND_INTEL_FWA_BUSY 2
  99. #define ND_INTEL_DIMM_FWA_NONE 0
  100. #define ND_INTEL_DIMM_FWA_NOTSTAGED 1
  101. #define ND_INTEL_DIMM_FWA_SUCCESS 2
  102. #define ND_INTEL_DIMM_FWA_NEEDRESET 3
  103. #define ND_INTEL_DIMM_FWA_MEDIAFAILED 4
  104. #define ND_INTEL_DIMM_FWA_ABORT 5
  105. #define ND_INTEL_DIMM_FWA_NOTSUPP 6
  106. #define ND_INTEL_DIMM_FWA_ERROR 7
  107. struct nd_intel_fw_activate_dimminfo {
  108. u32 status;
  109. u16 result;
  110. u8 state;
  111. u8 reserved[7];
  112. } __packed;
  113. #define ND_INTEL_DIMM_FWA_ARM 1
  114. #define ND_INTEL_DIMM_FWA_DISARM 0
  115. struct nd_intel_fw_activate_arm {
  116. u8 activate_arm;
  117. u32 status;
  118. } __packed;
  119. /* Root device command payloads */
  120. #define ND_INTEL_BUS_FWA_CAP_FWQUIESCE (1 << 0)
  121. #define ND_INTEL_BUS_FWA_CAP_OSQUIESCE (1 << 1)
  122. #define ND_INTEL_BUS_FWA_CAP_RESET (1 << 2)
  123. struct nd_intel_bus_fw_activate_businfo {
  124. u32 status;
  125. u16 reserved;
  126. u8 state;
  127. u8 capability;
  128. u64 activate_tmo;
  129. u64 cpu_quiesce_tmo;
  130. u64 io_quiesce_tmo;
  131. u64 max_quiesce_tmo;
  132. } __packed;
  133. #define ND_INTEL_BUS_FWA_STATUS_NOARM (6 | 1 << 16)
  134. #define ND_INTEL_BUS_FWA_STATUS_BUSY (6 | 2 << 16)
  135. #define ND_INTEL_BUS_FWA_STATUS_NOFW (6 | 3 << 16)
  136. #define ND_INTEL_BUS_FWA_STATUS_TMO (6 | 4 << 16)
  137. #define ND_INTEL_BUS_FWA_STATUS_NOIDLE (6 | 5 << 16)
  138. #define ND_INTEL_BUS_FWA_STATUS_ABORT (6 | 6 << 16)
  139. #define ND_INTEL_BUS_FWA_IODEV_FORCE_IDLE (0)
  140. #define ND_INTEL_BUS_FWA_IODEV_OS_IDLE (1)
  141. struct nd_intel_bus_fw_activate {
  142. u8 iodev_state;
  143. u32 status;
  144. } __packed;
  145. extern const struct nvdimm_fw_ops *intel_fw_ops;
  146. extern const struct nvdimm_bus_fw_ops *intel_bus_fw_ops;
  147. #endif