acpi_lpss.c 35 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * ACPI support for Intel Lynxpoint LPSS.
  4. *
  5. * Copyright (C) 2013, Intel Corporation
  6. * Authors: Mika Westerberg <mika.westerberg@linux.intel.com>
  7. * Rafael J. Wysocki <rafael.j.wysocki@intel.com>
  8. */
  9. #include <linux/acpi.h>
  10. #include <linux/clkdev.h>
  11. #include <linux/clk-provider.h>
  12. #include <linux/dmi.h>
  13. #include <linux/err.h>
  14. #include <linux/io.h>
  15. #include <linux/mutex.h>
  16. #include <linux/pci.h>
  17. #include <linux/platform_device.h>
  18. #include <linux/platform_data/x86/clk-lpss.h>
  19. #include <linux/platform_data/x86/pmc_atom.h>
  20. #include <linux/pm_domain.h>
  21. #include <linux/pm_runtime.h>
  22. #include <linux/pwm.h>
  23. #include <linux/suspend.h>
  24. #include <linux/delay.h>
  25. #include "internal.h"
  26. #ifdef CONFIG_X86_INTEL_LPSS
  27. #include <asm/cpu_device_id.h>
  28. #include <asm/intel-family.h>
  29. #include <asm/iosf_mbi.h>
  30. #define LPSS_ADDR(desc) ((unsigned long)&desc)
  31. #define LPSS_CLK_SIZE 0x04
  32. #define LPSS_LTR_SIZE 0x18
  33. /* Offsets relative to LPSS_PRIVATE_OFFSET */
  34. #define LPSS_CLK_DIVIDER_DEF_MASK (BIT(1) | BIT(16))
  35. #define LPSS_RESETS 0x04
  36. #define LPSS_RESETS_RESET_FUNC BIT(0)
  37. #define LPSS_RESETS_RESET_APB BIT(1)
  38. #define LPSS_GENERAL 0x08
  39. #define LPSS_GENERAL_LTR_MODE_SW BIT(2)
  40. #define LPSS_GENERAL_UART_RTS_OVRD BIT(3)
  41. #define LPSS_SW_LTR 0x10
  42. #define LPSS_AUTO_LTR 0x14
  43. #define LPSS_LTR_SNOOP_REQ BIT(15)
  44. #define LPSS_LTR_SNOOP_MASK 0x0000FFFF
  45. #define LPSS_LTR_SNOOP_LAT_1US 0x800
  46. #define LPSS_LTR_SNOOP_LAT_32US 0xC00
  47. #define LPSS_LTR_SNOOP_LAT_SHIFT 5
  48. #define LPSS_LTR_SNOOP_LAT_CUTOFF 3000
  49. #define LPSS_LTR_MAX_VAL 0x3FF
  50. #define LPSS_TX_INT 0x20
  51. #define LPSS_TX_INT_MASK BIT(1)
  52. #define LPSS_PRV_REG_COUNT 9
  53. /* LPSS Flags */
  54. #define LPSS_CLK BIT(0)
  55. #define LPSS_CLK_GATE BIT(1)
  56. #define LPSS_CLK_DIVIDER BIT(2)
  57. #define LPSS_LTR BIT(3)
  58. #define LPSS_SAVE_CTX BIT(4)
  59. /*
  60. * For some devices the DSDT AML code for another device turns off the device
  61. * before our suspend handler runs, causing us to read/save all 1-s (0xffffffff)
  62. * as ctx register values.
  63. * Luckily these devices always use the same ctx register values, so we can
  64. * work around this by saving the ctx registers once on activation.
  65. */
  66. #define LPSS_SAVE_CTX_ONCE BIT(5)
  67. #define LPSS_NO_D3_DELAY BIT(6)
  68. struct lpss_private_data;
  69. struct lpss_device_desc {
  70. unsigned int flags;
  71. const char *clk_con_id;
  72. unsigned int prv_offset;
  73. size_t prv_size_override;
  74. struct property_entry *properties;
  75. void (*setup)(struct lpss_private_data *pdata);
  76. bool resume_from_noirq;
  77. };
  78. static const struct lpss_device_desc lpss_dma_desc = {
  79. .flags = LPSS_CLK,
  80. };
  81. struct lpss_private_data {
  82. struct acpi_device *adev;
  83. void __iomem *mmio_base;
  84. resource_size_t mmio_size;
  85. unsigned int fixed_clk_rate;
  86. struct clk *clk;
  87. const struct lpss_device_desc *dev_desc;
  88. u32 prv_reg_ctx[LPSS_PRV_REG_COUNT];
  89. };
  90. /* Devices which need to be in D3 before lpss_iosf_enter_d3_state() proceeds */
  91. static u32 pmc_atom_d3_mask = 0xfe000ffe;
  92. /* LPSS run time quirks */
  93. static unsigned int lpss_quirks;
  94. /*
  95. * LPSS_QUIRK_ALWAYS_POWER_ON: override power state for LPSS DMA device.
  96. *
  97. * The LPSS DMA controller has neither _PS0 nor _PS3 method. Moreover
  98. * it can be powered off automatically whenever the last LPSS device goes down.
  99. * In case of no power any access to the DMA controller will hang the system.
  100. * The behaviour is reproduced on some HP laptops based on Intel BayTrail as
  101. * well as on ASuS T100TA transformer.
  102. *
  103. * This quirk overrides power state of entire LPSS island to keep DMA powered
  104. * on whenever we have at least one other device in use.
  105. */
  106. #define LPSS_QUIRK_ALWAYS_POWER_ON BIT(0)
  107. /* UART Component Parameter Register */
  108. #define LPSS_UART_CPR 0xF4
  109. #define LPSS_UART_CPR_AFCE BIT(4)
  110. static void lpss_uart_setup(struct lpss_private_data *pdata)
  111. {
  112. unsigned int offset;
  113. u32 val;
  114. offset = pdata->dev_desc->prv_offset + LPSS_TX_INT;
  115. val = readl(pdata->mmio_base + offset);
  116. writel(val | LPSS_TX_INT_MASK, pdata->mmio_base + offset);
  117. val = readl(pdata->mmio_base + LPSS_UART_CPR);
  118. if (!(val & LPSS_UART_CPR_AFCE)) {
  119. offset = pdata->dev_desc->prv_offset + LPSS_GENERAL;
  120. val = readl(pdata->mmio_base + offset);
  121. val |= LPSS_GENERAL_UART_RTS_OVRD;
  122. writel(val, pdata->mmio_base + offset);
  123. }
  124. }
  125. static void lpss_deassert_reset(struct lpss_private_data *pdata)
  126. {
  127. unsigned int offset;
  128. u32 val;
  129. offset = pdata->dev_desc->prv_offset + LPSS_RESETS;
  130. val = readl(pdata->mmio_base + offset);
  131. val |= LPSS_RESETS_RESET_APB | LPSS_RESETS_RESET_FUNC;
  132. writel(val, pdata->mmio_base + offset);
  133. }
  134. /*
  135. * BYT PWM used for backlight control by the i915 driver on systems without
  136. * the Crystal Cove PMIC.
  137. */
  138. static struct pwm_lookup byt_pwm_lookup[] = {
  139. PWM_LOOKUP_WITH_MODULE("80860F09:00", 0, "0000:00:02.0",
  140. "pwm_soc_backlight", 0, PWM_POLARITY_NORMAL,
  141. "pwm-lpss-platform"),
  142. };
  143. static void byt_pwm_setup(struct lpss_private_data *pdata)
  144. {
  145. struct acpi_device *adev = pdata->adev;
  146. /* Only call pwm_add_table for the first PWM controller */
  147. if (!adev->pnp.unique_id || strcmp(adev->pnp.unique_id, "1"))
  148. return;
  149. pwm_add_table(byt_pwm_lookup, ARRAY_SIZE(byt_pwm_lookup));
  150. }
  151. #define LPSS_I2C_ENABLE 0x6c
  152. static void byt_i2c_setup(struct lpss_private_data *pdata)
  153. {
  154. const char *uid_str = acpi_device_uid(pdata->adev);
  155. acpi_handle handle = pdata->adev->handle;
  156. unsigned long long shared_host = 0;
  157. acpi_status status;
  158. long uid = 0;
  159. /* Expected to always be true, but better safe then sorry */
  160. if (uid_str)
  161. uid = simple_strtol(uid_str, NULL, 10);
  162. /* Detect I2C bus shared with PUNIT and ignore its d3 status */
  163. status = acpi_evaluate_integer(handle, "_SEM", NULL, &shared_host);
  164. if (ACPI_SUCCESS(status) && shared_host && uid)
  165. pmc_atom_d3_mask &= ~(BIT_LPSS2_F1_I2C1 << (uid - 1));
  166. lpss_deassert_reset(pdata);
  167. if (readl(pdata->mmio_base + pdata->dev_desc->prv_offset))
  168. pdata->fixed_clk_rate = 133000000;
  169. writel(0, pdata->mmio_base + LPSS_I2C_ENABLE);
  170. }
  171. /* BSW PWM used for backlight control by the i915 driver */
  172. static struct pwm_lookup bsw_pwm_lookup[] = {
  173. PWM_LOOKUP_WITH_MODULE("80862288:00", 0, "0000:00:02.0",
  174. "pwm_soc_backlight", 0, PWM_POLARITY_NORMAL,
  175. "pwm-lpss-platform"),
  176. };
  177. static void bsw_pwm_setup(struct lpss_private_data *pdata)
  178. {
  179. struct acpi_device *adev = pdata->adev;
  180. /* Only call pwm_add_table for the first PWM controller */
  181. if (!adev->pnp.unique_id || strcmp(adev->pnp.unique_id, "1"))
  182. return;
  183. pwm_add_table(bsw_pwm_lookup, ARRAY_SIZE(bsw_pwm_lookup));
  184. }
  185. static const struct lpss_device_desc lpt_dev_desc = {
  186. .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_LTR
  187. | LPSS_SAVE_CTX,
  188. .prv_offset = 0x800,
  189. };
  190. static const struct lpss_device_desc lpt_i2c_dev_desc = {
  191. .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_LTR | LPSS_SAVE_CTX,
  192. .prv_offset = 0x800,
  193. };
  194. static struct property_entry uart_properties[] = {
  195. PROPERTY_ENTRY_U32("reg-io-width", 4),
  196. PROPERTY_ENTRY_U32("reg-shift", 2),
  197. PROPERTY_ENTRY_BOOL("snps,uart-16550-compatible"),
  198. { },
  199. };
  200. static const struct lpss_device_desc lpt_uart_dev_desc = {
  201. .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_LTR
  202. | LPSS_SAVE_CTX,
  203. .clk_con_id = "baudclk",
  204. .prv_offset = 0x800,
  205. .setup = lpss_uart_setup,
  206. .properties = uart_properties,
  207. };
  208. static const struct lpss_device_desc lpt_sdio_dev_desc = {
  209. .flags = LPSS_LTR,
  210. .prv_offset = 0x1000,
  211. .prv_size_override = 0x1018,
  212. };
  213. static const struct lpss_device_desc byt_pwm_dev_desc = {
  214. .flags = LPSS_SAVE_CTX,
  215. .prv_offset = 0x800,
  216. .setup = byt_pwm_setup,
  217. };
  218. static const struct lpss_device_desc bsw_pwm_dev_desc = {
  219. .flags = LPSS_SAVE_CTX_ONCE | LPSS_NO_D3_DELAY,
  220. .prv_offset = 0x800,
  221. .setup = bsw_pwm_setup,
  222. .resume_from_noirq = true,
  223. };
  224. static const struct lpss_device_desc byt_uart_dev_desc = {
  225. .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX,
  226. .clk_con_id = "baudclk",
  227. .prv_offset = 0x800,
  228. .setup = lpss_uart_setup,
  229. .properties = uart_properties,
  230. };
  231. static const struct lpss_device_desc bsw_uart_dev_desc = {
  232. .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX
  233. | LPSS_NO_D3_DELAY,
  234. .clk_con_id = "baudclk",
  235. .prv_offset = 0x800,
  236. .setup = lpss_uart_setup,
  237. .properties = uart_properties,
  238. };
  239. static const struct lpss_device_desc byt_spi_dev_desc = {
  240. .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX,
  241. .prv_offset = 0x400,
  242. };
  243. static const struct lpss_device_desc byt_sdio_dev_desc = {
  244. .flags = LPSS_CLK,
  245. };
  246. static const struct lpss_device_desc byt_i2c_dev_desc = {
  247. .flags = LPSS_CLK | LPSS_SAVE_CTX,
  248. .prv_offset = 0x800,
  249. .setup = byt_i2c_setup,
  250. .resume_from_noirq = true,
  251. };
  252. static const struct lpss_device_desc bsw_i2c_dev_desc = {
  253. .flags = LPSS_CLK | LPSS_SAVE_CTX | LPSS_NO_D3_DELAY,
  254. .prv_offset = 0x800,
  255. .setup = byt_i2c_setup,
  256. .resume_from_noirq = true,
  257. };
  258. static const struct lpss_device_desc bsw_spi_dev_desc = {
  259. .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX
  260. | LPSS_NO_D3_DELAY,
  261. .prv_offset = 0x400,
  262. .setup = lpss_deassert_reset,
  263. };
  264. static const struct x86_cpu_id lpss_cpu_ids[] = {
  265. X86_MATCH_INTEL_FAM6_MODEL(ATOM_SILVERMONT, NULL),
  266. X86_MATCH_INTEL_FAM6_MODEL(ATOM_AIRMONT, NULL),
  267. {}
  268. };
  269. #else
  270. #define LPSS_ADDR(desc) (0UL)
  271. #endif /* CONFIG_X86_INTEL_LPSS */
  272. static const struct acpi_device_id acpi_lpss_device_ids[] = {
  273. /* Generic LPSS devices */
  274. { "INTL9C60", LPSS_ADDR(lpss_dma_desc) },
  275. /* Lynxpoint LPSS devices */
  276. { "INT33C0", LPSS_ADDR(lpt_dev_desc) },
  277. { "INT33C1", LPSS_ADDR(lpt_dev_desc) },
  278. { "INT33C2", LPSS_ADDR(lpt_i2c_dev_desc) },
  279. { "INT33C3", LPSS_ADDR(lpt_i2c_dev_desc) },
  280. { "INT33C4", LPSS_ADDR(lpt_uart_dev_desc) },
  281. { "INT33C5", LPSS_ADDR(lpt_uart_dev_desc) },
  282. { "INT33C6", LPSS_ADDR(lpt_sdio_dev_desc) },
  283. { "INT33C7", },
  284. /* BayTrail LPSS devices */
  285. { "80860F09", LPSS_ADDR(byt_pwm_dev_desc) },
  286. { "80860F0A", LPSS_ADDR(byt_uart_dev_desc) },
  287. { "80860F0E", LPSS_ADDR(byt_spi_dev_desc) },
  288. { "80860F14", LPSS_ADDR(byt_sdio_dev_desc) },
  289. { "80860F41", LPSS_ADDR(byt_i2c_dev_desc) },
  290. { "INT33B2", },
  291. { "INT33FC", },
  292. /* Braswell LPSS devices */
  293. { "80862286", LPSS_ADDR(lpss_dma_desc) },
  294. { "80862288", LPSS_ADDR(bsw_pwm_dev_desc) },
  295. { "8086228A", LPSS_ADDR(bsw_uart_dev_desc) },
  296. { "8086228E", LPSS_ADDR(bsw_spi_dev_desc) },
  297. { "808622C0", LPSS_ADDR(lpss_dma_desc) },
  298. { "808622C1", LPSS_ADDR(bsw_i2c_dev_desc) },
  299. /* Broadwell LPSS devices */
  300. { "INT3430", LPSS_ADDR(lpt_dev_desc) },
  301. { "INT3431", LPSS_ADDR(lpt_dev_desc) },
  302. { "INT3432", LPSS_ADDR(lpt_i2c_dev_desc) },
  303. { "INT3433", LPSS_ADDR(lpt_i2c_dev_desc) },
  304. { "INT3434", LPSS_ADDR(lpt_uart_dev_desc) },
  305. { "INT3435", LPSS_ADDR(lpt_uart_dev_desc) },
  306. { "INT3436", LPSS_ADDR(lpt_sdio_dev_desc) },
  307. { "INT3437", },
  308. /* Wildcat Point LPSS devices */
  309. { "INT3438", LPSS_ADDR(lpt_dev_desc) },
  310. { }
  311. };
  312. #ifdef CONFIG_X86_INTEL_LPSS
  313. static int is_memory(struct acpi_resource *res, void *not_used)
  314. {
  315. struct resource r;
  316. return !acpi_dev_resource_memory(res, &r);
  317. }
  318. /* LPSS main clock device. */
  319. static struct platform_device *lpss_clk_dev;
  320. static inline void lpt_register_clock_device(void)
  321. {
  322. lpss_clk_dev = platform_device_register_simple("clk-lpt", -1, NULL, 0);
  323. }
  324. static int register_device_clock(struct acpi_device *adev,
  325. struct lpss_private_data *pdata)
  326. {
  327. const struct lpss_device_desc *dev_desc = pdata->dev_desc;
  328. const char *devname = dev_name(&adev->dev);
  329. struct clk *clk;
  330. struct lpss_clk_data *clk_data;
  331. const char *parent, *clk_name;
  332. void __iomem *prv_base;
  333. if (!lpss_clk_dev)
  334. lpt_register_clock_device();
  335. clk_data = platform_get_drvdata(lpss_clk_dev);
  336. if (!clk_data)
  337. return -ENODEV;
  338. clk = clk_data->clk;
  339. if (!pdata->mmio_base
  340. || pdata->mmio_size < dev_desc->prv_offset + LPSS_CLK_SIZE)
  341. return -ENODATA;
  342. parent = clk_data->name;
  343. prv_base = pdata->mmio_base + dev_desc->prv_offset;
  344. if (pdata->fixed_clk_rate) {
  345. clk = clk_register_fixed_rate(NULL, devname, parent, 0,
  346. pdata->fixed_clk_rate);
  347. goto out;
  348. }
  349. if (dev_desc->flags & LPSS_CLK_GATE) {
  350. clk = clk_register_gate(NULL, devname, parent, 0,
  351. prv_base, 0, 0, NULL);
  352. parent = devname;
  353. }
  354. if (dev_desc->flags & LPSS_CLK_DIVIDER) {
  355. /* Prevent division by zero */
  356. if (!readl(prv_base))
  357. writel(LPSS_CLK_DIVIDER_DEF_MASK, prv_base);
  358. clk_name = kasprintf(GFP_KERNEL, "%s-div", devname);
  359. if (!clk_name)
  360. return -ENOMEM;
  361. clk = clk_register_fractional_divider(NULL, clk_name, parent,
  362. 0, prv_base,
  363. 1, 15, 16, 15, 0, NULL);
  364. parent = clk_name;
  365. clk_name = kasprintf(GFP_KERNEL, "%s-update", devname);
  366. if (!clk_name) {
  367. kfree(parent);
  368. return -ENOMEM;
  369. }
  370. clk = clk_register_gate(NULL, clk_name, parent,
  371. CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE,
  372. prv_base, 31, 0, NULL);
  373. kfree(parent);
  374. kfree(clk_name);
  375. }
  376. out:
  377. if (IS_ERR(clk))
  378. return PTR_ERR(clk);
  379. pdata->clk = clk;
  380. clk_register_clkdev(clk, dev_desc->clk_con_id, devname);
  381. return 0;
  382. }
  383. struct lpss_device_links {
  384. const char *supplier_hid;
  385. const char *supplier_uid;
  386. const char *consumer_hid;
  387. const char *consumer_uid;
  388. u32 flags;
  389. const struct dmi_system_id *dep_missing_ids;
  390. };
  391. /* Please keep this list sorted alphabetically by vendor and model */
  392. static const struct dmi_system_id i2c1_dep_missing_dmi_ids[] = {
  393. {
  394. .matches = {
  395. DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."),
  396. DMI_MATCH(DMI_PRODUCT_NAME, "T200TA"),
  397. },
  398. },
  399. {}
  400. };
  401. /*
  402. * The _DEP method is used to identify dependencies but instead of creating
  403. * device links for every handle in _DEP, only links in the following list are
  404. * created. That is necessary because, in the general case, _DEP can refer to
  405. * devices that might not have drivers, or that are on different buses, or where
  406. * the supplier is not enumerated until after the consumer is probed.
  407. */
  408. static const struct lpss_device_links lpss_device_links[] = {
  409. /* CHT External sdcard slot controller depends on PMIC I2C ctrl */
  410. {"808622C1", "7", "80860F14", "3", DL_FLAG_PM_RUNTIME},
  411. /* CHT iGPU depends on PMIC I2C controller */
  412. {"808622C1", "7", "LNXVIDEO", NULL, DL_FLAG_PM_RUNTIME},
  413. /* BYT iGPU depends on the Embedded Controller I2C controller (UID 1) */
  414. {"80860F41", "1", "LNXVIDEO", NULL, DL_FLAG_PM_RUNTIME,
  415. i2c1_dep_missing_dmi_ids},
  416. /* BYT CR iGPU depends on PMIC I2C controller (UID 5 on CR) */
  417. {"80860F41", "5", "LNXVIDEO", NULL, DL_FLAG_PM_RUNTIME},
  418. /* BYT iGPU depends on PMIC I2C controller (UID 7 on non CR) */
  419. {"80860F41", "7", "LNXVIDEO", NULL, DL_FLAG_PM_RUNTIME},
  420. };
  421. static bool acpi_lpss_is_supplier(struct acpi_device *adev,
  422. const struct lpss_device_links *link)
  423. {
  424. return acpi_dev_hid_uid_match(adev, link->supplier_hid, link->supplier_uid);
  425. }
  426. static bool acpi_lpss_is_consumer(struct acpi_device *adev,
  427. const struct lpss_device_links *link)
  428. {
  429. return acpi_dev_hid_uid_match(adev, link->consumer_hid, link->consumer_uid);
  430. }
  431. struct hid_uid {
  432. const char *hid;
  433. const char *uid;
  434. };
  435. static int match_hid_uid(struct device *dev, const void *data)
  436. {
  437. struct acpi_device *adev = ACPI_COMPANION(dev);
  438. const struct hid_uid *id = data;
  439. if (!adev)
  440. return 0;
  441. return acpi_dev_hid_uid_match(adev, id->hid, id->uid);
  442. }
  443. static struct device *acpi_lpss_find_device(const char *hid, const char *uid)
  444. {
  445. struct device *dev;
  446. struct hid_uid data = {
  447. .hid = hid,
  448. .uid = uid,
  449. };
  450. dev = bus_find_device(&platform_bus_type, NULL, &data, match_hid_uid);
  451. if (dev)
  452. return dev;
  453. return bus_find_device(&pci_bus_type, NULL, &data, match_hid_uid);
  454. }
  455. static bool acpi_lpss_dep(struct acpi_device *adev, acpi_handle handle)
  456. {
  457. struct acpi_handle_list dep_devices;
  458. acpi_status status;
  459. int i;
  460. if (!acpi_has_method(adev->handle, "_DEP"))
  461. return false;
  462. status = acpi_evaluate_reference(adev->handle, "_DEP", NULL,
  463. &dep_devices);
  464. if (ACPI_FAILURE(status)) {
  465. dev_dbg(&adev->dev, "Failed to evaluate _DEP.\n");
  466. return false;
  467. }
  468. for (i = 0; i < dep_devices.count; i++) {
  469. if (dep_devices.handles[i] == handle)
  470. return true;
  471. }
  472. return false;
  473. }
  474. static void acpi_lpss_link_consumer(struct device *dev1,
  475. const struct lpss_device_links *link)
  476. {
  477. struct device *dev2;
  478. dev2 = acpi_lpss_find_device(link->consumer_hid, link->consumer_uid);
  479. if (!dev2)
  480. return;
  481. if ((link->dep_missing_ids && dmi_check_system(link->dep_missing_ids))
  482. || acpi_lpss_dep(ACPI_COMPANION(dev2), ACPI_HANDLE(dev1)))
  483. device_link_add(dev2, dev1, link->flags);
  484. put_device(dev2);
  485. }
  486. static void acpi_lpss_link_supplier(struct device *dev1,
  487. const struct lpss_device_links *link)
  488. {
  489. struct device *dev2;
  490. dev2 = acpi_lpss_find_device(link->supplier_hid, link->supplier_uid);
  491. if (!dev2)
  492. return;
  493. if ((link->dep_missing_ids && dmi_check_system(link->dep_missing_ids))
  494. || acpi_lpss_dep(ACPI_COMPANION(dev1), ACPI_HANDLE(dev2)))
  495. device_link_add(dev1, dev2, link->flags);
  496. put_device(dev2);
  497. }
  498. static void acpi_lpss_create_device_links(struct acpi_device *adev,
  499. struct platform_device *pdev)
  500. {
  501. int i;
  502. for (i = 0; i < ARRAY_SIZE(lpss_device_links); i++) {
  503. const struct lpss_device_links *link = &lpss_device_links[i];
  504. if (acpi_lpss_is_supplier(adev, link))
  505. acpi_lpss_link_consumer(&pdev->dev, link);
  506. if (acpi_lpss_is_consumer(adev, link))
  507. acpi_lpss_link_supplier(&pdev->dev, link);
  508. }
  509. }
  510. static int acpi_lpss_create_device(struct acpi_device *adev,
  511. const struct acpi_device_id *id)
  512. {
  513. const struct lpss_device_desc *dev_desc;
  514. struct lpss_private_data *pdata;
  515. struct resource_entry *rentry;
  516. struct list_head resource_list;
  517. struct platform_device *pdev;
  518. int ret;
  519. dev_desc = (const struct lpss_device_desc *)id->driver_data;
  520. if (!dev_desc) {
  521. pdev = acpi_create_platform_device(adev, NULL);
  522. return IS_ERR_OR_NULL(pdev) ? PTR_ERR(pdev) : 1;
  523. }
  524. pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
  525. if (!pdata)
  526. return -ENOMEM;
  527. INIT_LIST_HEAD(&resource_list);
  528. ret = acpi_dev_get_resources(adev, &resource_list, is_memory, NULL);
  529. if (ret < 0)
  530. goto err_out;
  531. list_for_each_entry(rentry, &resource_list, node)
  532. if (resource_type(rentry->res) == IORESOURCE_MEM) {
  533. if (dev_desc->prv_size_override)
  534. pdata->mmio_size = dev_desc->prv_size_override;
  535. else
  536. pdata->mmio_size = resource_size(rentry->res);
  537. pdata->mmio_base = ioremap(rentry->res->start,
  538. pdata->mmio_size);
  539. break;
  540. }
  541. acpi_dev_free_resource_list(&resource_list);
  542. if (!pdata->mmio_base) {
  543. /* Avoid acpi_bus_attach() instantiating a pdev for this dev. */
  544. adev->pnp.type.platform_id = 0;
  545. /* Skip the device, but continue the namespace scan. */
  546. ret = 0;
  547. goto err_out;
  548. }
  549. pdata->adev = adev;
  550. pdata->dev_desc = dev_desc;
  551. if (dev_desc->setup)
  552. dev_desc->setup(pdata);
  553. if (dev_desc->flags & LPSS_CLK) {
  554. ret = register_device_clock(adev, pdata);
  555. if (ret) {
  556. /* Skip the device, but continue the namespace scan. */
  557. ret = 0;
  558. goto err_out;
  559. }
  560. }
  561. /*
  562. * This works around a known issue in ACPI tables where LPSS devices
  563. * have _PS0 and _PS3 without _PSC (and no power resources), so
  564. * acpi_bus_init_power() will assume that the BIOS has put them into D0.
  565. */
  566. acpi_device_fix_up_power(adev);
  567. adev->driver_data = pdata;
  568. pdev = acpi_create_platform_device(adev, dev_desc->properties);
  569. if (!IS_ERR_OR_NULL(pdev)) {
  570. acpi_lpss_create_device_links(adev, pdev);
  571. return 1;
  572. }
  573. ret = PTR_ERR(pdev);
  574. adev->driver_data = NULL;
  575. err_out:
  576. kfree(pdata);
  577. return ret;
  578. }
  579. static u32 __lpss_reg_read(struct lpss_private_data *pdata, unsigned int reg)
  580. {
  581. return readl(pdata->mmio_base + pdata->dev_desc->prv_offset + reg);
  582. }
  583. static void __lpss_reg_write(u32 val, struct lpss_private_data *pdata,
  584. unsigned int reg)
  585. {
  586. writel(val, pdata->mmio_base + pdata->dev_desc->prv_offset + reg);
  587. }
  588. static int lpss_reg_read(struct device *dev, unsigned int reg, u32 *val)
  589. {
  590. struct acpi_device *adev;
  591. struct lpss_private_data *pdata;
  592. unsigned long flags;
  593. int ret;
  594. ret = acpi_bus_get_device(ACPI_HANDLE(dev), &adev);
  595. if (WARN_ON(ret))
  596. return ret;
  597. spin_lock_irqsave(&dev->power.lock, flags);
  598. if (pm_runtime_suspended(dev)) {
  599. ret = -EAGAIN;
  600. goto out;
  601. }
  602. pdata = acpi_driver_data(adev);
  603. if (WARN_ON(!pdata || !pdata->mmio_base)) {
  604. ret = -ENODEV;
  605. goto out;
  606. }
  607. *val = __lpss_reg_read(pdata, reg);
  608. out:
  609. spin_unlock_irqrestore(&dev->power.lock, flags);
  610. return ret;
  611. }
  612. static ssize_t lpss_ltr_show(struct device *dev, struct device_attribute *attr,
  613. char *buf)
  614. {
  615. u32 ltr_value = 0;
  616. unsigned int reg;
  617. int ret;
  618. reg = strcmp(attr->attr.name, "auto_ltr") ? LPSS_SW_LTR : LPSS_AUTO_LTR;
  619. ret = lpss_reg_read(dev, reg, &ltr_value);
  620. if (ret)
  621. return ret;
  622. return snprintf(buf, PAGE_SIZE, "%08x\n", ltr_value);
  623. }
  624. static ssize_t lpss_ltr_mode_show(struct device *dev,
  625. struct device_attribute *attr, char *buf)
  626. {
  627. u32 ltr_mode = 0;
  628. char *outstr;
  629. int ret;
  630. ret = lpss_reg_read(dev, LPSS_GENERAL, &ltr_mode);
  631. if (ret)
  632. return ret;
  633. outstr = (ltr_mode & LPSS_GENERAL_LTR_MODE_SW) ? "sw" : "auto";
  634. return sprintf(buf, "%s\n", outstr);
  635. }
  636. static DEVICE_ATTR(auto_ltr, S_IRUSR, lpss_ltr_show, NULL);
  637. static DEVICE_ATTR(sw_ltr, S_IRUSR, lpss_ltr_show, NULL);
  638. static DEVICE_ATTR(ltr_mode, S_IRUSR, lpss_ltr_mode_show, NULL);
  639. static struct attribute *lpss_attrs[] = {
  640. &dev_attr_auto_ltr.attr,
  641. &dev_attr_sw_ltr.attr,
  642. &dev_attr_ltr_mode.attr,
  643. NULL,
  644. };
  645. static const struct attribute_group lpss_attr_group = {
  646. .attrs = lpss_attrs,
  647. .name = "lpss_ltr",
  648. };
  649. static void acpi_lpss_set_ltr(struct device *dev, s32 val)
  650. {
  651. struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
  652. u32 ltr_mode, ltr_val;
  653. ltr_mode = __lpss_reg_read(pdata, LPSS_GENERAL);
  654. if (val < 0) {
  655. if (ltr_mode & LPSS_GENERAL_LTR_MODE_SW) {
  656. ltr_mode &= ~LPSS_GENERAL_LTR_MODE_SW;
  657. __lpss_reg_write(ltr_mode, pdata, LPSS_GENERAL);
  658. }
  659. return;
  660. }
  661. ltr_val = __lpss_reg_read(pdata, LPSS_SW_LTR) & ~LPSS_LTR_SNOOP_MASK;
  662. if (val >= LPSS_LTR_SNOOP_LAT_CUTOFF) {
  663. ltr_val |= LPSS_LTR_SNOOP_LAT_32US;
  664. val = LPSS_LTR_MAX_VAL;
  665. } else if (val > LPSS_LTR_MAX_VAL) {
  666. ltr_val |= LPSS_LTR_SNOOP_LAT_32US | LPSS_LTR_SNOOP_REQ;
  667. val >>= LPSS_LTR_SNOOP_LAT_SHIFT;
  668. } else {
  669. ltr_val |= LPSS_LTR_SNOOP_LAT_1US | LPSS_LTR_SNOOP_REQ;
  670. }
  671. ltr_val |= val;
  672. __lpss_reg_write(ltr_val, pdata, LPSS_SW_LTR);
  673. if (!(ltr_mode & LPSS_GENERAL_LTR_MODE_SW)) {
  674. ltr_mode |= LPSS_GENERAL_LTR_MODE_SW;
  675. __lpss_reg_write(ltr_mode, pdata, LPSS_GENERAL);
  676. }
  677. }
  678. #ifdef CONFIG_PM
  679. /**
  680. * acpi_lpss_save_ctx() - Save the private registers of LPSS device
  681. * @dev: LPSS device
  682. * @pdata: pointer to the private data of the LPSS device
  683. *
  684. * Most LPSS devices have private registers which may loose their context when
  685. * the device is powered down. acpi_lpss_save_ctx() saves those registers into
  686. * prv_reg_ctx array.
  687. */
  688. static void acpi_lpss_save_ctx(struct device *dev,
  689. struct lpss_private_data *pdata)
  690. {
  691. unsigned int i;
  692. for (i = 0; i < LPSS_PRV_REG_COUNT; i++) {
  693. unsigned long offset = i * sizeof(u32);
  694. pdata->prv_reg_ctx[i] = __lpss_reg_read(pdata, offset);
  695. dev_dbg(dev, "saving 0x%08x from LPSS reg at offset 0x%02lx\n",
  696. pdata->prv_reg_ctx[i], offset);
  697. }
  698. }
  699. /**
  700. * acpi_lpss_restore_ctx() - Restore the private registers of LPSS device
  701. * @dev: LPSS device
  702. * @pdata: pointer to the private data of the LPSS device
  703. *
  704. * Restores the registers that were previously stored with acpi_lpss_save_ctx().
  705. */
  706. static void acpi_lpss_restore_ctx(struct device *dev,
  707. struct lpss_private_data *pdata)
  708. {
  709. unsigned int i;
  710. for (i = 0; i < LPSS_PRV_REG_COUNT; i++) {
  711. unsigned long offset = i * sizeof(u32);
  712. __lpss_reg_write(pdata->prv_reg_ctx[i], pdata, offset);
  713. dev_dbg(dev, "restoring 0x%08x to LPSS reg at offset 0x%02lx\n",
  714. pdata->prv_reg_ctx[i], offset);
  715. }
  716. }
  717. static void acpi_lpss_d3_to_d0_delay(struct lpss_private_data *pdata)
  718. {
  719. /*
  720. * The following delay is needed or the subsequent write operations may
  721. * fail. The LPSS devices are actually PCI devices and the PCI spec
  722. * expects 10ms delay before the device can be accessed after D3 to D0
  723. * transition. However some platforms like BSW does not need this delay.
  724. */
  725. unsigned int delay = 10; /* default 10ms delay */
  726. if (pdata->dev_desc->flags & LPSS_NO_D3_DELAY)
  727. delay = 0;
  728. msleep(delay);
  729. }
  730. static int acpi_lpss_activate(struct device *dev)
  731. {
  732. struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
  733. int ret;
  734. ret = acpi_dev_resume(dev);
  735. if (ret)
  736. return ret;
  737. acpi_lpss_d3_to_d0_delay(pdata);
  738. /*
  739. * This is called only on ->probe() stage where a device is either in
  740. * known state defined by BIOS or most likely powered off. Due to this
  741. * we have to deassert reset line to be sure that ->probe() will
  742. * recognize the device.
  743. */
  744. if (pdata->dev_desc->flags & (LPSS_SAVE_CTX | LPSS_SAVE_CTX_ONCE))
  745. lpss_deassert_reset(pdata);
  746. #ifdef CONFIG_PM
  747. if (pdata->dev_desc->flags & LPSS_SAVE_CTX_ONCE)
  748. acpi_lpss_save_ctx(dev, pdata);
  749. #endif
  750. return 0;
  751. }
  752. static void acpi_lpss_dismiss(struct device *dev)
  753. {
  754. acpi_dev_suspend(dev, false);
  755. }
  756. /* IOSF SB for LPSS island */
  757. #define LPSS_IOSF_UNIT_LPIOEP 0xA0
  758. #define LPSS_IOSF_UNIT_LPIO1 0xAB
  759. #define LPSS_IOSF_UNIT_LPIO2 0xAC
  760. #define LPSS_IOSF_PMCSR 0x84
  761. #define LPSS_PMCSR_D0 0
  762. #define LPSS_PMCSR_D3hot 3
  763. #define LPSS_PMCSR_Dx_MASK GENMASK(1, 0)
  764. #define LPSS_IOSF_GPIODEF0 0x154
  765. #define LPSS_GPIODEF0_DMA1_D3 BIT(2)
  766. #define LPSS_GPIODEF0_DMA2_D3 BIT(3)
  767. #define LPSS_GPIODEF0_DMA_D3_MASK GENMASK(3, 2)
  768. #define LPSS_GPIODEF0_DMA_LLP BIT(13)
  769. static DEFINE_MUTEX(lpss_iosf_mutex);
  770. static bool lpss_iosf_d3_entered = true;
  771. static void lpss_iosf_enter_d3_state(void)
  772. {
  773. u32 value1 = 0;
  774. u32 mask1 = LPSS_GPIODEF0_DMA_D3_MASK | LPSS_GPIODEF0_DMA_LLP;
  775. u32 value2 = LPSS_PMCSR_D3hot;
  776. u32 mask2 = LPSS_PMCSR_Dx_MASK;
  777. /*
  778. * PMC provides an information about actual status of the LPSS devices.
  779. * Here we read the values related to LPSS power island, i.e. LPSS
  780. * devices, excluding both LPSS DMA controllers, along with SCC domain.
  781. */
  782. u32 func_dis, d3_sts_0, pmc_status;
  783. int ret;
  784. ret = pmc_atom_read(PMC_FUNC_DIS, &func_dis);
  785. if (ret)
  786. return;
  787. mutex_lock(&lpss_iosf_mutex);
  788. ret = pmc_atom_read(PMC_D3_STS_0, &d3_sts_0);
  789. if (ret)
  790. goto exit;
  791. /*
  792. * Get the status of entire LPSS power island per device basis.
  793. * Shutdown both LPSS DMA controllers if and only if all other devices
  794. * are already in D3hot.
  795. */
  796. pmc_status = (~(d3_sts_0 | func_dis)) & pmc_atom_d3_mask;
  797. if (pmc_status)
  798. goto exit;
  799. iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO1, MBI_CFG_WRITE,
  800. LPSS_IOSF_PMCSR, value2, mask2);
  801. iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO2, MBI_CFG_WRITE,
  802. LPSS_IOSF_PMCSR, value2, mask2);
  803. iosf_mbi_modify(LPSS_IOSF_UNIT_LPIOEP, MBI_CR_WRITE,
  804. LPSS_IOSF_GPIODEF0, value1, mask1);
  805. lpss_iosf_d3_entered = true;
  806. exit:
  807. mutex_unlock(&lpss_iosf_mutex);
  808. }
  809. static void lpss_iosf_exit_d3_state(void)
  810. {
  811. u32 value1 = LPSS_GPIODEF0_DMA1_D3 | LPSS_GPIODEF0_DMA2_D3 |
  812. LPSS_GPIODEF0_DMA_LLP;
  813. u32 mask1 = LPSS_GPIODEF0_DMA_D3_MASK | LPSS_GPIODEF0_DMA_LLP;
  814. u32 value2 = LPSS_PMCSR_D0;
  815. u32 mask2 = LPSS_PMCSR_Dx_MASK;
  816. mutex_lock(&lpss_iosf_mutex);
  817. if (!lpss_iosf_d3_entered)
  818. goto exit;
  819. lpss_iosf_d3_entered = false;
  820. iosf_mbi_modify(LPSS_IOSF_UNIT_LPIOEP, MBI_CR_WRITE,
  821. LPSS_IOSF_GPIODEF0, value1, mask1);
  822. iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO2, MBI_CFG_WRITE,
  823. LPSS_IOSF_PMCSR, value2, mask2);
  824. iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO1, MBI_CFG_WRITE,
  825. LPSS_IOSF_PMCSR, value2, mask2);
  826. exit:
  827. mutex_unlock(&lpss_iosf_mutex);
  828. }
  829. static int acpi_lpss_suspend(struct device *dev, bool wakeup)
  830. {
  831. struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
  832. int ret;
  833. if (pdata->dev_desc->flags & LPSS_SAVE_CTX)
  834. acpi_lpss_save_ctx(dev, pdata);
  835. ret = acpi_dev_suspend(dev, wakeup);
  836. /*
  837. * This call must be last in the sequence, otherwise PMC will return
  838. * wrong status for devices being about to be powered off. See
  839. * lpss_iosf_enter_d3_state() for further information.
  840. */
  841. if (acpi_target_system_state() == ACPI_STATE_S0 &&
  842. lpss_quirks & LPSS_QUIRK_ALWAYS_POWER_ON && iosf_mbi_available())
  843. lpss_iosf_enter_d3_state();
  844. return ret;
  845. }
  846. static int acpi_lpss_resume(struct device *dev)
  847. {
  848. struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
  849. int ret;
  850. /*
  851. * This call is kept first to be in symmetry with
  852. * acpi_lpss_runtime_suspend() one.
  853. */
  854. if (lpss_quirks & LPSS_QUIRK_ALWAYS_POWER_ON && iosf_mbi_available())
  855. lpss_iosf_exit_d3_state();
  856. ret = acpi_dev_resume(dev);
  857. if (ret)
  858. return ret;
  859. acpi_lpss_d3_to_d0_delay(pdata);
  860. if (pdata->dev_desc->flags & (LPSS_SAVE_CTX | LPSS_SAVE_CTX_ONCE))
  861. acpi_lpss_restore_ctx(dev, pdata);
  862. return 0;
  863. }
  864. #ifdef CONFIG_PM_SLEEP
  865. static int acpi_lpss_do_suspend_late(struct device *dev)
  866. {
  867. int ret;
  868. if (dev_pm_skip_suspend(dev))
  869. return 0;
  870. ret = pm_generic_suspend_late(dev);
  871. return ret ? ret : acpi_lpss_suspend(dev, device_may_wakeup(dev));
  872. }
  873. static int acpi_lpss_suspend_late(struct device *dev)
  874. {
  875. struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
  876. if (pdata->dev_desc->resume_from_noirq)
  877. return 0;
  878. return acpi_lpss_do_suspend_late(dev);
  879. }
  880. static int acpi_lpss_suspend_noirq(struct device *dev)
  881. {
  882. struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
  883. int ret;
  884. if (pdata->dev_desc->resume_from_noirq) {
  885. /*
  886. * The driver's ->suspend_late callback will be invoked by
  887. * acpi_lpss_do_suspend_late(), with the assumption that the
  888. * driver really wanted to run that code in ->suspend_noirq, but
  889. * it could not run after acpi_dev_suspend() and the driver
  890. * expected the latter to be called in the "late" phase.
  891. */
  892. ret = acpi_lpss_do_suspend_late(dev);
  893. if (ret)
  894. return ret;
  895. }
  896. return acpi_subsys_suspend_noirq(dev);
  897. }
  898. static int acpi_lpss_do_resume_early(struct device *dev)
  899. {
  900. int ret = acpi_lpss_resume(dev);
  901. return ret ? ret : pm_generic_resume_early(dev);
  902. }
  903. static int acpi_lpss_resume_early(struct device *dev)
  904. {
  905. struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
  906. if (pdata->dev_desc->resume_from_noirq)
  907. return 0;
  908. if (dev_pm_skip_resume(dev))
  909. return 0;
  910. return acpi_lpss_do_resume_early(dev);
  911. }
  912. static int acpi_lpss_resume_noirq(struct device *dev)
  913. {
  914. struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
  915. int ret;
  916. /* Follow acpi_subsys_resume_noirq(). */
  917. if (dev_pm_skip_resume(dev))
  918. return 0;
  919. ret = pm_generic_resume_noirq(dev);
  920. if (ret)
  921. return ret;
  922. if (!pdata->dev_desc->resume_from_noirq)
  923. return 0;
  924. /*
  925. * The driver's ->resume_early callback will be invoked by
  926. * acpi_lpss_do_resume_early(), with the assumption that the driver
  927. * really wanted to run that code in ->resume_noirq, but it could not
  928. * run before acpi_dev_resume() and the driver expected the latter to be
  929. * called in the "early" phase.
  930. */
  931. return acpi_lpss_do_resume_early(dev);
  932. }
  933. static int acpi_lpss_do_restore_early(struct device *dev)
  934. {
  935. int ret = acpi_lpss_resume(dev);
  936. return ret ? ret : pm_generic_restore_early(dev);
  937. }
  938. static int acpi_lpss_restore_early(struct device *dev)
  939. {
  940. struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
  941. if (pdata->dev_desc->resume_from_noirq)
  942. return 0;
  943. return acpi_lpss_do_restore_early(dev);
  944. }
  945. static int acpi_lpss_restore_noirq(struct device *dev)
  946. {
  947. struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
  948. int ret;
  949. ret = pm_generic_restore_noirq(dev);
  950. if (ret)
  951. return ret;
  952. if (!pdata->dev_desc->resume_from_noirq)
  953. return 0;
  954. /* This is analogous to what happens in acpi_lpss_resume_noirq(). */
  955. return acpi_lpss_do_restore_early(dev);
  956. }
  957. static int acpi_lpss_do_poweroff_late(struct device *dev)
  958. {
  959. int ret = pm_generic_poweroff_late(dev);
  960. return ret ? ret : acpi_lpss_suspend(dev, device_may_wakeup(dev));
  961. }
  962. static int acpi_lpss_poweroff_late(struct device *dev)
  963. {
  964. struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
  965. if (dev_pm_skip_suspend(dev))
  966. return 0;
  967. if (pdata->dev_desc->resume_from_noirq)
  968. return 0;
  969. return acpi_lpss_do_poweroff_late(dev);
  970. }
  971. static int acpi_lpss_poweroff_noirq(struct device *dev)
  972. {
  973. struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
  974. if (dev_pm_skip_suspend(dev))
  975. return 0;
  976. if (pdata->dev_desc->resume_from_noirq) {
  977. /* This is analogous to the acpi_lpss_suspend_noirq() case. */
  978. int ret = acpi_lpss_do_poweroff_late(dev);
  979. if (ret)
  980. return ret;
  981. }
  982. return pm_generic_poweroff_noirq(dev);
  983. }
  984. #endif /* CONFIG_PM_SLEEP */
  985. static int acpi_lpss_runtime_suspend(struct device *dev)
  986. {
  987. int ret = pm_generic_runtime_suspend(dev);
  988. return ret ? ret : acpi_lpss_suspend(dev, true);
  989. }
  990. static int acpi_lpss_runtime_resume(struct device *dev)
  991. {
  992. int ret = acpi_lpss_resume(dev);
  993. return ret ? ret : pm_generic_runtime_resume(dev);
  994. }
  995. #endif /* CONFIG_PM */
  996. static struct dev_pm_domain acpi_lpss_pm_domain = {
  997. #ifdef CONFIG_PM
  998. .activate = acpi_lpss_activate,
  999. .dismiss = acpi_lpss_dismiss,
  1000. #endif
  1001. .ops = {
  1002. #ifdef CONFIG_PM
  1003. #ifdef CONFIG_PM_SLEEP
  1004. .prepare = acpi_subsys_prepare,
  1005. .complete = acpi_subsys_complete,
  1006. .suspend = acpi_subsys_suspend,
  1007. .suspend_late = acpi_lpss_suspend_late,
  1008. .suspend_noirq = acpi_lpss_suspend_noirq,
  1009. .resume_noirq = acpi_lpss_resume_noirq,
  1010. .resume_early = acpi_lpss_resume_early,
  1011. .freeze = acpi_subsys_freeze,
  1012. .poweroff = acpi_subsys_poweroff,
  1013. .poweroff_late = acpi_lpss_poweroff_late,
  1014. .poweroff_noirq = acpi_lpss_poweroff_noirq,
  1015. .restore_noirq = acpi_lpss_restore_noirq,
  1016. .restore_early = acpi_lpss_restore_early,
  1017. #endif
  1018. .runtime_suspend = acpi_lpss_runtime_suspend,
  1019. .runtime_resume = acpi_lpss_runtime_resume,
  1020. #endif
  1021. },
  1022. };
  1023. static int acpi_lpss_platform_notify(struct notifier_block *nb,
  1024. unsigned long action, void *data)
  1025. {
  1026. struct platform_device *pdev = to_platform_device(data);
  1027. struct lpss_private_data *pdata;
  1028. struct acpi_device *adev;
  1029. const struct acpi_device_id *id;
  1030. id = acpi_match_device(acpi_lpss_device_ids, &pdev->dev);
  1031. if (!id || !id->driver_data)
  1032. return 0;
  1033. if (acpi_bus_get_device(ACPI_HANDLE(&pdev->dev), &adev))
  1034. return 0;
  1035. pdata = acpi_driver_data(adev);
  1036. if (!pdata)
  1037. return 0;
  1038. if (pdata->mmio_base &&
  1039. pdata->mmio_size < pdata->dev_desc->prv_offset + LPSS_LTR_SIZE) {
  1040. dev_err(&pdev->dev, "MMIO size insufficient to access LTR\n");
  1041. return 0;
  1042. }
  1043. switch (action) {
  1044. case BUS_NOTIFY_BIND_DRIVER:
  1045. dev_pm_domain_set(&pdev->dev, &acpi_lpss_pm_domain);
  1046. break;
  1047. case BUS_NOTIFY_DRIVER_NOT_BOUND:
  1048. case BUS_NOTIFY_UNBOUND_DRIVER:
  1049. dev_pm_domain_set(&pdev->dev, NULL);
  1050. break;
  1051. case BUS_NOTIFY_ADD_DEVICE:
  1052. dev_pm_domain_set(&pdev->dev, &acpi_lpss_pm_domain);
  1053. if (pdata->dev_desc->flags & LPSS_LTR)
  1054. return sysfs_create_group(&pdev->dev.kobj,
  1055. &lpss_attr_group);
  1056. break;
  1057. case BUS_NOTIFY_DEL_DEVICE:
  1058. if (pdata->dev_desc->flags & LPSS_LTR)
  1059. sysfs_remove_group(&pdev->dev.kobj, &lpss_attr_group);
  1060. dev_pm_domain_set(&pdev->dev, NULL);
  1061. break;
  1062. default:
  1063. break;
  1064. }
  1065. return 0;
  1066. }
  1067. static struct notifier_block acpi_lpss_nb = {
  1068. .notifier_call = acpi_lpss_platform_notify,
  1069. };
  1070. static void acpi_lpss_bind(struct device *dev)
  1071. {
  1072. struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
  1073. if (!pdata || !pdata->mmio_base || !(pdata->dev_desc->flags & LPSS_LTR))
  1074. return;
  1075. if (pdata->mmio_size >= pdata->dev_desc->prv_offset + LPSS_LTR_SIZE)
  1076. dev->power.set_latency_tolerance = acpi_lpss_set_ltr;
  1077. else
  1078. dev_err(dev, "MMIO size insufficient to access LTR\n");
  1079. }
  1080. static void acpi_lpss_unbind(struct device *dev)
  1081. {
  1082. dev->power.set_latency_tolerance = NULL;
  1083. }
  1084. static struct acpi_scan_handler lpss_handler = {
  1085. .ids = acpi_lpss_device_ids,
  1086. .attach = acpi_lpss_create_device,
  1087. .bind = acpi_lpss_bind,
  1088. .unbind = acpi_lpss_unbind,
  1089. };
  1090. void __init acpi_lpss_init(void)
  1091. {
  1092. const struct x86_cpu_id *id;
  1093. int ret;
  1094. ret = lpt_clk_init();
  1095. if (ret)
  1096. return;
  1097. id = x86_match_cpu(lpss_cpu_ids);
  1098. if (id)
  1099. lpss_quirks |= LPSS_QUIRK_ALWAYS_POWER_ON;
  1100. bus_register_notifier(&platform_bus_type, &acpi_lpss_nb);
  1101. acpi_scan_add_handler(&lpss_handler);
  1102. }
  1103. #else
  1104. static struct acpi_scan_handler lpss_handler = {
  1105. .ids = acpi_lpss_device_ids,
  1106. };
  1107. void __init acpi_lpss_init(void)
  1108. {
  1109. acpi_scan_add_handler(&lpss_handler);
  1110. }
  1111. #endif /* CONFIG_X86_INTEL_LPSS */