aegis128-neon-inner.c 6.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Copyright (C) 2019 Linaro, Ltd. <ard.biesheuvel@linaro.org>
  4. */
  5. #ifdef CONFIG_ARM64
  6. #include <asm/neon-intrinsics.h>
  7. #define AES_ROUND "aese %0.16b, %1.16b \n\t aesmc %0.16b, %0.16b"
  8. #else
  9. #include <arm_neon.h>
  10. #define AES_ROUND "aese.8 %q0, %q1 \n\t aesmc.8 %q0, %q0"
  11. #endif
  12. #define AEGIS_BLOCK_SIZE 16
  13. #include <stddef.h>
  14. extern int aegis128_have_aes_insn;
  15. void *memcpy(void *dest, const void *src, size_t n);
  16. void *memset(void *s, int c, size_t n);
  17. struct aegis128_state {
  18. uint8x16_t v[5];
  19. };
  20. extern const uint8_t crypto_aes_sbox[];
  21. static struct aegis128_state aegis128_load_state_neon(const void *state)
  22. {
  23. return (struct aegis128_state){ {
  24. vld1q_u8(state),
  25. vld1q_u8(state + 16),
  26. vld1q_u8(state + 32),
  27. vld1q_u8(state + 48),
  28. vld1q_u8(state + 64)
  29. } };
  30. }
  31. static void aegis128_save_state_neon(struct aegis128_state st, void *state)
  32. {
  33. vst1q_u8(state, st.v[0]);
  34. vst1q_u8(state + 16, st.v[1]);
  35. vst1q_u8(state + 32, st.v[2]);
  36. vst1q_u8(state + 48, st.v[3]);
  37. vst1q_u8(state + 64, st.v[4]);
  38. }
  39. static inline __attribute__((always_inline))
  40. uint8x16_t aegis_aes_round(uint8x16_t w)
  41. {
  42. uint8x16_t z = {};
  43. #ifdef CONFIG_ARM64
  44. if (!__builtin_expect(aegis128_have_aes_insn, 1)) {
  45. static const uint8_t shift_rows[] = {
  46. 0x0, 0x5, 0xa, 0xf, 0x4, 0x9, 0xe, 0x3,
  47. 0x8, 0xd, 0x2, 0x7, 0xc, 0x1, 0x6, 0xb,
  48. };
  49. static const uint8_t ror32by8[] = {
  50. 0x1, 0x2, 0x3, 0x0, 0x5, 0x6, 0x7, 0x4,
  51. 0x9, 0xa, 0xb, 0x8, 0xd, 0xe, 0xf, 0xc,
  52. };
  53. uint8x16_t v;
  54. // shift rows
  55. w = vqtbl1q_u8(w, vld1q_u8(shift_rows));
  56. // sub bytes
  57. #ifndef CONFIG_CC_IS_GCC
  58. v = vqtbl4q_u8(vld1q_u8_x4(crypto_aes_sbox), w);
  59. v = vqtbx4q_u8(v, vld1q_u8_x4(crypto_aes_sbox + 0x40), w - 0x40);
  60. v = vqtbx4q_u8(v, vld1q_u8_x4(crypto_aes_sbox + 0x80), w - 0x80);
  61. v = vqtbx4q_u8(v, vld1q_u8_x4(crypto_aes_sbox + 0xc0), w - 0xc0);
  62. #else
  63. asm("tbl %0.16b, {v16.16b-v19.16b}, %1.16b" : "=w"(v) : "w"(w));
  64. w -= 0x40;
  65. asm("tbx %0.16b, {v20.16b-v23.16b}, %1.16b" : "+w"(v) : "w"(w));
  66. w -= 0x40;
  67. asm("tbx %0.16b, {v24.16b-v27.16b}, %1.16b" : "+w"(v) : "w"(w));
  68. w -= 0x40;
  69. asm("tbx %0.16b, {v28.16b-v31.16b}, %1.16b" : "+w"(v) : "w"(w));
  70. #endif
  71. // mix columns
  72. w = (v << 1) ^ (uint8x16_t)(((int8x16_t)v >> 7) & 0x1b);
  73. w ^= (uint8x16_t)vrev32q_u16((uint16x8_t)v);
  74. w ^= vqtbl1q_u8(v ^ w, vld1q_u8(ror32by8));
  75. return w;
  76. }
  77. #endif
  78. /*
  79. * We use inline asm here instead of the vaeseq_u8/vaesmcq_u8 intrinsics
  80. * to force the compiler to issue the aese/aesmc instructions in pairs.
  81. * This is much faster on many cores, where the instruction pair can
  82. * execute in a single cycle.
  83. */
  84. asm(AES_ROUND : "+w"(w) : "w"(z));
  85. return w;
  86. }
  87. static inline __attribute__((always_inline))
  88. struct aegis128_state aegis128_update_neon(struct aegis128_state st,
  89. uint8x16_t m)
  90. {
  91. m ^= aegis_aes_round(st.v[4]);
  92. st.v[4] ^= aegis_aes_round(st.v[3]);
  93. st.v[3] ^= aegis_aes_round(st.v[2]);
  94. st.v[2] ^= aegis_aes_round(st.v[1]);
  95. st.v[1] ^= aegis_aes_round(st.v[0]);
  96. st.v[0] ^= m;
  97. return st;
  98. }
  99. static inline __attribute__((always_inline))
  100. void preload_sbox(void)
  101. {
  102. if (!IS_ENABLED(CONFIG_ARM64) ||
  103. !IS_ENABLED(CONFIG_CC_IS_GCC) ||
  104. __builtin_expect(aegis128_have_aes_insn, 1))
  105. return;
  106. asm("ld1 {v16.16b-v19.16b}, [%0], #64 \n\t"
  107. "ld1 {v20.16b-v23.16b}, [%0], #64 \n\t"
  108. "ld1 {v24.16b-v27.16b}, [%0], #64 \n\t"
  109. "ld1 {v28.16b-v31.16b}, [%0] \n\t"
  110. :: "r"(crypto_aes_sbox));
  111. }
  112. void crypto_aegis128_init_neon(void *state, const void *key, const void *iv)
  113. {
  114. static const uint8_t const0[] = {
  115. 0x00, 0x01, 0x01, 0x02, 0x03, 0x05, 0x08, 0x0d,
  116. 0x15, 0x22, 0x37, 0x59, 0x90, 0xe9, 0x79, 0x62,
  117. };
  118. static const uint8_t const1[] = {
  119. 0xdb, 0x3d, 0x18, 0x55, 0x6d, 0xc2, 0x2f, 0xf1,
  120. 0x20, 0x11, 0x31, 0x42, 0x73, 0xb5, 0x28, 0xdd,
  121. };
  122. uint8x16_t k = vld1q_u8(key);
  123. uint8x16_t kiv = k ^ vld1q_u8(iv);
  124. struct aegis128_state st = {{
  125. kiv,
  126. vld1q_u8(const1),
  127. vld1q_u8(const0),
  128. k ^ vld1q_u8(const0),
  129. k ^ vld1q_u8(const1),
  130. }};
  131. int i;
  132. preload_sbox();
  133. for (i = 0; i < 5; i++) {
  134. st = aegis128_update_neon(st, k);
  135. st = aegis128_update_neon(st, kiv);
  136. }
  137. aegis128_save_state_neon(st, state);
  138. }
  139. void crypto_aegis128_update_neon(void *state, const void *msg)
  140. {
  141. struct aegis128_state st = aegis128_load_state_neon(state);
  142. preload_sbox();
  143. st = aegis128_update_neon(st, vld1q_u8(msg));
  144. aegis128_save_state_neon(st, state);
  145. }
  146. void crypto_aegis128_encrypt_chunk_neon(void *state, void *dst, const void *src,
  147. unsigned int size)
  148. {
  149. struct aegis128_state st = aegis128_load_state_neon(state);
  150. uint8x16_t msg;
  151. preload_sbox();
  152. while (size >= AEGIS_BLOCK_SIZE) {
  153. uint8x16_t s = st.v[1] ^ (st.v[2] & st.v[3]) ^ st.v[4];
  154. msg = vld1q_u8(src);
  155. st = aegis128_update_neon(st, msg);
  156. vst1q_u8(dst, msg ^ s);
  157. size -= AEGIS_BLOCK_SIZE;
  158. src += AEGIS_BLOCK_SIZE;
  159. dst += AEGIS_BLOCK_SIZE;
  160. }
  161. if (size > 0) {
  162. uint8x16_t s = st.v[1] ^ (st.v[2] & st.v[3]) ^ st.v[4];
  163. uint8_t buf[AEGIS_BLOCK_SIZE] = {};
  164. memcpy(buf, src, size);
  165. msg = vld1q_u8(buf);
  166. st = aegis128_update_neon(st, msg);
  167. vst1q_u8(buf, msg ^ s);
  168. memcpy(dst, buf, size);
  169. }
  170. aegis128_save_state_neon(st, state);
  171. }
  172. void crypto_aegis128_decrypt_chunk_neon(void *state, void *dst, const void *src,
  173. unsigned int size)
  174. {
  175. struct aegis128_state st = aegis128_load_state_neon(state);
  176. uint8x16_t msg;
  177. preload_sbox();
  178. while (size >= AEGIS_BLOCK_SIZE) {
  179. msg = vld1q_u8(src) ^ st.v[1] ^ (st.v[2] & st.v[3]) ^ st.v[4];
  180. st = aegis128_update_neon(st, msg);
  181. vst1q_u8(dst, msg);
  182. size -= AEGIS_BLOCK_SIZE;
  183. src += AEGIS_BLOCK_SIZE;
  184. dst += AEGIS_BLOCK_SIZE;
  185. }
  186. if (size > 0) {
  187. uint8x16_t s = st.v[1] ^ (st.v[2] & st.v[3]) ^ st.v[4];
  188. uint8_t buf[AEGIS_BLOCK_SIZE];
  189. vst1q_u8(buf, s);
  190. memcpy(buf, src, size);
  191. msg = vld1q_u8(buf) ^ s;
  192. vst1q_u8(buf, msg);
  193. memcpy(dst, buf, size);
  194. st = aegis128_update_neon(st, msg);
  195. }
  196. aegis128_save_state_neon(st, state);
  197. }
  198. void crypto_aegis128_final_neon(void *state, void *tag_xor, uint64_t assoclen,
  199. uint64_t cryptlen)
  200. {
  201. struct aegis128_state st = aegis128_load_state_neon(state);
  202. uint8x16_t v;
  203. int i;
  204. preload_sbox();
  205. v = st.v[3] ^ (uint8x16_t)vcombine_u64(vmov_n_u64(8 * assoclen),
  206. vmov_n_u64(8 * cryptlen));
  207. for (i = 0; i < 7; i++)
  208. st = aegis128_update_neon(st, v);
  209. v = vld1q_u8(tag_xor);
  210. v ^= st.v[0] ^ st.v[1] ^ st.v[2] ^ st.v[3] ^ st.v[4];
  211. vst1q_u8(tag_xor, v);
  212. }