tlb.c 6.7 KB

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  1. /*
  2. * arch/xtensa/mm/tlb.c
  3. *
  4. * Logic that manipulates the Xtensa MMU. Derived from MIPS.
  5. *
  6. * This file is subject to the terms and conditions of the GNU General Public
  7. * License. See the file "COPYING" in the main directory of this archive
  8. * for more details.
  9. *
  10. * Copyright (C) 2001 - 2003 Tensilica Inc.
  11. *
  12. * Joe Taylor
  13. * Chris Zankel <chris@zankel.net>
  14. * Marc Gauthier
  15. */
  16. #include <linux/mm.h>
  17. #include <asm/processor.h>
  18. #include <asm/mmu_context.h>
  19. #include <asm/tlbflush.h>
  20. #include <asm/cacheflush.h>
  21. static inline void __flush_itlb_all (void)
  22. {
  23. int w, i;
  24. for (w = 0; w < ITLB_ARF_WAYS; w++) {
  25. for (i = 0; i < (1 << XCHAL_ITLB_ARF_ENTRIES_LOG2); i++) {
  26. int e = w + (i << PAGE_SHIFT);
  27. invalidate_itlb_entry_no_isync(e);
  28. }
  29. }
  30. asm volatile ("isync\n");
  31. }
  32. static inline void __flush_dtlb_all (void)
  33. {
  34. int w, i;
  35. for (w = 0; w < DTLB_ARF_WAYS; w++) {
  36. for (i = 0; i < (1 << XCHAL_DTLB_ARF_ENTRIES_LOG2); i++) {
  37. int e = w + (i << PAGE_SHIFT);
  38. invalidate_dtlb_entry_no_isync(e);
  39. }
  40. }
  41. asm volatile ("isync\n");
  42. }
  43. void local_flush_tlb_all(void)
  44. {
  45. __flush_itlb_all();
  46. __flush_dtlb_all();
  47. }
  48. /* If mm is current, we simply assign the current task a new ASID, thus,
  49. * invalidating all previous tlb entries. If mm is someone else's user mapping,
  50. * wie invalidate the context, thus, when that user mapping is swapped in,
  51. * a new context will be assigned to it.
  52. */
  53. void local_flush_tlb_mm(struct mm_struct *mm)
  54. {
  55. int cpu = smp_processor_id();
  56. if (mm == current->active_mm) {
  57. unsigned long flags;
  58. local_irq_save(flags);
  59. mm->context.asid[cpu] = NO_CONTEXT;
  60. activate_context(mm, cpu);
  61. local_irq_restore(flags);
  62. } else {
  63. mm->context.asid[cpu] = NO_CONTEXT;
  64. mm->context.cpu = -1;
  65. }
  66. }
  67. #define _ITLB_ENTRIES (ITLB_ARF_WAYS << XCHAL_ITLB_ARF_ENTRIES_LOG2)
  68. #define _DTLB_ENTRIES (DTLB_ARF_WAYS << XCHAL_DTLB_ARF_ENTRIES_LOG2)
  69. #if _ITLB_ENTRIES > _DTLB_ENTRIES
  70. # define _TLB_ENTRIES _ITLB_ENTRIES
  71. #else
  72. # define _TLB_ENTRIES _DTLB_ENTRIES
  73. #endif
  74. void local_flush_tlb_range(struct vm_area_struct *vma,
  75. unsigned long start, unsigned long end)
  76. {
  77. int cpu = smp_processor_id();
  78. struct mm_struct *mm = vma->vm_mm;
  79. unsigned long flags;
  80. if (mm->context.asid[cpu] == NO_CONTEXT)
  81. return;
  82. pr_debug("[tlbrange<%02lx,%08lx,%08lx>]\n",
  83. (unsigned long)mm->context.asid[cpu], start, end);
  84. local_irq_save(flags);
  85. if (end-start + (PAGE_SIZE-1) <= _TLB_ENTRIES << PAGE_SHIFT) {
  86. int oldpid = get_rasid_register();
  87. set_rasid_register(ASID_INSERT(mm->context.asid[cpu]));
  88. start &= PAGE_MASK;
  89. if (vma->vm_flags & VM_EXEC)
  90. while(start < end) {
  91. invalidate_itlb_mapping(start);
  92. invalidate_dtlb_mapping(start);
  93. start += PAGE_SIZE;
  94. }
  95. else
  96. while(start < end) {
  97. invalidate_dtlb_mapping(start);
  98. start += PAGE_SIZE;
  99. }
  100. set_rasid_register(oldpid);
  101. } else {
  102. local_flush_tlb_mm(mm);
  103. }
  104. local_irq_restore(flags);
  105. }
  106. void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
  107. {
  108. int cpu = smp_processor_id();
  109. struct mm_struct* mm = vma->vm_mm;
  110. unsigned long flags;
  111. int oldpid;
  112. if (mm->context.asid[cpu] == NO_CONTEXT)
  113. return;
  114. local_irq_save(flags);
  115. oldpid = get_rasid_register();
  116. set_rasid_register(ASID_INSERT(mm->context.asid[cpu]));
  117. if (vma->vm_flags & VM_EXEC)
  118. invalidate_itlb_mapping(page);
  119. invalidate_dtlb_mapping(page);
  120. set_rasid_register(oldpid);
  121. local_irq_restore(flags);
  122. }
  123. void local_flush_tlb_kernel_range(unsigned long start, unsigned long end)
  124. {
  125. if (end > start && start >= TASK_SIZE && end <= PAGE_OFFSET &&
  126. end - start < _TLB_ENTRIES << PAGE_SHIFT) {
  127. start &= PAGE_MASK;
  128. while (start < end) {
  129. invalidate_itlb_mapping(start);
  130. invalidate_dtlb_mapping(start);
  131. start += PAGE_SIZE;
  132. }
  133. } else {
  134. local_flush_tlb_all();
  135. }
  136. }
  137. #ifdef CONFIG_DEBUG_TLB_SANITY
  138. static unsigned get_pte_for_vaddr(unsigned vaddr)
  139. {
  140. struct task_struct *task = get_current();
  141. struct mm_struct *mm = task->mm;
  142. pgd_t *pgd;
  143. p4d_t *p4d;
  144. pud_t *pud;
  145. pmd_t *pmd;
  146. pte_t *pte;
  147. if (!mm)
  148. mm = task->active_mm;
  149. pgd = pgd_offset(mm, vaddr);
  150. if (pgd_none_or_clear_bad(pgd))
  151. return 0;
  152. p4d = p4d_offset(pgd, vaddr);
  153. if (p4d_none_or_clear_bad(p4d))
  154. return 0;
  155. pud = pud_offset(p4d, vaddr);
  156. if (pud_none_or_clear_bad(pud))
  157. return 0;
  158. pmd = pmd_offset(pud, vaddr);
  159. if (pmd_none_or_clear_bad(pmd))
  160. return 0;
  161. pte = pte_offset_map(pmd, vaddr);
  162. if (!pte)
  163. return 0;
  164. return pte_val(*pte);
  165. }
  166. enum {
  167. TLB_SUSPICIOUS = 1,
  168. TLB_INSANE = 2,
  169. };
  170. static void tlb_insane(void)
  171. {
  172. BUG_ON(1);
  173. }
  174. static void tlb_suspicious(void)
  175. {
  176. WARN_ON(1);
  177. }
  178. /*
  179. * Check that TLB entries with kernel ASID (1) have kernel VMA (>= TASK_SIZE),
  180. * and TLB entries with user ASID (>=4) have VMA < TASK_SIZE.
  181. *
  182. * Check that valid TLB entries either have the same PA as the PTE, or PTE is
  183. * marked as non-present. Non-present PTE and the page with non-zero refcount
  184. * and zero mapcount is normal for batched TLB flush operation. Zero refcount
  185. * means that the page was freed prematurely. Non-zero mapcount is unusual,
  186. * but does not necessary means an error, thus marked as suspicious.
  187. */
  188. static int check_tlb_entry(unsigned w, unsigned e, bool dtlb)
  189. {
  190. unsigned tlbidx = w | (e << PAGE_SHIFT);
  191. unsigned r0 = dtlb ?
  192. read_dtlb_virtual(tlbidx) : read_itlb_virtual(tlbidx);
  193. unsigned r1 = dtlb ?
  194. read_dtlb_translation(tlbidx) : read_itlb_translation(tlbidx);
  195. unsigned vpn = (r0 & PAGE_MASK) | (e << PAGE_SHIFT);
  196. unsigned pte = get_pte_for_vaddr(vpn);
  197. unsigned mm_asid = (get_rasid_register() >> 8) & ASID_MASK;
  198. unsigned tlb_asid = r0 & ASID_MASK;
  199. bool kernel = tlb_asid == 1;
  200. int rc = 0;
  201. if (tlb_asid > 0 && ((vpn < TASK_SIZE) == kernel)) {
  202. pr_err("%cTLB: way: %u, entry: %u, VPN %08x in %s PTE\n",
  203. dtlb ? 'D' : 'I', w, e, vpn,
  204. kernel ? "kernel" : "user");
  205. rc |= TLB_INSANE;
  206. }
  207. if (tlb_asid == mm_asid) {
  208. if ((pte ^ r1) & PAGE_MASK) {
  209. pr_err("%cTLB: way: %u, entry: %u, mapping: %08x->%08x, PTE: %08x\n",
  210. dtlb ? 'D' : 'I', w, e, r0, r1, pte);
  211. if (pte == 0 || !pte_present(__pte(pte))) {
  212. struct page *p = pfn_to_page(r1 >> PAGE_SHIFT);
  213. pr_err("page refcount: %d, mapcount: %d\n",
  214. page_count(p),
  215. page_mapcount(p));
  216. if (!page_count(p))
  217. rc |= TLB_INSANE;
  218. else if (page_mapcount(p))
  219. rc |= TLB_SUSPICIOUS;
  220. } else {
  221. rc |= TLB_INSANE;
  222. }
  223. }
  224. }
  225. return rc;
  226. }
  227. void check_tlb_sanity(void)
  228. {
  229. unsigned long flags;
  230. unsigned w, e;
  231. int bug = 0;
  232. local_irq_save(flags);
  233. for (w = 0; w < DTLB_ARF_WAYS; ++w)
  234. for (e = 0; e < (1 << XCHAL_DTLB_ARF_ENTRIES_LOG2); ++e)
  235. bug |= check_tlb_entry(w, e, true);
  236. for (w = 0; w < ITLB_ARF_WAYS; ++w)
  237. for (e = 0; e < (1 << XCHAL_ITLB_ARF_ENTRIES_LOG2); ++e)
  238. bug |= check_tlb_entry(w, e, false);
  239. if (bug & TLB_INSANE)
  240. tlb_insane();
  241. if (bug & TLB_SUSPICIOUS)
  242. tlb_suspicious();
  243. local_irq_restore(flags);
  244. }
  245. #endif /* CONFIG_DEBUG_TLB_SANITY */