mmu.c 2.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * xtensa mmu stuff
  4. *
  5. * Extracted from init.c
  6. */
  7. #include <linux/memblock.h>
  8. #include <linux/percpu.h>
  9. #include <linux/init.h>
  10. #include <linux/string.h>
  11. #include <linux/slab.h>
  12. #include <linux/cache.h>
  13. #include <asm/tlb.h>
  14. #include <asm/tlbflush.h>
  15. #include <asm/mmu_context.h>
  16. #include <asm/page.h>
  17. #include <asm/initialize_mmu.h>
  18. #include <asm/io.h>
  19. #if defined(CONFIG_HIGHMEM)
  20. static void * __init init_pmd(unsigned long vaddr, unsigned long n_pages)
  21. {
  22. pmd_t *pmd = pmd_off_k(vaddr);
  23. pte_t *pte;
  24. unsigned long i;
  25. n_pages = ALIGN(n_pages, PTRS_PER_PTE);
  26. pr_debug("%s: vaddr: 0x%08lx, n_pages: %ld\n",
  27. __func__, vaddr, n_pages);
  28. pte = memblock_alloc_low(n_pages * sizeof(pte_t), PAGE_SIZE);
  29. if (!pte)
  30. panic("%s: Failed to allocate %lu bytes align=%lx\n",
  31. __func__, n_pages * sizeof(pte_t), PAGE_SIZE);
  32. for (i = 0; i < n_pages; ++i)
  33. pte_clear(NULL, 0, pte + i);
  34. for (i = 0; i < n_pages; i += PTRS_PER_PTE, ++pmd) {
  35. pte_t *cur_pte = pte + i;
  36. BUG_ON(!pmd_none(*pmd));
  37. set_pmd(pmd, __pmd(((unsigned long)cur_pte) & PAGE_MASK));
  38. BUG_ON(cur_pte != pte_offset_kernel(pmd, 0));
  39. pr_debug("%s: pmd: 0x%p, pte: 0x%p\n",
  40. __func__, pmd, cur_pte);
  41. }
  42. return pte;
  43. }
  44. static void __init fixedrange_init(void)
  45. {
  46. init_pmd(__fix_to_virt(0), __end_of_fixed_addresses);
  47. }
  48. #endif
  49. void __init paging_init(void)
  50. {
  51. #ifdef CONFIG_HIGHMEM
  52. fixedrange_init();
  53. pkmap_page_table = init_pmd(PKMAP_BASE, LAST_PKMAP);
  54. kmap_init();
  55. #endif
  56. }
  57. /*
  58. * Flush the mmu and reset associated register to default values.
  59. */
  60. void init_mmu(void)
  61. {
  62. #if !(XCHAL_HAVE_PTP_MMU && XCHAL_HAVE_SPANNING_WAY)
  63. /*
  64. * Writing zeros to the instruction and data TLBCFG special
  65. * registers ensure that valid values exist in the register.
  66. *
  67. * For existing PGSZID<w> fields, zero selects the first element
  68. * of the page-size array. For nonexistent PGSZID<w> fields,
  69. * zero is the best value to write. Also, when changing PGSZID<w>
  70. * fields, the corresponding TLB must be flushed.
  71. */
  72. set_itlbcfg_register(0);
  73. set_dtlbcfg_register(0);
  74. #endif
  75. init_kio();
  76. local_flush_tlb_all();
  77. /* Set rasid register to a known value. */
  78. set_rasid_register(ASID_INSERT(ASID_USER_FIRST));
  79. /* Set PTEVADDR special register to the start of the page
  80. * table, which is in kernel mappable space (ie. not
  81. * statically mapped). This register's value is undefined on
  82. * reset.
  83. */
  84. set_ptevaddr_register(XCHAL_PAGE_TABLE_VADDR);
  85. }
  86. void init_kio(void)
  87. {
  88. #if XCHAL_HAVE_PTP_MMU && XCHAL_HAVE_SPANNING_WAY && defined(CONFIG_USE_OF)
  89. /*
  90. * Update the IO area mapping in case xtensa_kio_paddr has changed
  91. */
  92. write_dtlb_entry(__pte(xtensa_kio_paddr + CA_WRITEBACK),
  93. XCHAL_KIO_CACHED_VADDR + 6);
  94. write_itlb_entry(__pte(xtensa_kio_paddr + CA_WRITEBACK),
  95. XCHAL_KIO_CACHED_VADDR + 6);
  96. write_dtlb_entry(__pte(xtensa_kio_paddr + CA_BYPASS),
  97. XCHAL_KIO_BYPASS_VADDR + 6);
  98. write_itlb_entry(__pte(xtensa_kio_paddr + CA_BYPASS),
  99. XCHAL_KIO_BYPASS_VADDR + 6);
  100. #endif
  101. }