misc.S 7.7 KB

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  1. /*
  2. * arch/xtensa/mm/misc.S
  3. *
  4. * Miscellaneous assembly functions.
  5. *
  6. * This file is subject to the terms and conditions of the GNU General Public
  7. * License. See the file "COPYING" in the main directory of this archive
  8. * for more details.
  9. *
  10. * Copyright (C) 2001 - 2007 Tensilica Inc.
  11. *
  12. * Chris Zankel <chris@zankel.net>
  13. */
  14. #include <linux/linkage.h>
  15. #include <linux/pgtable.h>
  16. #include <asm/page.h>
  17. #include <asm/asmmacro.h>
  18. #include <asm/cacheasm.h>
  19. #include <asm/tlbflush.h>
  20. /*
  21. * clear_page and clear_user_page are the same for non-cache-aliased configs.
  22. *
  23. * clear_page (unsigned long page)
  24. * a2
  25. */
  26. ENTRY(clear_page)
  27. abi_entry_default
  28. movi a3, 0
  29. __loopi a2, a7, PAGE_SIZE, 32
  30. s32i a3, a2, 0
  31. s32i a3, a2, 4
  32. s32i a3, a2, 8
  33. s32i a3, a2, 12
  34. s32i a3, a2, 16
  35. s32i a3, a2, 20
  36. s32i a3, a2, 24
  37. s32i a3, a2, 28
  38. __endla a2, a7, 32
  39. abi_ret_default
  40. ENDPROC(clear_page)
  41. /*
  42. * copy_page and copy_user_page are the same for non-cache-aliased configs.
  43. *
  44. * copy_page (void *to, void *from)
  45. * a2 a3
  46. */
  47. ENTRY(copy_page)
  48. abi_entry_default
  49. __loopi a2, a4, PAGE_SIZE, 32
  50. l32i a8, a3, 0
  51. l32i a9, a3, 4
  52. s32i a8, a2, 0
  53. s32i a9, a2, 4
  54. l32i a8, a3, 8
  55. l32i a9, a3, 12
  56. s32i a8, a2, 8
  57. s32i a9, a2, 12
  58. l32i a8, a3, 16
  59. l32i a9, a3, 20
  60. s32i a8, a2, 16
  61. s32i a9, a2, 20
  62. l32i a8, a3, 24
  63. l32i a9, a3, 28
  64. s32i a8, a2, 24
  65. s32i a9, a2, 28
  66. addi a2, a2, 32
  67. addi a3, a3, 32
  68. __endl a2, a4
  69. abi_ret_default
  70. ENDPROC(copy_page)
  71. #ifdef CONFIG_MMU
  72. /*
  73. * If we have to deal with cache aliasing, we use temporary memory mappings
  74. * to ensure that the source and destination pages have the same color as
  75. * the virtual address. We use way 0 and 1 for temporary mappings in such cases.
  76. *
  77. * The temporary DTLB entries shouldn't be flushed by interrupts, but are
  78. * flushed by preemptive task switches. Special code in the
  79. * fast_second_level_miss handler re-established the temporary mapping.
  80. * It requires that the PPNs for the destination and source addresses are
  81. * in a6, and a7, respectively.
  82. */
  83. /* TLB miss exceptions are treated special in the following region */
  84. ENTRY(__tlbtemp_mapping_start)
  85. #if (DCACHE_WAY_SIZE > PAGE_SIZE)
  86. /*
  87. * clear_page_alias(void *addr, unsigned long paddr)
  88. * a2 a3
  89. */
  90. ENTRY(clear_page_alias)
  91. abi_entry_default
  92. /* Skip setting up a temporary DTLB if not aliased low page. */
  93. movi a5, PAGE_OFFSET
  94. movi a6, 0
  95. beqz a3, 1f
  96. /* Setup a temporary DTLB for the addr. */
  97. addi a6, a3, (PAGE_KERNEL | _PAGE_HW_WRITE)
  98. mov a4, a2
  99. wdtlb a6, a2
  100. dsync
  101. 1: movi a3, 0
  102. __loopi a2, a7, PAGE_SIZE, 32
  103. s32i a3, a2, 0
  104. s32i a3, a2, 4
  105. s32i a3, a2, 8
  106. s32i a3, a2, 12
  107. s32i a3, a2, 16
  108. s32i a3, a2, 20
  109. s32i a3, a2, 24
  110. s32i a3, a2, 28
  111. __endla a2, a7, 32
  112. bnez a6, 1f
  113. abi_ret_default
  114. /* We need to invalidate the temporary idtlb entry, if any. */
  115. 1: idtlb a4
  116. dsync
  117. abi_ret_default
  118. ENDPROC(clear_page_alias)
  119. /*
  120. * copy_page_alias(void *to, void *from,
  121. * a2 a3
  122. * unsigned long to_paddr, unsigned long from_paddr)
  123. * a4 a5
  124. */
  125. ENTRY(copy_page_alias)
  126. abi_entry_default
  127. /* Skip setting up a temporary DTLB for destination if not aliased. */
  128. movi a6, 0
  129. movi a7, 0
  130. beqz a4, 1f
  131. /* Setup a temporary DTLB for destination. */
  132. addi a6, a4, (PAGE_KERNEL | _PAGE_HW_WRITE)
  133. wdtlb a6, a2
  134. dsync
  135. /* Skip setting up a temporary DTLB for source if not aliased. */
  136. 1: beqz a5, 1f
  137. /* Setup a temporary DTLB for source. */
  138. addi a7, a5, PAGE_KERNEL
  139. addi a8, a3, 1 # way1
  140. wdtlb a7, a8
  141. dsync
  142. 1: __loopi a2, a4, PAGE_SIZE, 32
  143. l32i a8, a3, 0
  144. l32i a9, a3, 4
  145. s32i a8, a2, 0
  146. s32i a9, a2, 4
  147. l32i a8, a3, 8
  148. l32i a9, a3, 12
  149. s32i a8, a2, 8
  150. s32i a9, a2, 12
  151. l32i a8, a3, 16
  152. l32i a9, a3, 20
  153. s32i a8, a2, 16
  154. s32i a9, a2, 20
  155. l32i a8, a3, 24
  156. l32i a9, a3, 28
  157. s32i a8, a2, 24
  158. s32i a9, a2, 28
  159. addi a2, a2, 32
  160. addi a3, a3, 32
  161. __endl a2, a4
  162. /* We need to invalidate any temporary mapping! */
  163. bnez a6, 1f
  164. bnez a7, 2f
  165. abi_ret_default
  166. 1: addi a2, a2, -PAGE_SIZE
  167. idtlb a2
  168. dsync
  169. bnez a7, 2f
  170. abi_ret_default
  171. 2: addi a3, a3, -PAGE_SIZE+1
  172. idtlb a3
  173. dsync
  174. abi_ret_default
  175. ENDPROC(copy_page_alias)
  176. #endif
  177. #if (DCACHE_WAY_SIZE > PAGE_SIZE)
  178. /*
  179. * void __flush_invalidate_dcache_page_alias (addr, phys)
  180. * a2 a3
  181. */
  182. ENTRY(__flush_invalidate_dcache_page_alias)
  183. abi_entry_default
  184. movi a7, 0 # required for exception handler
  185. addi a6, a3, (PAGE_KERNEL | _PAGE_HW_WRITE)
  186. mov a4, a2
  187. wdtlb a6, a2
  188. dsync
  189. ___flush_invalidate_dcache_page a2 a3
  190. idtlb a4
  191. dsync
  192. abi_ret_default
  193. ENDPROC(__flush_invalidate_dcache_page_alias)
  194. /*
  195. * void __invalidate_dcache_page_alias (addr, phys)
  196. * a2 a3
  197. */
  198. ENTRY(__invalidate_dcache_page_alias)
  199. abi_entry_default
  200. movi a7, 0 # required for exception handler
  201. addi a6, a3, (PAGE_KERNEL | _PAGE_HW_WRITE)
  202. mov a4, a2
  203. wdtlb a6, a2
  204. dsync
  205. ___invalidate_dcache_page a2 a3
  206. idtlb a4
  207. dsync
  208. abi_ret_default
  209. ENDPROC(__invalidate_dcache_page_alias)
  210. #endif
  211. ENTRY(__tlbtemp_mapping_itlb)
  212. #if (ICACHE_WAY_SIZE > PAGE_SIZE)
  213. ENTRY(__invalidate_icache_page_alias)
  214. abi_entry_default
  215. addi a6, a3, (PAGE_KERNEL_EXEC | _PAGE_HW_WRITE)
  216. mov a4, a2
  217. witlb a6, a2
  218. isync
  219. ___invalidate_icache_page a2 a3
  220. iitlb a4
  221. isync
  222. abi_ret_default
  223. ENDPROC(__invalidate_icache_page_alias)
  224. #endif
  225. /* End of special treatment in tlb miss exception */
  226. ENTRY(__tlbtemp_mapping_end)
  227. #endif /* CONFIG_MMU
  228. /*
  229. * void __invalidate_icache_page(ulong start)
  230. */
  231. ENTRY(__invalidate_icache_page)
  232. abi_entry_default
  233. ___invalidate_icache_page a2 a3
  234. isync
  235. abi_ret_default
  236. ENDPROC(__invalidate_icache_page)
  237. /*
  238. * void __invalidate_dcache_page(ulong start)
  239. */
  240. ENTRY(__invalidate_dcache_page)
  241. abi_entry_default
  242. ___invalidate_dcache_page a2 a3
  243. dsync
  244. abi_ret_default
  245. ENDPROC(__invalidate_dcache_page)
  246. /*
  247. * void __flush_invalidate_dcache_page(ulong start)
  248. */
  249. ENTRY(__flush_invalidate_dcache_page)
  250. abi_entry_default
  251. ___flush_invalidate_dcache_page a2 a3
  252. dsync
  253. abi_ret_default
  254. ENDPROC(__flush_invalidate_dcache_page)
  255. /*
  256. * void __flush_dcache_page(ulong start)
  257. */
  258. ENTRY(__flush_dcache_page)
  259. abi_entry_default
  260. ___flush_dcache_page a2 a3
  261. dsync
  262. abi_ret_default
  263. ENDPROC(__flush_dcache_page)
  264. /*
  265. * void __invalidate_icache_range(ulong start, ulong size)
  266. */
  267. ENTRY(__invalidate_icache_range)
  268. abi_entry_default
  269. ___invalidate_icache_range a2 a3 a4
  270. isync
  271. abi_ret_default
  272. ENDPROC(__invalidate_icache_range)
  273. /*
  274. * void __flush_invalidate_dcache_range(ulong start, ulong size)
  275. */
  276. ENTRY(__flush_invalidate_dcache_range)
  277. abi_entry_default
  278. ___flush_invalidate_dcache_range a2 a3 a4
  279. dsync
  280. abi_ret_default
  281. ENDPROC(__flush_invalidate_dcache_range)
  282. /*
  283. * void _flush_dcache_range(ulong start, ulong size)
  284. */
  285. ENTRY(__flush_dcache_range)
  286. abi_entry_default
  287. ___flush_dcache_range a2 a3 a4
  288. dsync
  289. abi_ret_default
  290. ENDPROC(__flush_dcache_range)
  291. /*
  292. * void _invalidate_dcache_range(ulong start, ulong size)
  293. */
  294. ENTRY(__invalidate_dcache_range)
  295. abi_entry_default
  296. ___invalidate_dcache_range a2 a3 a4
  297. abi_ret_default
  298. ENDPROC(__invalidate_dcache_range)
  299. /*
  300. * void _invalidate_icache_all(void)
  301. */
  302. ENTRY(__invalidate_icache_all)
  303. abi_entry_default
  304. ___invalidate_icache_all a2 a3
  305. isync
  306. abi_ret_default
  307. ENDPROC(__invalidate_icache_all)
  308. /*
  309. * void _flush_invalidate_dcache_all(void)
  310. */
  311. ENTRY(__flush_invalidate_dcache_all)
  312. abi_entry_default
  313. ___flush_invalidate_dcache_all a2 a3
  314. dsync
  315. abi_ret_default
  316. ENDPROC(__flush_invalidate_dcache_all)
  317. /*
  318. * void _invalidate_dcache_all(void)
  319. */
  320. ENTRY(__invalidate_dcache_all)
  321. abi_entry_default
  322. ___invalidate_dcache_all a2 a3
  323. dsync
  324. abi_ret_default
  325. ENDPROC(__invalidate_dcache_all)