pci-auto.c 8.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * arch/xtensa/lib/pci-auto.c
  4. *
  5. * PCI autoconfiguration library
  6. *
  7. * Copyright (C) 2001 - 2005 Tensilica Inc.
  8. *
  9. * Chris Zankel <zankel@tensilica.com, cez@zankel.net>
  10. *
  11. * Based on work from Matt Porter <mporter@mvista.com>
  12. */
  13. #include <linux/kernel.h>
  14. #include <linux/init.h>
  15. #include <linux/pci.h>
  16. #include <asm/pci-bridge.h>
  17. /*
  18. *
  19. * Setting up a PCI
  20. *
  21. * pci_ctrl->first_busno = <first bus number (0)>
  22. * pci_ctrl->last_busno = <last bus number (0xff)>
  23. * pci_ctrl->ops = <PCI config operations>
  24. * pci_ctrl->map_irq = <function to return the interrupt number for a device>
  25. *
  26. * pci_ctrl->io_space.start = <IO space start address (PCI view)>
  27. * pci_ctrl->io_space.end = <IO space end address (PCI view)>
  28. * pci_ctrl->io_space.base = <IO space offset: address 0 from CPU space>
  29. * pci_ctrl->mem_space.start = <MEM space start address (PCI view)>
  30. * pci_ctrl->mem_space.end = <MEM space end address (PCI view)>
  31. * pci_ctrl->mem_space.base = <MEM space offset: address 0 from CPU space>
  32. *
  33. * pcibios_init_resource(&pci_ctrl->io_resource, <IO space start>,
  34. * <IO space end>, IORESOURCE_IO, "PCI host bridge");
  35. * pcibios_init_resource(&pci_ctrl->mem_resources[0], <MEM space start>,
  36. * <MEM space end>, IORESOURCE_MEM, "PCI host bridge");
  37. *
  38. * pci_ctrl->last_busno = pciauto_bus_scan(pci_ctrl,pci_ctrl->first_busno);
  39. *
  40. * int __init pciauto_bus_scan(struct pci_controller *pci_ctrl, int current_bus)
  41. *
  42. */
  43. static int pciauto_upper_iospc;
  44. static int pciauto_upper_memspc;
  45. static struct pci_dev pciauto_dev;
  46. static struct pci_bus pciauto_bus;
  47. /*
  48. * Helper functions
  49. */
  50. /* Initialize the bars of a PCI device. */
  51. static void __init
  52. pciauto_setup_bars(struct pci_dev *dev, int bar_limit)
  53. {
  54. int bar_size;
  55. int bar, bar_nr;
  56. int *upper_limit;
  57. int found_mem64 = 0;
  58. for (bar = PCI_BASE_ADDRESS_0, bar_nr = 0;
  59. bar <= bar_limit;
  60. bar+=4, bar_nr++)
  61. {
  62. /* Tickle the BAR and get the size */
  63. pci_write_config_dword(dev, bar, 0xffffffff);
  64. pci_read_config_dword(dev, bar, &bar_size);
  65. /* If BAR is not implemented go to the next BAR */
  66. if (!bar_size)
  67. continue;
  68. /* Check the BAR type and set our address mask */
  69. if (bar_size & PCI_BASE_ADDRESS_SPACE_IO)
  70. {
  71. bar_size &= PCI_BASE_ADDRESS_IO_MASK;
  72. upper_limit = &pciauto_upper_iospc;
  73. pr_debug("PCI Autoconfig: BAR %d, I/O, ", bar_nr);
  74. }
  75. else
  76. {
  77. if ((bar_size & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
  78. PCI_BASE_ADDRESS_MEM_TYPE_64)
  79. found_mem64 = 1;
  80. bar_size &= PCI_BASE_ADDRESS_MEM_MASK;
  81. upper_limit = &pciauto_upper_memspc;
  82. pr_debug("PCI Autoconfig: BAR %d, Mem, ", bar_nr);
  83. }
  84. /* Allocate a base address (bar_size is negative!) */
  85. *upper_limit = (*upper_limit + bar_size) & bar_size;
  86. /* Write it out and update our limit */
  87. pci_write_config_dword(dev, bar, *upper_limit);
  88. /*
  89. * If we are a 64-bit decoder then increment to the
  90. * upper 32 bits of the bar and force it to locate
  91. * in the lower 4GB of memory.
  92. */
  93. if (found_mem64)
  94. pci_write_config_dword(dev, (bar+=4), 0x00000000);
  95. pr_debug("size=0x%x, address=0x%x\n",
  96. ~bar_size + 1, *upper_limit);
  97. }
  98. }
  99. /* Initialize the interrupt number. */
  100. static void __init
  101. pciauto_setup_irq(struct pci_controller* pci_ctrl,struct pci_dev *dev,int devfn)
  102. {
  103. u8 pin;
  104. int irq = 0;
  105. pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
  106. /* Fix illegal pin numbers. */
  107. if (pin == 0 || pin > 4)
  108. pin = 1;
  109. if (pci_ctrl->map_irq)
  110. irq = pci_ctrl->map_irq(dev, PCI_SLOT(devfn), pin);
  111. if (irq == -1)
  112. irq = 0;
  113. pr_debug("PCI Autoconfig: Interrupt %d, pin %d\n", irq, pin);
  114. pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
  115. }
  116. static void __init
  117. pciauto_prescan_setup_bridge(struct pci_dev *dev, int current_bus,
  118. int sub_bus, int *iosave, int *memsave)
  119. {
  120. /* Configure bus number registers */
  121. pci_write_config_byte(dev, PCI_PRIMARY_BUS, current_bus);
  122. pci_write_config_byte(dev, PCI_SECONDARY_BUS, sub_bus + 1);
  123. pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, 0xff);
  124. /* Round memory allocator to 1MB boundary */
  125. pciauto_upper_memspc &= ~(0x100000 - 1);
  126. *memsave = pciauto_upper_memspc;
  127. /* Round I/O allocator to 4KB boundary */
  128. pciauto_upper_iospc &= ~(0x1000 - 1);
  129. *iosave = pciauto_upper_iospc;
  130. /* Set up memory and I/O filter limits, assume 32-bit I/O space */
  131. pci_write_config_word(dev, PCI_MEMORY_LIMIT,
  132. ((pciauto_upper_memspc - 1) & 0xfff00000) >> 16);
  133. pci_write_config_byte(dev, PCI_IO_LIMIT,
  134. ((pciauto_upper_iospc - 1) & 0x0000f000) >> 8);
  135. pci_write_config_word(dev, PCI_IO_LIMIT_UPPER16,
  136. ((pciauto_upper_iospc - 1) & 0xffff0000) >> 16);
  137. }
  138. static void __init
  139. pciauto_postscan_setup_bridge(struct pci_dev *dev, int current_bus, int sub_bus,
  140. int *iosave, int *memsave)
  141. {
  142. int cmdstat;
  143. /* Configure bus number registers */
  144. pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, sub_bus);
  145. /*
  146. * Round memory allocator to 1MB boundary.
  147. * If no space used, allocate minimum.
  148. */
  149. pciauto_upper_memspc &= ~(0x100000 - 1);
  150. if (*memsave == pciauto_upper_memspc)
  151. pciauto_upper_memspc -= 0x00100000;
  152. pci_write_config_word(dev, PCI_MEMORY_BASE, pciauto_upper_memspc >> 16);
  153. /* Allocate 1MB for pre-fretch */
  154. pci_write_config_word(dev, PCI_PREF_MEMORY_LIMIT,
  155. ((pciauto_upper_memspc - 1) & 0xfff00000) >> 16);
  156. pciauto_upper_memspc -= 0x100000;
  157. pci_write_config_word(dev, PCI_PREF_MEMORY_BASE,
  158. pciauto_upper_memspc >> 16);
  159. /* Round I/O allocator to 4KB boundary */
  160. pciauto_upper_iospc &= ~(0x1000 - 1);
  161. if (*iosave == pciauto_upper_iospc)
  162. pciauto_upper_iospc -= 0x1000;
  163. pci_write_config_byte(dev, PCI_IO_BASE,
  164. (pciauto_upper_iospc & 0x0000f000) >> 8);
  165. pci_write_config_word(dev, PCI_IO_BASE_UPPER16,
  166. pciauto_upper_iospc >> 16);
  167. /* Enable memory and I/O accesses, enable bus master */
  168. pci_read_config_dword(dev, PCI_COMMAND, &cmdstat);
  169. pci_write_config_dword(dev, PCI_COMMAND,
  170. cmdstat |
  171. PCI_COMMAND_IO |
  172. PCI_COMMAND_MEMORY |
  173. PCI_COMMAND_MASTER);
  174. }
  175. /*
  176. * Scan the current PCI bus.
  177. */
  178. int __init pciauto_bus_scan(struct pci_controller *pci_ctrl, int current_bus)
  179. {
  180. int sub_bus, pci_devfn, pci_class, cmdstat, found_multi=0;
  181. unsigned short vid;
  182. unsigned char header_type;
  183. struct pci_dev *dev = &pciauto_dev;
  184. pciauto_dev.bus = &pciauto_bus;
  185. pciauto_dev.sysdata = pci_ctrl;
  186. pciauto_bus.ops = pci_ctrl->ops;
  187. /*
  188. * Fetch our I/O and memory space upper boundaries used
  189. * to allocated base addresses on this pci_controller.
  190. */
  191. if (current_bus == pci_ctrl->first_busno)
  192. {
  193. pciauto_upper_iospc = pci_ctrl->io_resource.end + 1;
  194. pciauto_upper_memspc = pci_ctrl->mem_resources[0].end + 1;
  195. }
  196. sub_bus = current_bus;
  197. for (pci_devfn = 0; pci_devfn < 0xff; pci_devfn++)
  198. {
  199. /* Skip our host bridge */
  200. if ((current_bus == pci_ctrl->first_busno) && (pci_devfn == 0))
  201. continue;
  202. if (PCI_FUNC(pci_devfn) && !found_multi)
  203. continue;
  204. pciauto_bus.number = current_bus;
  205. pciauto_dev.devfn = pci_devfn;
  206. /* If config space read fails from this device, move on */
  207. if (pci_read_config_byte(dev, PCI_HEADER_TYPE, &header_type))
  208. continue;
  209. if (!PCI_FUNC(pci_devfn))
  210. found_multi = header_type & 0x80;
  211. pci_read_config_word(dev, PCI_VENDOR_ID, &vid);
  212. if (vid == 0xffff || vid == 0x0000) {
  213. found_multi = 0;
  214. continue;
  215. }
  216. pci_read_config_dword(dev, PCI_CLASS_REVISION, &pci_class);
  217. if ((pci_class >> 16) == PCI_CLASS_BRIDGE_PCI) {
  218. int iosave, memsave;
  219. pr_debug("PCI Autoconfig: Found P2P bridge, device %d\n",
  220. PCI_SLOT(pci_devfn));
  221. /* Allocate PCI I/O and/or memory space */
  222. pciauto_setup_bars(dev, PCI_BASE_ADDRESS_1);
  223. pciauto_prescan_setup_bridge(dev, current_bus, sub_bus,
  224. &iosave, &memsave);
  225. sub_bus = pciauto_bus_scan(pci_ctrl, sub_bus+1);
  226. pciauto_postscan_setup_bridge(dev, current_bus, sub_bus,
  227. &iosave, &memsave);
  228. pciauto_bus.number = current_bus;
  229. continue;
  230. }
  231. /*
  232. * Found a peripheral, enable some standard
  233. * settings
  234. */
  235. pci_read_config_dword(dev, PCI_COMMAND, &cmdstat);
  236. pci_write_config_dword(dev, PCI_COMMAND,
  237. cmdstat |
  238. PCI_COMMAND_IO |
  239. PCI_COMMAND_MEMORY |
  240. PCI_COMMAND_MASTER);
  241. pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x80);
  242. /* Allocate PCI I/O and/or memory space */
  243. pr_debug("PCI Autoconfig: Found Bus %d, Device %d, Function %d\n",
  244. current_bus, PCI_SLOT(pci_devfn), PCI_FUNC(pci_devfn));
  245. pciauto_setup_bars(dev, PCI_BASE_ADDRESS_5);
  246. pciauto_setup_irq(pci_ctrl, dev, pci_devfn);
  247. }
  248. return sub_bus;
  249. }